CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005
|
|
- Christiana Walker
- 5 years ago
- Views:
Transcription
1 CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005 EXPERIMENT 1 FUNDAMENTALS 1. GOALS : Lern how to develop cr lrm digitl circuit during which the following re introduced : CS2204 l fundmentls, nd Digitl Circuit Design fundmentls 2. L Work : 2.1. L Fundmentls : The L will tke plce in CIS L 227RH. Ech section will hve three hours per week in the l. The l is structured to develop term project y using the Xilinx Foundtion 4.2i softwre pckge nd the Digilent XLA5 FPGA (Field Progrmmle Gte Arry) ord. An FPGA chip is hrdwre progrmmle chip tht ehves like the circuit designed on the computer. The L will introduce current digitl design techniques nd tools. It will emulte n environment where engineers grouped together s tem, design projects lock y lock under the guidnce of project mnger. In CS2204, two students will work s tem. Tems re formed lpheticlly. Strting with the third l session, the focus will e on digitl circuit design. A succession of six design experiments will led to the completion of the term project. Ech experiment will mke use of erlier experiments. Experiment 1 nd 2 will introduce Xilinx softwre, Digilent hrdwre nd digitl circuit. Experiments 3, 4, 5 nd 6 re term project phses. Experiment 6 completes the term project. Experiments will e incresingly more complex. Students re strongly suggested tht they keep their experiment files nd directories well orgnized. The L will not ffect the term grde directly, ut l ttention grdes tht men student s motivtion (L ttendnce, rrivl/deprture to/from the L), concentrtion on the experiments, how much they re le to work with their temmtes nd whether their circuits work, will e given. The lst three design experiments will e reviewed nd comments will e mde Softwre Pckge nd the Hrdwre Bord : In order to develop circuits, softwre pckge from Xilinx, the Xilinx Foundtion 4.2i will e used. This softwre is different from the one which comes with the textook. The textook softwre will not e used. The design will e tested on prototyping ord which is the hrdwre students will use in the l. The ord, the Digilent XLA5 FPGA ord, mkes the design process nd verifying tht the design works more concrete. The Digilent ord contins n 84-pin SPARTAN FPGA chip. The circuit developed y using the softwre on the computer is downloded to the FPGA on the Digilent ord. Downloding mens the FPGA chip is hrdwre progrmmed. The progrmmed FPGA chip chrcteristics re often close to those of the gol : custom chip. Thus, if the circuit works correctly on the FPGA chip, one would quickly develop the custom chip from tht Getting Strted in the L : Xilinx Foundtion projects mke use of mny files s it is n industry softwre pckge. In order to help students keep trck of their files, it is decided tht students keep their files in one plce ccessile on cmpus : the LABS domin which corresponds to the S drive on l PCs. The S drive is on server ccessile from lptops nd ny PC t Poly. In order to log on to 227RH PCs, students need to hve n ccount for the LABS domin. Students who do not hve LABS domin ccount cn get it t the Informtion Systems (IS) help desk. Students hve to hve the ccount y the third l session. Hving the LABS domin ccount is not enough to ccess the S drive. This drive must e ctivted s well. If the drive is not ctive, students need to request it from the IS help desk too. The informtion Systems (IS) help desk : Polytechnic University Pge 1 of 6 Experiment 1- Fundmentls Ferury 8, 2005
2 Room : 337 RH help@duke.poly.edu (718) In cse students hve 227RH l relted prolems or would like to hve the l open, they contct the CS l supervisor Mr. Keni Yip t (718) , keni@poly.edu. His office is 225RH. The L softwre nd hrdwre, coupled with 3-hour l sessions nd widely ccessile project storge re re intended to provide students with semless digitl circuit development environment. 3. Developing Cr Set-Belt Alrm Circuit : In order to ccomplish the gols mentioned on pge 1, we will develop smll digitl circuit. The circuit is cr lrm circuit which sounds the lrm if the driver turns on the cr engine efore fstening the set elt. The first development cycle is the development cycle on computers which is the schemtic (determintion of components nd their wiring) sed on design fctors. If the circuit is simple, one cn completely design the circuit, the schemtic, on pper. Then, the schemtic is copied from the pper to the computer. If the circuit is complex, s mny rel-life circuits re, then the high-level design with locks nd sulocks is determined on pper. Then, the schemtic (component determintion nd wiring) is crried out on computers. Once the schemtic is complete, it is tested (simulted) on the computer to see if it works nd stisfies product requirements, otherwise it is modified. Thus, the development cycle on computers consists of three steps : logic design test modify The first step of the development cycle on computers/pper is clled logic design since logicl concepts re pplied to otin the schemtic. Logic design consists of otining the precise input-output reltionship of the circuit nd implementtion of the circuit Development Cycle on Pper/Computers : Logic Design : The Input-Output Reltionship : The input-output reltionship mens tht the circuit is viewed s lck ox with only its inputs nd outputs considered. Then, the outputs re relted to the inputs. Tht is, we try to determine when (for which input comintions)n output is 1 nd when it is 0. As lck ox, the cr set-elt lrm circuit is shown elow with two inputs nd one output : Pin 28 Pin 27 SW1 SW2 Cr Set-Belt Alrm Circuit lrm LD8 Pin 60 Input is connected to the engine. It is normlly 0. It is 1 when the driver turns on the engine. The input is emulted y switch 1, SW1, which is connected to pin 28 of the FPGA chip. Input is connected to the set elt. It is normlly 0, mening the elt is not fstened. It ecomes 1 if the set elt is fstened. The input is emulted y switch 2, SW2, which is connected to pin 27 of the FPGA chip. Output lrm is normlly 0, mening no lrm. When it is 1 the lrm sounds, i.e. the driver hs turned on the engine efore fstening the set elt. The output is emulted y LED light 8, LD8, which is connected to pin 60 of the FPGA chip. Note tht the pin ssignment of the FPGA chip is given on pge 8 of the Development Cycle on Bredords with FPGAs hndout. Polytechnic University Pge 2 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005
3 Textully, the opertion of the digitl circuit, or the input-output reltionship of the circuit cn e specified s follows : The lrm sounds when the engine is turned on AND the set elt is NOT fstened. An equl wy to descrie the input-output reltionship y concentrting on the output = 1 cse nd without ignoring the output = 0 cse is : The output is 1 when input is 1 AND input is 0. Soon we will see tht often we prefer to specify ll input nd output vlues when they re 1. Then, the new input/output reltionship is : The output is 1 when input is 1 AND input is NOT 1. We see tht in the textul description there re two sentences forming compound sttement y mens of the word AND : one sentence is the engine is turned on nd the other one is the set elt is NOT fstened. We lso see tht the second sentence is in the negtive form. Ech sentence specifies wht vlue ech input should hve to sound the lrm. The word tht comines the two sentences, AND, indictes if the input vlues should e 1 simult- Note tht this is the forml wy the textul reltionship is given in digitl circuit design. Another wy to descrie the input-output reltionship is y mens of truth tle tht shows the vlue of the output for ech input comintion : lrm The implementtion : The implementtion mens the schemtic (digitl circuit components nd their wiring) is determined sed on the given product gols (fctors) : speed, cost, power consumption, reliility, size, weight, etc. For Experiment 1, we will not focus on these gols to e le to concentrte on the components, wiring, the softwre, nd the hrdwre. Let s strt with the determintion of the components : the input-output reltionship indictes tht we need digitl circuit tht outputs 1 when it detects tht input is 1 nd input is 0. Wht we re given re components (digitl electronic circuits) nmed gtes. We re given AND, OR nd NOT gtes to use. We will implement the lrm circuit y using these gtes. Truth tles (input-output reltionships) nd symols of these gtes re s follows : AND OR NOT AND Gte AND OR Gte OR NOT Gte NOT An AND gte outputs 1 if oth outputs re 1 simultneously. An OR gte outputs 1, if t lest one of the inputs is 1. A NOT gte flips the input vlue. Note tht gte is the simplest digitl electronic circuit one hs. Which gtes cn e used nd how they re connected to ech other re sed on the textul description given ove : The lrm sounds when the engine is turned on AND the set elt is NOT fstened. Polytechnic University Pge 3 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005
4 neously or not. In this cse, they should e 1 simultneously. The second sentence indictes we need to hve the inverse vlue of the input to sound the lrm. Thus, we come to the conclusion tht the two circuit inputs re ANDed fter the second input is negted (NOT). Tht is, ll we hve to do is to use the gtes implied y the words AND nd NOT in the compound sentence. We cn determine the implementtion (which gtes, how mny of ech nd their wiring) in different wy! Implementing the circuit lso mens implementing the truth tle of the digitl circuit y using the truth tles of the gtes. The lrm circuit truth tle is similr to the AND gte truth tle, except the ottom two rows. An AND gte, coupled with NOT gte on the input would mke the ottom two rows of the two tles identicl. Tht is, the lrm circuit truth tle is implemented y the truth tles of the AND nd NOT gtes : y (NOT ) lrm ( AND y) ( AND NOT ) NOT = y AND y = AND NOT = lrm Since the input-output reltionship of the circuit, (its truth tle) is identicl to the truth tle of the cr set-elt lrm circuit, we conclude tht the ove circuit implements the lrm circuit. A digitl circuit like the one ove, consisting of gtes, is clled gte network. There is field in Mthemtics tht dels with textul description of digitl circuits : Truth-Functionl Clculus. It works on declrtive sentences connected y legl connectives, forming truth-functionl compound ( compound sttement). A declrtive sentence cn e either true or flse. The legl connectives cn e AND, OR, NOT, mong others. Ech sentence is ssigned vrile nd the connectives re represented y their symols. For exmple, AND is Λ, ORis nd NOT is. One cn then convert long text (truth-functionl compound) to truth functionl clculus expression with vriles nd symols only. For exmple, the ove lrm circuit expression is ( Λ ()). Truth-functionl clculus is concerned out when the compound (the text) is true (1, one) nd flse (0, zero). It does not cre out the mening of the sentences s long s they re true or flse. Also, truth functionl expression concentrtes on the input nd output vlues tht re equl 1 s it is cler in the ove truth functionl expression. Converting declrtive sentences nd connectives is strightforwrd, only for simple circuits, since the textul inputoutput reltionship is short. Rel-life prolems re complex nd their textul description is very difficult to convert to n expression y mens of truth-functionl clculus. Now tht we know wht is in the lck ox on pge 2, we end the gte network design of the lrm circuit on pper. We re now redy to move the design to the computer : drwing the schemtic circuit on computer, using Xilinx Foundtion softwre. For this, we will copy the circuit digrm from pper to computer, then simulte it nd modify it if necessry. The simultion of the circuit is done on computer. Modifiction is the chnge of the design sed on test results if errors re discovered. After the modifiction the circuit is simulted gin to verify the circuit modifiction is correct. Often logic design on pper is interleved with or done concurrently with logic design on computers, especilly for complex circuits. Therefore, strting with Experiment 4, we will stop designing them sequentilly. Design on pper will e concurrent with design on computer Circuit Design on the Computer (Xilinx Softwre) : Follow the steps given elow to develop the circuit. Note tht throughout the semester, steps to go through will e given where ullet symol such s tht shows new step. Key presses nd mouse selections re shown in old. Also, throughout the semester, the hndouts will e prepred y ssuming tht students use their S drive s their project storge spce. If students re not le to ccess the S drive, for exmple, in plce where no network connection is possile, they should use the defult Xilinx project directory which hs the pth \Fndtn\ctive\projects\... Lter, students should move their project to the S drive when they estlish the connection. Another convention to rememer is tht when we sy click the mouse, we men clicking the left mouse utton. The right mouse click will e explicitly mentioned. Polytechnic University Pge 4 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005
5 First tsk efore strting new project : In order to keep our designs orgnized, we need to hve them stored with respect to their experiment numer. For ech experiment, we will hve directory on the S drive. Therefore, for the current experiment, we will do the following : Crete new directory nmed exp1 under cs2204. We will hve our lrm circuit project under this exp1 directory. Strting the Xilinx softwre : On your PC, strt the Xilinx Project Mnger y doing one of the two elow : Doule click on the Xilinx Project Mnger icon, Go through menu selections : Strt (on the lower left corner) -> Progrms -> Xilinx Foundtion 4.2 -> Project Mnger. You will see dilogue ox titled Getting Strted in the foreground while the Project Mnger window is in the ckground. Creting New Project : Since we hve not designed ny project yet, we will strt with creting new project. In the Getting Strted dilogue ox, click on the rdio utton with lel Crete New project. Click OK A dilogue ox with the nme New Project will pop up. In the dilogue ox, enter lrm s the nme of your design. We will chnge the directory of the project to the exp1 directory on the S drive : Click on the Browse... utton nd select the project directory (your working directory) s the exp1 directory. All your lrm circuit files will e sved there. Click on the rdio utton with lel Schemtic since we will hve schemtic design, not n HDL design. Finlly, there re three list oxes on the lst row. They re out the FPGA chip specificlly. We hve to mke sure tht the choices re Sprtn, S10PC84, nd 3. Click on the rrow in the Flow re nd scroll until you see Sprtn. Select it. Click on the rrow in the re to the right nd scroll down until you see S10PC84. Select it. Click on the rrow in the re to the right nd select speed 3 for the FPGA. Press OK. The computer shows the Project Mnger window with three pnels. The upper right one which we will constntly use, shows the flow of the project until it completes. We re now redy to open the Schemtic editor to egin the design of the lrm circuit. The schemtic design Click on the Schemtic Editor utton on the upper right pnel to strt the schemtic editor. A lnk design sheet (window) will e shown. At this time, when the schemtic editor is strted, it is lwys in the Select nd Drg mode. In order to plce components (such s n AND gte) on the design sheet, we need to chnge the mode to the Sym- Polytechnic University Pge 5 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005
6 ols mode. This cn e done in three different wys : Click on the Symols toolox icon on the left side of the screen : Pull down the menu Mode then select Symols, or Press key F3. The SC Symols window ppers on the right side. This is the lirry of components we will use this semester. Scroll down the list to ecome fmilir with it : Let s plce one of the two components, the 2-input AND gte on the sheet : Click on the AND2 component inside the window on the lirry list. Now n AND2 gte is ttched to your mouse nd you cn plce it on the design sheet wherever you wnt. Drg the mouse to the left nd click it in the middle of the sheet. From this point on follow the steps shown y the professor to complete the implementtion, testing nd downloding. CONTACTS : 1) Students cn see the professor nd teching djuncts (TAs), out the lectures, homework, nd l experiments. 2) Professor s contct informtion : Room : 114 LC (718) Fx : (718) hldun@photon.poly.edu Open-door policy to see the professor. If the door is closed, he might e in the l. Present in the l : Mondys (4-6), Wednesdys (3-5) nd Fridys (2-4) 3) The TAs of the course re Nikhil Joshi, Spn Shenoy, Jeff To, Bo Yng nd Peng Yo. 4) All hndout nd l files re t the course we site : 5) When short-term prolems re encountered in PC ls, students re dvised to contct : help@duke.poly.edu or (718) or go to Room : 337 RH. For CS2204 l relted issues nd to hve the l open, students need to contct the CIS l supervisor Mr. Keni Yip t (718) , keni@poly.edu. His office is 225RH For longer-term prolems in PC ls nd ny other mtter, students should not hesitte to contct the professor nd TAs. Polytechnic University Pge 6 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005
CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN fall 2008
CS224 DIGITAL LOGIC & STATE MACHINE DESIGN fll 28 STAND ALONE XILINX PROJECT 2-TO- MULTIPLEXER. Gols : Lern how to develop stnd lone 2-to- multiplexer () Xilinx project during which the following re introduced
More informationMath Circles Finite Automata Question Sheet 3 (Solutions)
Mth Circles Finite Automt Question Sheet 3 (Solutions) Nickols Rollick nrollick@uwterloo.c Novemer 2, 28 Note: These solutions my give you the nswers to ll the prolems, ut they usully won t tell you how
More informationStudent Book SERIES. Patterns and Algebra. Name
E Student Book 3 + 7 5 + 5 Nme Contents Series E Topic Ptterns nd functions (pp. ) identifying nd creting ptterns skip counting completing nd descriing ptterns predicting repeting ptterns predicting growing
More informationDigital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid
Digitl Design Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design, First Edition, y, John Wiley nd Sons Pulishers, 27. http://www.ddvhid.com Copyright 27 Instructors of courses
More informationSequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12
9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering http://www.eee.hku.hk/~engg5 Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil
More informationThe Math Learning Center PO Box 12929, Salem, Oregon Math Learning Center
Resource Overview Quntile Mesure: Skill or Concept: 300Q Model the concept of ddition for sums to 10. (QT N 36) Model the concept of sutrction using numers less thn or equl to 10. (QT N 37) Write ddition
More informationmac profile Configuration Guide Adobe Photoshop CS/CC Sawgrass Virtuoso SG400/SG800 Macintosh v
mc profile Mcintosh 10.5-10.10 Configurtion Guide Adoe Photoshop CS/CC Swgrss Virtuoso SG400/SG800 v20150427 Configurtion Guide - Photoshop CS/CC Swgrss SG400/800 Before proceeding, ensure the correct
More information& Y Connected resistors, Light emitting diode.
& Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd
More informationStudent Book SERIES. Fractions. Name
D Student Book Nme Series D Contents Topic Introducing frctions (pp. ) modelling frctions frctions of collection compring nd ordering frctions frction ingo pply Dte completed / / / / / / / / Topic Types
More informationEE Controls Lab #2: Implementing State-Transition Logic on a PLC
Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre
More information510 Series Color Jetprinter
510 Series Color Jetprinter User s Guide for Windows Setup trouleshooting A checklist to find solutions to common setup prolems. Printer overview Lern out the printer prts nd the printer softwre. Printing
More informationCS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates
Bsic Logic Gtes : Computer Architecture I Boolen Algebr Instructor: Prof. Bhgi Nrhri Dept. of Computer Science Course URL: www.ses.gwu.edu/~bhgiweb/cs35/ Digitl Logic Circuits We sw how we cn build the
More informationKirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):
SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween
More informationFOMA M702iG Manual for Data Communication
FOMA M702iG Mnul for Dt Communiction Dt Communictions... 1 Before Using... 2 Prepring for Dt Communiction... 3 Instlling the Communiction Configurtion Files (Drivers)... 4 Connecting the FOMA Hndset nd
More informationGeometric quantities for polar curves
Roerto s Notes on Integrl Clculus Chpter 5: Bsic pplictions of integrtion Section 10 Geometric quntities for polr curves Wht you need to know lredy: How to use integrls to compute res nd lengths of regions
More informationHomework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week
Announcements Homework #1 due Mondy t 6pm White drop ox in Student Lounge on the second floor of Cory Tuesdy ls cncelled next week Attend your other l slot Books on reserve in Bechtel Hmley, 2 nd nd 3
More informationECE Digital Logic (Labs) ECE 274 Digital Logic. ECE Digital Logic (Textbook) ECE Digital Logic (Optional Textbook)
ECE 74 Digitl Logic ECE 74 - Digitl Logic (Ls) Instructor: Romn Lysecky, rlysecky@ece.rizon.edu Office Hours: MW :-: PM, ECE Lecture: MW :-: PM, ILC 4 Course Wesite: http://www.ece.rizon.edu/~ece74/ TAs:
More informationPROGRAMMING MANUAL MTMA/01 MTMV/01 FB00329-EN
RMMING MNUL MTM/01 MTMV/01 FB00329-EN Generl precutions Red the instructions crefully efore eginning the instlltion nd crry out the ctions s specified y the mnufcturer. The instlltion, progrmming, commissioning
More information(1) Non-linear system
Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems
More informationExercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION
Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You
More informationDiscontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)
ICs for Cssette, Cssette Deck ANN, ANN Puse Detection s of Rdio Cssette, Cssette Deck Overview The ANN nd the ANN re the puse detection integrted circuits which select the progrm on the cssette tpe. In
More informationAquauno Select MINUTES. (duration) FREQUENCY LED. OFF 8h AQUAUNO SELECT 5 MIN FREQUENCY. the timer is being programmed;
Aquuno Select Pg. INSTALLATION. Attch the timer to cold wter tp, following these simple instructions. Do not instll the timer in pit or vlve ox, elow ground level or indoors. Do not use the timer with
More informationPatterns and Algebra
Student Book Series D Mthletis Instnt Workooks Copyright Series D Contents Topi Ptterns nd funtions identifying nd reting ptterns skip ounting ompleting nd desriing ptterns numer ptterns in tles growing
More informationDataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)
The slides contin revisited mterils from: Peter Mrwedel, TU Dortmund Lothr Thiele, ETH Zurich Frnk Vhid, University of liforni, Riverside Dtflow Lnguge Model Drsticlly different wy of looking t computtion:
More informationPatterns and Relationships
Series Techer Ptterns nd Reltionships opyright 009 3P Lerning. All rights reserved. First edition printed 009 in Austrli. A ctlogue record for this ook is ville from 3P Lerning Ltd. ISBN 978-1-91860-3-4
More informationAlgebra Practice. Dr. Barbara Sandall, Ed.D., and Travis Olson, M.S.
By Dr. Brr Sndll, Ed.D., Dr. Melfried Olson, Ed.D., nd Trvis Olson, M.S. COPYRIGHT 2006 Mrk Twin Medi, Inc. ISBN 978-1-58037-754-6 Printing No. 404042-EB Mrk Twin Medi, Inc., Pulishers Distriuted y Crson-Dellos
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
Hll Ticket No Question Pper Code: AEC009 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigl, Hyderd - 500 043 MODEL QUESTION PAPER Four Yer B.Tech V Semester End Exmintions, Novemer - 2018 Regultions:
More informationLecture 20. Intro to line integrals. Dan Nichols MATH 233, Spring 2018 University of Massachusetts.
Lecture 2 Intro to line integrls Dn Nichols nichols@mth.umss.edu MATH 233, Spring 218 University of Msschusetts April 12, 218 (2) onservtive vector fields We wnt to determine if F P (x, y), Q(x, y) is
More informationTopic 20: Huffman Coding
Topic 0: Huffmn Coding The uthor should gze t Noh, nd... lern, s they did in the Ark, to crowd gret del of mtter into very smll compss. Sydney Smith, dinburgh Review Agend ncoding Compression Huffmn Coding
More informationExample. Check that the Jacobian of the transformation to spherical coordinates is
lss, given on Feb 3, 2, for Mth 3, Winter 2 Recll tht the fctor which ppers in chnge of vrible formul when integrting is the Jcobin, which is the determinnt of mtrix of first order prtil derivtives. Exmple.
More information1 tray of toffee 1 bar of toffee. 10 In the decimal number, 0 7, the 7 refers to 7 tenths or
Chpter 3 Deciml Numers Do you know wht DECIMAL is? In chpter, we delt with units, s, 0 s nd 00 s. When you tke single unit nd divide it into (or 0 or 00) its, wht we then hve re deciml frctions of whole
More informationSynchronous Generator Line Synchronization
Synchronous Genertor Line Synchroniztion 1 Synchronous Genertor Line Synchroniztion Introduction One issue in power genertion is synchronous genertor strting. Typiclly, synchronous genertor is connected
More informationSolutions to exercise 1 in ETS052 Computer Communication
Solutions to exercise in TS52 Computer Communiction 23 Septemer, 23 If it occupies millisecond = 3 seconds, then second is occupied y 3 = 3 its = kps. kps If it occupies 2 microseconds = 2 6 seconds, then
More informationCHAPTER 2 LITERATURE STUDY
CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:
More informationSOLVING TRIANGLES USING THE SINE AND COSINE RULES
Mthemtics Revision Guides - Solving Generl Tringles - Sine nd Cosine Rules Pge 1 of 17 M.K. HOME TUITION Mthemtics Revision Guides Level: GCSE Higher Tier SOLVING TRIANGLES USING THE SINE AND COSINE RULES
More informationMagnetic monopole field exposed by electrons
Mgnetic monopole field exposed y electrons A. Béché, R. Vn Boxem, G. Vn Tendeloo, nd J. Vereeck EMAT, University of Antwerp, Groenenorgerln 171, 22 Antwerp, Belgium Opticl xis Opticl xis Needle Smple Needle
More informationOn the Description of Communications Between Software Components with UML
On the Description of Communictions Between Softwre Components with UML Zhiwei An Dennis Peters Fculty of Engineering nd Applied Science Memoril University of Newfoundlnd St. John s NL A1B 3X5 zhiwei@engr.mun.c
More informationABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC
User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...
More information(1) Primary Trigonometric Ratios (SOH CAH TOA): Given a right triangle OPQ with acute angle, we have the following trig ratios: ADJ
Tringles nd Trigonometry Prepred y: S diyy Hendrikson Nme: Dte: Suppose we were sked to solve the following tringles: Notie tht eh tringle hs missing informtion, whih inludes side lengths nd ngles. When
More informationRegular languages can be expressed as regular expressions.
Regulr lnguges cn e expressed s regulr expressions. A generl nondeterministic finite utomton (GNFA) is kind of NFA such tht: There is unique strt stte nd is unique ccept stte. Every pir of nodes re connected
More informationMAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES
MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion
More informationHow to remove BRNS/BRFS series from a PWB
Applictions mnul for BRNS/BRFS series How to remove BRNS/BRFS series from PWB VER1.0 Applictions Mnul BRNS/BRFS series Pge 1. Overview 1-1 1.1 Overview 1-1 2. Preprtion 2-1 2.1 2.2 2.3 Removl tool Adhesive
More informationAbacaba-Dabacaba! by Michael Naylor Western Washington University
Abcb-Dbcb! by Michel Nylor Western Wshington University The Abcb structure shows up in n mzing vriety of plces. This rticle explores 10 surprising ides which ll shre this pttern, pth tht will tke us through
More informationSection 6.1 Law of Sines. Notes. Oblique Triangles - triangles that have no right angles. A c. A is acute. A is obtuse
Setion 6.1 Lw of Sines Notes. Olique Tringles - tringles tht hve no right ngles h is ute h is otuse Lw of Sines - If is tringle with sides,, nd, then sin = sin = sin or sin = sin = sin The miguous se (SS)
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationFitting & User Instructions
Issue 03 Alexnder Universl Furniture Risers Note: These frmes require the ddition of n ttchment. (See pges 4 - ) Bse Frme Mrk Bse Frme Mrk Fitting & User Instructions These instructions pply to the rising
More informationMOS Transistors. Silicon Lattice
rin n Width W chnnel p-type (doped) sustrte MO Trnsistors n Gte Length L O 2 (insultor) ource Conductor (poly) rin rin Gte nmo trnsistor Gte ource pmo trnsistor licon sustrte doped with impurities dding
More informationModule 9. DC Machines. Version 2 EE IIT, Kharagpur
Module 9 DC Mchines Version EE IIT, Khrgpur esson 40 osses, Efficiency nd Testing of D.C. Mchines Version EE IIT, Khrgpur Contents 40 osses, efficiency nd testing of D.C. mchines (esson-40) 4 40.1 Gols
More informationMixed CMOS PTL Adders
Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções 14 20 de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde
More informationCHAPTER 3 AMPLIFIER DESIGN TECHNIQUES
CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.
More informationarxiv: v1 [cs.cc] 29 Mar 2012
Solving Mhjong Solitire ords with peeking Michiel de Bondt rxiv:1203.6559v1 [cs.cc] 29 Mr 2012 Decemer 22, 2013 Astrct We first prove tht solving Mhjong Solitire ords with peeking is NPcomplete, even if
More informationMulti-beam antennas in a broadband wireless access system
Multi-em ntenns in rodnd wireless ccess system Ulrik Engström, Mrtin Johnsson, nders Derneryd nd jörn Johnnisson ntenn Reserch Center Ericsson Reserch Ericsson SE-4 84 Mölndl Sweden E-mil: ulrik.engstrom@ericsson.com,
More informationSeries. Teacher. Numbers
Series B Techer Copyright 2009 3P Lerning. All rights reserved. First edition printed 2009 in Austrli. A ctlogue record for this book is vilble from 3P Lerning Ltd. ISBN 978-1-921860-17-1 Ownership of
More informationClick Here to BEGIN: Independent Agent Contracting Link
LOA Guide : Getting Contrcted with AllWell Centene Medicre Advntge This guide is for ll gents who ssign commissions to n gency. You will NOT need to provide ny gency informtion in this contrcting; s ll
More informationTo provide data transmission in indoor
Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut
More informationISM-PRO SOFTWARE DIGITAL MICROSCOPE OPERATION MANUAL
MN-ISM-PRO-E www.insize.om ISM-PRO SOFTWARE DIGITAL MICROSCOPE OPERATION MANUAL Desription Clik Next. As the following piture: ISM-PRO softwre is for ISM-PM00SA, ISM-PM600SA, ISM- PM60L digitl mirosopes.
More informationABOUT THIS MANUAL ABOUT THIS MANUAL
ABOUT THIS MANUAL ABOUT THIS MANUAL This mnul provides detils on IQ Designer, which is ville with the upgrde. Mke sure tht the mchine hs een upgrded to the most recent version. When you find this icon
More informationECE 274 Digital Logic
ECE - Digitl Logic (Textbook - Required) ECE Digitl Logic Instructor: Romn Lysecky, rlysecky@ece.rizon.edu Office Hours: TBA, ECE F Lecture: MWF :-: PM, ILC Course Website: http://www.ece.rizon.edu/~ece/
More informationASSEMBLY INSTRUCTIONS
ASSEMBLY INSTRUCTIONS Multi Line 6 x8 255x193x203cm / 100 1 /2 x76 x80 Poly-Tex, Inc. PO Box 458 27725 Dnville Avenue Cstle Rock, MN 55010 We Site: www.poly-tex.com English - 69717 Hoy Greenhouse Service
More informationOperation Manual. Addendum. Embroidery Machine. Product Code: 884-T13
Emroidery Mchine Opertion Mnul Addendum Product Code: 884-T13 Be sure to red this document efore using the mchine. We recommend tht you keep this document nery for future reference. ABOUT THIS MANUAL ABOUT
More informationArduino for Model Railroaders
Steve Mssikker Arduino for Model Rilroders Ornge Book Protocol 2 Full Description November 28 Tble of contents Dontors Documenttion Kit V.4-8 Pge 2 I wnt to tke the time to sincerely thnk you for your
More informationECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design
ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers,
More informationMONOCHRONICLE STRAIGHT
UPDATED 09-2010 HYDROCARBON Hydrocrbon is poncho-style cowl in bulky-weight yrn, worked in the round. It ws designed to be s prcticl s it is stylish, with shping tht covers the neck nd shoulders nd the
More informationAlgorithms for Memory Hierarchies Lecture 14
Algorithms for emory Hierrchies Lecture 4 Lecturer: Nodri Sitchinv Scribe: ichel Hmnn Prllelism nd Cche Obliviousness The combintion of prllelism nd cche obliviousness is n ongoing topic of reserch, in
More informationTriangles and parallelograms of equal area in an ellipse
1 Tringles nd prllelogrms of equl re in n ellipse Roert Buonpstore nd Thoms J Osler Mthemtics Deprtment RownUniversity Glssoro, NJ 0808 USA uonp0@studentsrownedu osler@rownedu Introduction In the pper
More informationRe: PCT Minimum Documentation: Updating of the Inventory of Patent Documents According to PCT Rule 34.1
C. SCIT 2508 00 August 10, 2000 Re: PCT Minimum Documenttion: Updting of the Inventory of Ptent Documents According to PCT Rule 34.1 Sir, Mdm, The current version of the Inventory of Ptent Documents for
More informationMake Your Math Super Powered
Mke Your Mth Super Powered: Use Gmes, Chllenges, nd Puzzles Where s the fun? Lern Mth Workshop model by prticipting in one nd explore fun nocost/low-cost gmes nd puzzles tht you cn esily bring into your
More informationMcAfee Network Security Platform
M-6030 Sensor Quik Strt Guide Revision B MAfee Network Seurity Pltform This Quik Strt Guide explins how to quikly set up nd tivte your MAfee Network Seurity Pltform [formerly MAfee IntruShield ] M-6030
More informationBirka B22: threaded in variation
Tblet Weving: 4-Hole Ptterns Stringcrfter The chrt, fining your wy roun the pttern, n suggestions for viking style bris for rnks in the Drchenwl Acemy of Defence You will nee: 22 crs 1 repet 88 Thres:
More informationEfficient and Resilient Key Discovery based on Pseudo-Random Key Pre-Deployment
Efficient nd Resilient Key Discovery sed on Pseudo-Rndom Key Pre-Deployment p. 1 Efficient nd Resilient Key Discovery sed on Pseudo-Rndom Key Pre-Deployment Roerto Di Pietro, Luigi V. Mncini, nd Alessndro
More informationUnderstanding Basic Analog Ideal Op Amps
Appliction Report SLAA068A - April 2000 Understnding Bsic Anlog Idel Op Amps Ron Mncini Mixed Signl Products ABSTRACT This ppliction report develops the equtions for the idel opertionl mplifier (op mp).
More informationGeneral Instructions 03HEL1010DDFW-V3. Please retain product label and instructions for future reference. 10x10 Helios Summer House
Generl Instructions Plese retin product lel nd instructions for future reference 03HEL1010DDFW-V3 x2 All uilding s should e erected y two dults Winter = High Moisture = Expnsion Summer = Low Moisture =
More informationFirst Round Solutions Grades 4, 5, and 6
First Round Solutions Grdes 4, 5, nd 1) There re four bsic rectngles not mde up of smller ones There re three more rectngles mde up of two smller ones ech, two rectngles mde up of three smller ones ech,
More informationDesign and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram
INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) 1497 152 SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S953-248(3)67111-3 Design nd implementtion of high-speed it-seril SFQ dder sed on the
More informationDirect Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28.
P U Z Z L E R If ll these pplinces were operting t one time, circuit reker would proly e tripped, preventing potentilly dngerous sitution. Wht cuses circuit reker to trip when too mny electricl devices
More informationSamantha s Strategies page 1 of 2
Unit 1 Module 2 Session 3 Smnth s Strtegies pge 1 of 2 Smnth hs been working with vriety of multiplition strtegies. 1 Write n expression to desribe eh of the sttements Smnth mde. To solve 18 20, I find
More informationChapter 2 Literature Review
Chpter 2 Literture Review 2.1 ADDER TOPOLOGIES Mny different dder rchitectures hve een proposed for inry ddition since 1950 s to improve vrious spects of speed, re nd power. Ripple Crry Adder hve the simplest
More informationMisty. Sudnow Dot Songs
Sudnow Dot Songs isty T The Dot Song is nottionl system tht depicts voiced chords in wy where the non-music reder cn find these firly redily. But the Dot Song is not intended be red, not s sight reder
More informationMcAfee Network Security Platform
M-2750 Sensor Quik Strt Guide Revision B MAfee Network Seurity Pltform This Quik Strt Guide explins how to quikly set up nd tivte your MAfee Network Seurity Pltform M-2750 Sensor in in-line mode. Cling
More informationNORTH STAR 4-PANEL PATIO DOOR ASSEMBLY INSTRUCTIONS
40684 Talbot Line, St. Thomas, Ont., N5P 3T Phone: (519) 637-7899 Toll Free: (800) 65-5701 Fax: (519) 637-3403 Web Site: www.northstarwindows.com NORTH STR 4-PNEL PTIO DOOR SSEMLY INSTRUCTIONS (JN/P-Dr04/4Panssy
More informationMATH 118 PROBLEM SET 6
MATH 118 PROBLEM SET 6 WASEEM LUTFI, GABRIEL MATSON, AND AMY PIRCHER Section 1 #16: Show tht if is qudrtic residue modulo m, nd b 1 (mod m, then b is lso qudrtic residue Then rove tht the roduct of the
More informationTUR DOORS SHOWER DOORS
TUR DOORS SHOWER DOORS INSTALLATION INSTRUCTIONS TUB DOORS: LBTDB6062 SHOWER DOORS: LBSDB4876 LBSDB6076 VERSION: 3.2 PREPARATION FOR INSTALLATION TUB DOORS SHOWER DOORS PREPARATION FOR INSTALLATION READ
More informationMETHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin
METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN Inventor: Brin L. Bskin 1 ABSTRACT The present invention encompsses method of loction comprising: using plurlity of signl trnsceivers to receive one or
More informationArea-Time Efficient Digit-Serial-Serial Two s Complement Multiplier
Are-Time Efficient Digit-Seril-Seril Two s Complement Multiplier Essm Elsyed nd Htem M. El-Boghddi Computer Engineering Deprtment, Ciro University, Egypt Astrct - Multipliction is n importnt primitive
More informationEnglish Printed in Taiwan XG
COVER 1-4 C M Y K English Printed in Tiwn XG0091-001 Congrtultions on choosing our product! Thnk you very much for purchsing our product. To otin the est performnce from this device nd to ensure sfe nd
More informationECE 274 Digital Logic Fall 2009 Digital Design
igitl Logic ll igitl esign MW -:PM, IL Romn Lysecky, rlysecky@ece.rizon.edu http://www.ece.rizon.edu/~ece hpter : Introduction Slides to ccompny the textbook igitl esign, irst dition, by rnk Vhid, John
More informationGEH-2024E Supersedes GEH INSTRUCTIONS MULTICONTACT AUXILARY RELAY. TYPE HFASl. www. ElectricalPartManuals. com. GENERAL fl ELECTRIC
INSTRUCTIONS MULTICONTACT AUXILARY RELAY TYPE HFASl GENERAL fl ELECTRIC E Supersedes 0 MULTICONTACT AUXILIARY RELAY TYPE HFASl DESCRIPTION The HFASl relys re instntneous, hinged-rmture, multi-contct, uxiliry
More informationEnergy Harvesting Two-Way Channels With Decoding and Processing Costs
IEEE TRANSACTIONS ON GREEN COMMUNICATIONS AND NETWORKING, VOL., NO., MARCH 07 3 Energy Hrvesting Two-Wy Chnnels With Decoding nd Processing Costs Ahmed Arf, Student Member, IEEE, Abdulrhmn Bknin, Student
More informationApplication Note. Differential Amplifier
Appliction Note AN367 Differentil Amplifier Author: Dve n Ess Associted Project: Yes Associted Prt Fmily: CY8C9x66, CY8C7x43, CY8C4x3A PSoC Designer ersion: 4. SP3 Abstrct For mny sensing pplictions, desirble
More informationThe Discussion of this exercise covers the following points:
Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI
More informationUniversity of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 4143/5195 Electrical Machinery Fall 2009
Problem 1: Using DC Mchine University o North Crolin-Chrlotte Deprtment o Electricl nd Computer Engineering ECGR 4143/5195 Electricl Mchinery Fll 2009 Problem Set 4 Due: Thursdy October 8 Suggested Reding:
More informationEQ: What are the similarities and differences between matrices and real numbers?
Unit 4 Lesson 1 Essentil Question Stndrds Objectives Vocbulry Mtrices Mtrix Opertions Wht re the similrities nd differences between mtrices nd rel numbers? M.ALGII.2.4 Unit 4: Lesson 1 Describe how you
More informationSpotted at APA. Top Points this week. Spring f ro. Year 7. Year 8. Year 9. Year 10. Year 11. Student Newsletter ~
Spring 2017 Top Points this week Yer 7 ly l x Mo Ale Yer 8 ict is Le w ed Be n Yer 9 sh er Ele Du ej on e Yer 10 Yer 11 ri em Me Another very busy week in the cdemy hs just gone by s we hd our APA World
More informationDomination and Independence on Square Chessboard
Engineering nd Technology Journl Vol. 5, Prt, No. 1, 017 A.A. Omrn Deprtment of Mthemtics, College of Eduction for Pure Science, University of bylon, bylon, Irq pure.hmed.omrn@uobby lon.edu.iq Domintion
More informationA Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM
A ovel Bck EMF Zero Crossing Detection of Brushless DC Motor Bsed on PWM Zhu Bo-peng Wei Hi-feng School of Electricl nd Informtion, Jingsu niversity of Science nd Technology, Zhenjing 1003 Chin) Abstrct:
More informationDigital Design. Chapter 1: Introduction
Digitl Design Chpter : Introduction Slides to ccompny the textbook Digitl Design, with RTL Design, VHDL, nd Verilog, 2nd Edition, by, John Wiley nd Sons Publishers, 2. http://www.ddvhid.com Copyright 2
More informationISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5
21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies
More informationOpen Access A Novel Parallel Current-sharing Control Method of Switch Power Supply
Send Orders for Reprints to reprints@enthmscience.e 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, 170-177 Open Access A Novel Prllel Current-shring Control Method of Switch Power Supply
More informationPerformance Monitoring Fundamentals: Demystifying Performance Assessment Techniques
Simplifying PID Control. Optimizing Plnt Performnce. Performnce Monitoring Fundmentls: Demystifying Performnce Assessment Techniques Roert C. Rice, PhD Rchelle R. Jyringi Dougls J. Cooper, PhD Control
More information