Back to the Future: Digital Circuit Design in the FinFET Era

Transcription

1 Copyright 2017 Americn Scientific Pulishers All rights reserved Printed in the United Sttes of Americ Journl of Low Power Electronics Vol. 13, 1 18, 2017 Bck to the Future: Digitl Circuit Design in the FinFET Er Xinfei Guo, Vihv Verm, Ptrici Gonzlez-Guerrero, Sergiu Mosnu, nd Mirce R. Stn Deprtment of Electricl nd Computer Engineering, University of Virgini, Chrlottesville, VA, 22904, USA (Received: 3 June 2017; Accepted: 13 June 2017) It hs een lmost decde since FinFET devices were introduced to full production; they llowed scling elow 20 nm, thus helping to extend Moore s lw y precious decde with nother decde likely in the future when scling to 5 nm nd elow. Due to superior electricl prmeters nd unique structure, these 3-D trnsistors offer significnt performnce improvements nd power reduction compred to plnr CMOS devices. As we re entering into the su-10 nm er, FinFETs hve ecome dominnt in most of the high-end products; s the trnsition from plnr to FinFET technologies is still ongoing, it is importnt for digitl circuit designers to understnd the chllenges nd opportunities rought in y the new technology chrcteristics. In this pper, we study these spects from the device to the circuit level, nd we mke detiled comprisons cross multiple technology nodes rnging from conventionl ulk to dvnced plnr technology nodes such s Fully Depleted Silicon-on-Insultor (FDSOI), to FinFETs. In the simultions we used oth stte-of-rt industry-stndrd models for current nodes, nd lso predictive models for future nodes. Our study shows tht esides the performnce nd power enefits, FinFET devices show significnt reduction of short-chnnel effects nd extremely low lekge, nd mny of the electricl chrcteristics re close to idel s in old long-chnnel technology nodes; FinFETs seem to hve put scling ck on trck! However, the comintion of the new device structures, doule/multi-ptterning, mny more complex rules, nd unique therml/reliility ehviors re creting new technicl chllenges. Moving forwrd, FinFETs still offer right future nd re n indispensle technology for wide rnge of pplictions from high-end performnce-criticl computing to energy-constrint moile pplictions nd smrt Internet-of-Things (IoT) devices. Keywords: FinFET, FDSOI, Plnr, VLSI, Scling, Sizing, Digitl Design. 1. INTRODUCTION The continuous scling of plnr CMOS devices hs delivered incresing performnce nd trnsistor densities. However, it lso reched point where incresed lekge current, fluctution of device chrcteristics nd short chnnel effects ecme serious ostcles to further scling. This ws minly ecuse deeply-scled plnr devices ecme incresingly influenced y the drin potentil s the gte lost the ility to fully control the chnnel; this led to trnsistors tht were never fully off nd leked continuously. To solve this prolem, gte oxides were ggressively thinned nd high-k dielectric gte mterils were dopted to increse the gte-chnnel cpcitnce, ut the gte-relted issues, such s gte lekge nd gte-induced drin lekge (GIDL) incresed. 1,2 FinFET Author to whom correspondence should e ddressed. Emil: xg2dt@virgini.edu devices ecme ttrctive for su-30 nm nodes 3,4 ecuse of their unique chnnel structure with good gte control tht enles much improved short chnnel control, thus requiring little or no doping in the chnnel. The threshold voltge V t cn e scled down in FinFETs for oth improved device performnce nd much lower opertion voltge. Lower chnnel doping lso reduces dopnt ion scttering, thus leding to etter drive currents nd decreses rndom dopnt fluctutions (RDF). 5 7 FinFETs ck-end-of-line (BEOL) friction is fully comptile with plnr devices in oth ulk nd SOI vrieties, which reduces the need for new, FinFET-specific developments in tht re. However, the introduction of FinFETs hs rought few chnges nd chllenges in digitl circuit design due to their unique gte structure nd electricl properties. This hs lso impcted the circuit design decisions nd some of the ville design trdeoffs. For exmple, FinFET devices hve significnt mount of prsitics J. Low Power Electron. 2017, Vol. 13, No /2017/13/001/018 doi: /jolpe

2 Bck to the Future: Digitl Circuit Design in the FinFET Er tht need to e modeled precisely nd e crefully considered in the lyout of ll circuits, especilly in SRAM nd nlog circuits. From circuit design spect, in ddition to the extr effort needed to ddress the impct of prsitics t the lyout level, new circuit techniques re needed in the re of ody-ising nd memory red/write ssist in SRAMs to replce techniques tht worked well in plnr ut re inefficient for FinFET. The doule/multiptterning lso requires tool vendors nd designers to work together to mke sure the lyout coloring is correct (colors refer to different exposures of the sme lyer while performing multiptterning). New constrints hve een dded to FinFET design, such s width quntiztion nd selfheting effects, for which designers need to mke erly decisions in the design cycle. In this pper, we nlyze these spects t oth the device nd circuit levels. To study these chllenges, we simulte cross multiple technology nodes which cover wide rnge of gte lengths nd lso sustrtes including oth SOI nd Bulk. For FinFET, we simulte with oth 1 nm industry-stndrd node nd 7 nm predictive node. This pper ims to provide detiled nlysis nd glol view of how FinFETs differ from previous technology nodes nd wht re the implictions on circuit design. We restrict our focus to digitl circuits, ut severl of the findings cn e pplied to nlog design s well. The pper is orgnized s follows. Section 2 discusses the FinFET sics nd how FinFETs re different from plnr technologies t the device level. We ddress the chnges nd chllenges FinFETs hve introduced for circuit design in Section 3. In Section 4, we summrize ll the chllenges from the designers perspective. Section 5 concludes the pper. 2. FINFET DEVICE 2.1. Scling nd Sizing FinFET Structure Compred to conventionl plnr devices (ulk or SOI), FinFET devices hve unique 3-D gte structures tht enle some specil properties for FinFET circuit design which will e detiled in the following sections. Illustrted in Figure 1 is plnr device nd FinFET device (the sustrte is not included in the figure). While the chnnel of the plnr device is horizontl, the FinFET chnnel is thin verticl fin with the gte fully wrpped round the chnnel formed etween the source nd the drin. The current flows prllel to the die plne wheres the conducting chnnel is formed round the fin edges. In dvnced technology nodes the numering scheme is somewht ritrry, while in older technologies the node numer used to denote the smllest feture size, usully the trnsistor gte length, in modern technologies the node numer does not refer to ny one feture in the process, nd foundries use slightly different conventions; we use 1 to denote the 14 nm 16 nm FinFET nodes offered y severl foundries. L Source W Gte () Drin Gte Dielectric Hfin Fin Width (t) Drin Gte Guo et l. L Gte Dielectric Source Fig. 1. Illustrtion of structurl differences (no sustrte): () plnr device; () FinFET device. With this structure, the gte is le to fully deplete the chnnel thus hving much etter electrosttic control over the chnnel. FinFETs cn e clssified y gte structure or type of sustrte. Different gte structures led to two versions of FinFET Shorted-gte (SG) FinFETs nd Independentgte (IG) FinFETs. In SG devices, the left nd right sides re connected together in wrp-round structure s in Figure 1; this cn serve s direct replcement for the plnr devices which lso hve one gte, source nd drin (three terminl-devices). In IG FinFETs, the top prt of the wrpround gte structure is etched out nd this results two seprte left nd right sides tht cn ct s independent gtes nd cn e controlled seprtely. 8,9 Although IG FinFETs offer more design options, the friction costs re lso higher in generl. Depending on the sustrte, the FinFETs cn e either SOI or ulk FinFETs s illustrted in Figure 2. SOI FinFETs re uilt on SOI wfers nd hve lower prsitic cpcitnce nd slightly less lekge. Bulk FinFETs re more fmilir to designers, the friction costs re reltively lower, nd they lso hve etter het trnsfer rte to the sustrte compred to SOI FinFETs, 8 thus ulk FinFETs re usully preferred for most digitl pplictions. The friction of oth types of FinFET devices is comptile with those of the conventionl plnr devices fricted on either ulk or SOI wfers Device Geometry nd Sizing Unlike plnr technologies for which the trnsistor width is continuous vlue fully under the control of the circuit designer, in FinFET technologies device widths re quntized into units of whole fins. The effective gte width G Silicon Sustrte () G () Buried Oxide Silicon Sustrte Fig. 2. Cross section view of structurl differences etween () Bulk FinFET nd () SOI FinFET. () 2 J. Low Power Electron. 13, 1 18, 2017

3 Guo et l. of FinFET device is roughly n(2h fin + t, wheren is the numer of fins, t is the fin width nd H fin is the fin height s illustrted in Figure 1(). Since the gte of FinFET device is designed to chieve good electrosttic control over the chnnel, nd ecuse of the etching uniformity requirements, the fin dimensions (e.g., height H fin ) re not under designer control, nd thus the device width cnnot hve n ritrry vlue s in plnr technologies. Wider trnsistors with higher on-currents re otined y using multiple fins, ut the rnge of choices is limited to integer vlues. This is known s the width quntiztion issue This quntiztion issue doesn t llow flexiility in terms of device sizing which ecomes prolemtic especilly in nlog design nd SRAMs. The designers need to dpt to this new constrint during the design phse. 13 An lterntive solution would e for the foundry to provide the designers with multiple versions of FinFET with different fin heights. 14 For exmple, 15 did n erly ttempt y exploring the design spce of FinFETs with doule fin heights nd showed tht the lck of continuous sizing cn e somewht compensted; this method though hs mny uncertinties from oth friction costs nd mnufcturing difficulties, so it is unlikely to ecome widely ville. In summry, for digitl circuits, width quntiztion might not e ig issue since most of the cell designs cn e dpted to use the limited choice of device widths ville FinFET Device Scling Fin Height As discussed in the lst section, fin height determines the overll width of device. This is very importnt prmeter for circuit designers ut they don t ctully hve control over it. Smller fin heights offer more flexiility in terms of sizing, ut this would led to more fins, which mens more silicon re. In contrst, FinFET devices with tller fins offer less flexiility with sizing ut hve smller silicon footprint nd the incresing fin heights for successive FinFET nodes comines with the lterl scling to ctully ccelerte Moore s Lw style scling; ut this might lso result in lrger short-chnnel effects nd some structurl instilities. 1,8 In ddition, tller devices could lso led to n increse in unwnted cpcitnce. This indictes tht there re some opportunities for devicecircuit codesign tht re unlikely to ecome ville for fless compnies ut could ecome importnt for verticlly-integrted compnies tht hve their own fs. Bck to the Future: Digitl Circuit Design in the FinFET Er An exmple of such involvement cn e to nlyze the design spce of current versus cpcitnce for different fin heights. As the technology node pproches the su-10 nm scle, this type of nlysis is more nd more importnt since the friction difficulties re incresing, nd the design trdeoffs might drsticlly chnge Bulk versus FDSOI versus FinFET Devices In this section, we present some study results cross multiple technology nodes (from 130 nm to 7 nm) which include oth rel technology nodes tht re used in industry, nd lso predictive nodes which re widely used in cdemi ut not tied to ny specific foundry. As for the 7 nm node, we use recently relesed predictive 7 nm PDK 17 which is sed on current relistic ssumptions for the 7 nm technology node ut is not tied to or verified y specific foundry. We elieve tht this nlysis will provide us with good insight on how FinFET devices re right now (with industry PDKs) nd how good these devices re likely to e in the future (with predictive PDKs) s we move forwrd compred to the plnr devices. From digitl circuit designer s perspective, whether the technology is plnr or FinFET, whether it is ulk or SOI, the prmeters of interest re the sme how much current cn one trnsistor drive, lekge, DIBL, GIDL nd so on. Summrized in Tle I re device prmeters we extrcted sed on extensive simultion results cross multiple technology nodes Device Models Device models re criticl for circuit designers to run simultions nd mke design decisions. They need to e ccurte nd efficient in terms of simultion time nd complexity. The fct tht fins re 3D structures tht rise ove the sustrte mens tht they re more strongly ffected y their immedite environment thn plnr devices. This results in numer of chllenges during the modeling process. For exmple, the interction etween the device nd its surroundings needs to e ccurtely modeled. Besides, the unique gte structure leds to incresed gte cpcitnce nd lso to more components when modeling the prsitic cpcitnce nd resistnce compred to the plnr devices. 19,20 These cpcitnce nd resistnce vlues re crucil since the inccurcy cused during extrcting R nd C prsitic will led to Tle I. Summry of device prmeters cross multiple technology nodes (extrcted from I V curves). Physicl length Nominl I n /I p Suthreshold DIBL GIDL Chnnel length Technology L g (nm) V dd (V) (Sturtion) slope (mv/dec) prmeter slope (mv/dec) modultion (/V) 130 nm ulk Bulk nm FDSOI nm ulk FinFET nmulkFinFET Note: Predictive nodes. J. Low Power Electron. 13, 1 18,

4 Bck to the Future: Digitl Circuit Design in the FinFET Er Guo et l. OFF Current/Width (ua/um) 10-2 Plnr, Bulk Plnr FDSOI Lekge reduced drmticlly FinFET, Bulk I ON /I OFF Plnr, Bulk Plnr FDSOI FinFET, Bulk () 130nm 45nm* 28nm 1xnm 7nm* 130nm 45nm* 28nm 1xnm 7nm* () Fig. 3. () Lekge current with technology scling; () I on /I off rtio with technology scling. Note: Predictive technology nodes (45 nm nd 7 nm). mis-chrcteriztion nd under/over-estimted design mrgins. Figure 4 shows n exmple of how FinFET prsitic cpcitnce is ccounted for 2-finger device. It is cler tht more components contriute to oth intrinsic cpcitnce (in the SPICE models) nd extrction cpcitnce (ccounted during extrction). For exmple, the gte cpcitnce includes gte to top of fin diffusion, gte to sustrte etween fins, gte to diffusion inside chnnel, gte to diffusion etween fins, gte to contct, nd so on. Similrly, the Fin-to-Fin cpcitnce is lso newly introduced for FinFET devices. The complexity of modeling hs een incresing s the device dimensions shrink. Coupling nd Miller effects re more pronounced in these devices s well. The FinFET structure rings new modeling chllenges. In plnr device, the source nd drin re self-ligned with the gte nd often intrude slightly under it. In Fin- FET devices there is spcer etween the gte nd the source nd drin, which re usully rised nd hve strin cused y SiGe lyer tht cretes lttice mismtch. This mens there re much more complex prsitic cpcitnce nd resistnce structures nd more model clirtions re required to chieve good ccurcy. As for the designer, the simultion efficiency lso mtters nd it depends on the levels of model complexity, ut thnks to the fst solvers nd ccurte extrction tools recently developed, the simultion time hs remined trctle Lekge One of the driving forces tht leds the industry to move from ulk plnr to FDSOI or FinFET technologies is the difference in lekge. With every new process genertion the douling of gte density is lso ssocited with douling of the mount of lekge current. 21 This is lso cler from the simultion results in Figure 3() where the suthreshold current (OFF current) per unit width is plotted for different technology nodes. It cn e seen from the plot tht, when scling from 130 nm to 45 nm, the lekge current increses significntly, due to the fct tht the chnnel depth underneth the gte ecomes lrger nd significnt volume of the chnnel is too fr wy from the gte nd there is susequent loss of electrosttic control. FDSOI nd FinFET on the other hnd chieve much etter lekge results ecuse the gte hs much etter control over the chnnel in these technologies. Our simultions show tht 28 nm FDSOI nd 7 nm FinFETs hve comprle Contct Contct Fin Gte Diffusion Gte Diffusion Diffusion Fin Diffusion Fin Sustrte () () Fig. 4. Cpcitnce components for FinFET device: () Cross-section view nd () Top view. 4 J. Low Power Electron. 13, 1 18, 2017

5 Guo et l. lekge numers. However, 1 nm ulk FinFET shows reduction of lekge of t lest 50%. This cn e due to the fct tht FDSOI nd FinFET use different mechnisms to reduce lekge. In FDSOI, lekge reduction is chieved y mking the chnnel thinner, y limiting its depth with the help of n insulting lyer, while in FinFET it is chieved y mking the gte wrp round the chnnel. Another wy of explining the lekge reduction in Fin- FET devices is to look into the suthreshold slope. The su-threshold slope lso mesures how fst the device cn switch from OFF to ON, nd the lower ound is 60 mv/dec t room temperture. Tle I shows tht, together with the move to FDSOI nd FinFET, the suthreshold slope vlue hs ctully improved with scling nd this hs resulted in significnt enefit for continuously improving frequency, ctive power, lekge power or comintion of the three over the pst few yers I on /I off Rtio The I on /I off rtio is n importnt figure of merit for hving high performnce (higher I on ) nd low lekge power (lower I off ) for the devices. Since the lekge current (I off ) hs een significntly reduced in FinFET devices, their I on /I off rtio is superior to ulk, s shown in Figure 3(). This hs lso enled continuous performnce improvement DIBL Drin-Induced-Brrier Lowering (DIBL) is short-chnnel effect tht ppers s the distnce etween the source nd drin decreses to the extent tht they ecome electrostticlly coupled. The drin is ffects the potentil rrier to crrier flow t the source junction, resulting in suthreshold current increse. To chrcterize it, we use the DIBL prmeter, which is defined in Eq. (1) nd corresponds to the chnge of lekge current due to V ds. The smller this prmeter, the etter the DIBL ehvior is. It is shown in Tle I tht FinFETs chieve very good DIBL ehviors compred to ulk devices. In prticulr, the 1xnm FinFET device hs the lowest DIBL effect mong ll five technology nodes considered. log I off = DIBL Prmeter V ds (1) Chnnel Length Modultion (CLM) Chnnel length modultion (CLM) is nother shortchnnel effect tht is cused y lrge drin ises. It is chrcterized y the CLM prmeter which is generlly proportionl to the inverse of the chnnel length. Smller mens less CLM effect. Tle I shows tht CLM hs een getting worse s the chnnel length shrinks in plnr devices even y incresing the doping density. When technology switched from plnr to FDSOI nd FinFET, CLM hs een improved due to the etter control over the chnnel. Especilly, in 7 nm technology node, the CLM Bck to the Future: Digitl Circuit Design in the FinFET Er effect is the smllest nd is s good s reltively old long-chnnel technology (130 nm) GIDL The introduction of high-k/metl-gte stcks in plnr devices hs led to sustntil reduction in the gte lekge nd hs exposed other lekge mechnisms such s gte-induced drin lekge (GIDL) s primry gterelted lekge mechnisms. 23 GIDL occurs due to the high reverse is etween the silicon ody nd the drin junction ( PN-junction) ner the gte edge t nerzero or negtive gte is. 24 GIDL usully increses s the gte length (L g ) decreses due to the floting ody effect nd is usully pronounced in short-chnnel devices. In this pper, we pick the GIDL slope to quntify this effect; the lrger this slope the lesser GIDL effect the device hs. Interestingly, the results in Tle I indicte tht s the technology switched to FinFET, GIDL hs ctully improved. The suppression of GIDL cn e explined y the light doping of the chnnel nd etter junction plcement grdient s suggested in Ref. [23]. In conclusion, FinFETs re superior to plnr devices in terms of I on /I off,dibl,clm, GIDL, nd thus pper to e true ck to the future reset of most of the metrics tht were getting worse with every new technology node for ulk plnr technologies! W p /W n Rtio Another interesting spect for FinFET technologies is tht the pull up network (PUN) nd the pull down network (PDN) cn ecome very symmetric. PMOS nd NMOS devices with the sme numer of fins hve very comprle driving strength, nd the conventionl 2:1 or 3:1 sizing strtegy is not e pplicle (or necessry) in the FinFET cse. This cn e seen from the I n /I p rtio in Tle I, which is very close to 1 for the FinFET nodes. Figure 5 further demonstrtes this. It plots the voltge trnsfer curve (VTC) under different supply voltges for FinFET inverter with W p /W n = 1. It shows tht the smllsignl gin (which is the slope of the trnsfer curve when the input is equl to the mid-point voltge) is close to idel (very high gin), nd the curves re very lnced in ll cses which further demonstrtes tht the rtio of 1:1 is optiml for FinFET logic. The reson ehind this fct is due to the unique friction process for FinFET. As opposed to plnr structures which cn only e fricted in single plne due to process vrition nd interfces trps, FinFETs cn e fricted with their chnnel long different directions in single die. This results in enhnced hole moility. The N type FinFETs implemented long plne 100 nd the P type FinFETs fricted long plne 110 led to fster logic gtes since it comts the inherent moility difference etween electrons nd holes. 1,25,26 Moreover, since the gte hs very good control over the chnnel, doping concentrtions cn e much lower thn in plnr devices, thus llowing to reduce the rndom dopnt J. Low Power Electron. 13, 1 18,

6 Bck to the Future: Digitl Circuit Design in the FinFET Er Guo et l. Vout (V) Vout = Vin Vdd=0.8V Vdd=0.6V Vdd=0.4V Vdd=0.2V Velocity Sturtion Index (Alph) Plnr Bulk Plnr FDSOI FinFET,Bulk Vin (V) Fig. 5. VTC curves under different supply voltges for 1xnm FinFET inverter (PMOS nd NMOS re sized eqully). fluctutions (RDF), 7 mitigting the impct of moility on current. The symmetric PUN nd PDN introduce ese in terms of physicl design nd sizing ut it lso rings slight chnges in design decisions nd stndrd cell design Alph-Power Lw The long-chnnel MOSFET model (Shockley model), ssumes tht crrier moility is independent of the pplied fields, since the lterl or verticl electric fields were low. 27 However, for short-chnnel MOSFETs, the velocity of crriers reches mximum sturtion speed due to crriers scttering off the silicon lttice. This lso leds to degrdtion in moility tht depends on the gte to source voltge V gs. The drin current I d is qudrticlly dependent on the drin to source voltge (Vds 2 ) in the long-chnnel regime nd linerly dependent on V ds when fully velocity sturted due to n electric field higher thn criticl electric field E c = V c /L g, 28 where V c is the corresponding criticl voltge nd L g is the gte length. A moderte supply voltge is when the trnsistor opertes etween the long-chnnel regime nd velocity sturtion. The complete model, clled the -power lw model, is presented in Eq. (2): 0 V gs <V t (Cutoff) V I ds = I ds dst V V ds <V dst (Liner) (2) dst I dst V ds >V dst (Sturtion) where I dst = P c /2 V gs V t nd V dst = P v V gs V t /2. The exponent is clled the velocity sturtion index, nd rnges from 1 for fully velocity sturted trnsistors to 2 for trnsistors with long chnnel or low supply voltge. Fig nm 28nm 1xnm 7nm Velocity sturtion index ( ) for different technologies. We performed I ds V gs simultions for the se NMOS trnsistors of four different technologies nd determined their respective velocity sturtion index. The results otined, summrized in Figure 6, suggest tht, s we switch to FinFETs, devices ehve incresingly more ccording to the long-chnnel model, gin, in ck to the future wy FinFET Friction In the previous section we studied the device prmeters of FinFET versus plnr technology nodes nd found out tht FinFET devices stnd out in lmost ll the metrics. Besides, the process technology of FinFET is reltively strightforwrd nd comptile with conventionl plnr device friction process. 29 But there re still chllenges, for exmple, fin shpe control nd recess of shllow trench isoltion (STI) oxide re still criticl in the integrtion of FinFETs. Due to the spce limit nd the focus of this pper, we list only few friction dvnces nd chllenges in the FinFET er in this section Doule/Multi-Ptterning Although technologies keep scling to the order of few nnometers, lithogrphy still uses 193 nm wvelength light, which mkes printility nd mnufcturility more chllenging due to incresed distortion. Beyond 20 nm the use of multi-ptterning is required for device friction. Using multi-ptterning technology, single lyout is decomposed into two or more msks nd mnufctured through two or more exposure steps. These msks re then comined to get the originl intended lyout. By decomposing the lyout into two or more msks s shown in Figure 7, the pitch size is effectively douled therey enhncing the resolution. 30 To chieve this, on the design side, color (msk) ssignments re used. Severl techniques of multi-ptterning include Litho-Etch-Litho-Etch Doule Ptterning (LELE DP), Spcer-is-Metl Self-Aligned Doule Ptterning (SIM 6 J. Low Power Electron. 13, 1 18, 2017

7 Guo et l. Fig. 7. Bck to the Future: Digitl Circuit Design in the FinFET Er Lyout decomposition: A single lyer is decomposed in two or more msks to enhnce the resolution. SADP), Litho-Etch-Litho-Etch-Litho-Etch Triple Ptterning (LELELE TP) nd Spcer-is-Dielectric Doule Ptterning (SID SADP). To use these techniques the designer cn include the colored msks per lyer tht must e multiptterned or use colourless flow where the foundry performs the decomposition Fin Formtion Although multiptterning rings new friction chllenges, some of the known friction steps from the plnr technology cn e repurposed to chieve new required shpes like the 3D fins. Sidewll spcer deposition steps from plnr processes re utilized to perform self-ligned doule ptterning (SADP). Similrly, the steps used to form Shllow trench isoltion (STI) cn e extended to fricte fins y dditionl etching of STI res nd therey exposing Si fins. Fins re fricted in regulr fshion over lrge re. Therefter unwnted fins re excised nd the remining fins ecome prt of ctive res of the devices. Hence FinFET friction ecomes comptile with old plnr CMOS processes using repurposing of existing steps, plus few extr steps Shpe of the Fins Severl studies hve shown tht FinFET performnce is ffected y the cross-sectionl re of the fin, therefore the fin shpe. Intel s 22 nm node microprocessor ws uilt with FinFET sidewlls sloping t out 8 degrees from verticl which mkes more sturdy devices mong other dvntges.26 Figure 8 shows the min types of fins nlyzed in the literture. Experimentl dt shows tht FinFET with rectngulr cross-sectionl re hs etter short chnnel effect metrics, in prticulr su-threshold slope, GIDL nd DIBL if compred with tringulr or trpezoidl cross-sectionl re.32 On the other hnd tringulr fin cn reduce lekge current y 70% if compred with rectngulr fin Middle-End-of-Line (MEOL) Middle-end-of-line (MEOL) is new term introduced in the FinFET er. It refers to the intermedite process steps tht complete the trnsistor formtion (Front-end-of-line: FEOL) efore contcts nd interconnect formtion (Bck-end-of-line: BEOL).34 MEOL is J. Low Power Electron. 13, 1 18, 2017 necessry to provide etter cell level connections with restricted ptterning cpilities nd multiptterning.35 The introduction of MEOL increses the complexity of friction nd modeling s well. For circuit designers, the dded new prsitic effects from MEOL need to e considered during the design process since these prsitics hve een demonstrted to e one of the dominnt sources.36 MEOL prsitics hve een usully ccounted t the logic gte-level prsitic extrction step using the stndrd EDA tools. For physicl design engineers, the dded MEOL mens more complex design rules nd longer deugging process, lso, the lyout tools must utomte conformnce to rules s much s possile Summry Wht Hve We Lerned So Fr? The studies discussed in the previous sections show tht FinFET devices outperform plnr devices (ulk nd SOI) in lmost ll spects. In prticulr, much less lekge current enle wide rnge of pplictions from high-end to energy-constrined pplictions. Better Ion /Ioff rtio hve led to continuous performnce improvement compred to plnr t the sme node. FinFET devices lso provide improved su-threshold nd short-chnnel ehvior. An dded dvntge of the FinFET is tht it cn e esily fricted long different chnnel plnes in single die, nd this mkes sizing strtegy simpler. The dded MEOL mde the trnsition from plnr devices to FinFETs slightly more complex in terms of the friction nd prsitics ut the Fig. 8. Left side: A fin with verticl slope which presents etter short chnnel metrics.32 Middle: A stndrd fin with some degree of inclintion s the one used in the 22 nm Intel s node.26 Right side: A fin with tringulr cross-sectionl re tht cn help to reduce the lekge.33 7

8 Bck to the Future: Digitl Circuit Design in the FinFET Er ck-end of the process is essentilly the sme, nd therefore the prt of the design flow ssocited with the physicl implementtion remins similr Guo et l. 1xnm Bulk FinFET 7nm Bulk FinFET 3. FINFET CIRCUITS Since FinFET devices hve much etter electrosttic properties nd other metrics thn plnr devices, new logic nd wider design spce explortion opportunities ecome ville. In this section, we discuss these new chnges tht FinFETs hve introduced t the circuit level Logic Styles As discussed in Section 2.1.1, FinFETs come in two flvors short-gted (SG) nd independent-gted (IG). For IG FinFETs, the top prt of the gte is etched out, resulting in two independent gtes. Becuse the two independent gtes cn e controlled seprtely, IG-mode FinFETs offer more design styles. 8,9 Although the gtes re electriclly isolted, their electrosttics re highly coupled. The threshold voltge of either of the gtes cn e esily influenced y pplying n pproprite voltge to the other gte. Shown in Figure 9 is one exmple of different flvors of 2-input NAND gte implemented using SG/IG gte or hyrid of oth (modified from Ref. [8]). In SG mode, FinFET gtes re tied together, so they work the sme s the plnr devices; In IG mode, one device (with two gtes) is driven y two independent signls, nd some logic functions cn e relized y one device; in IG-Low Power mode, one gte is disled nd cts s the reverse-ised ck-gte. The designers cn even mix the two types of devices nd lnce the trdeoff if it is llowed y the foundry. But IG gte requires one more step of etching in the friction step Body Effect Adptive Body Bising (ABB) hs een used y circuit designers s n effective design technique to reduce the impct of die-to-die nd within-die vritions y chnging the NMOS nd PMOS threshold voltges independently in order to mximize performnce. 37 FinFETs fricted in I ON (ua) ON current doesn't chnge with ody is VBS (V) Fig. 10. ON current versus Body is for 2-finger 1 nmnd7nm NMOS trnsistor. ulk or SOI processes receive little enefit from controlled ody effect ecuse the chnnel in the FinFET is mostly in the top of the fin, wy from the ody. Thus the ody is techniques is not pplicle to FinFET circuit design nymore. 38 To vlidte the ove rgument, we pply oth reverse nd forwrd ody is to 2-finger trnsistor nd simulte the ON current for oth 1 nm nd 7 nm nodes, with the results re shown in Figure 10. The ON current doesn t chnge with the ody voltge, s expected, nd it indictes tht FinFET devices re lrgely insensitive to the ody effect. On one hnd, this reduces the ville design knos, on nother hnd, this cn mitigte the stck effect. In the following sections, we present two solutions to ddress these two seprte spects Gte Overdrive with Split-Circuit Bising to Sustitute for Body Bising in FinFET In this section, circuit topology is presented which sustitutes ody ising, ut doesn t rely on the ody (or ck plne) voltge to do so. Additionlly, the topology presented here does not require vrying the voltge swing to V dd V dd V dd V dd V High SG IG IG - Low Power IG - Hyrid Fig. 9. Different FinFET logic styles: 2-input NAND gte designs with SG nd IG devices. 8 J. Low Power Electron. 13, 1 18, 2017

9 Guo et l. Bck to the Future: Digitl Circuit Design in the FinFET Er () () Fig. 11. () Sttic CMOS inverter with 2 fins per trnsistor nd () Split-circuit inverter with split inputs, outputs, nd supply rils. 39 modulte performnce nd power s in DVS. The effect is chieved y splitting the inputs, outputs, nd supply rils of gte nd pplying smll difference etween the two sets of supply rils, which will either overdrive some device gtes (in forwrd is) or decrese the lekge current for off trnsistors (in reverse is). 39 Figure 11 shows n inverter implemented with the regulr topology nd the proposed split-circuit ising topology. The ide is to regulte V gs to mimic the threshold shift chieved y ody ising. In order to do this, two supply voltge domins re needed. One domin will e the nominl domin, with voltge swings from 0 to V dd. The second domin will hve the sme differentil, ut oth the ground nd supply ril will e shifted up y some is voltge, V, such tht the voltge swings of gtes receiving this supply domin will swing from 0 + V to V dd + V. The inputs, outputs, nd supply rils of trditionl CMOS topology re split such tht the numer of ech re douled. Any two corresponding inputs will crry the sme logic, ut one is shifted up y some is voltge, V. Under forwrd is, the higher inputs will drive the gtes of the NMOS while the lower inputs will drive the NMOS; this will result in higher V gs forhlfofthe NMOS nd higher solute vlue of V gs forhlfofthe PMOS, nd therefore higher I on for hlf of the devices. Under reverse is, V will e negtive. The power ril voltges will e otined y two off-chip supplies which hve the sme differentil (V dd ), nd one on-chip chrge pump to mintin the voltge seprtion etween the two domins ( V ). Figure 12 shows the performnce nd sttic power response of utterfly module of FFT for the 7 nm nd 20 nm FinFET nodes to the split-circuit ising, which enles wide rnge of performnce (For exmple, t forwrd is of 0.2 V the dely of the utterfly module reduced to 58% of the nominl dely with 7 nm). This confirms tht split-circuit ising gives effective control over device current post-friction in FinFET technology which cnnot enefit significntly from controlled ody effect Stck Height s Potentil Design Kno in FinFET Circuit Design In some logic cells, NAND gte for exmple, severl trnsistors re connected in series nd stcked. In plnr CMOS circuit, stck height is limited y the ody effect; due to the ody effect, the voltge etween source nd ody of the top stcked trnsistor will increse the threshold voltge nd will led to performnce degrdtion; if the stck height keeps incresing, the pull down current will ecome smller nd the circuit will ecome slower or might not () () Fig. 12. Simultion results (using the predictive FinFET nodes 40 ) with the Split-ising circuit for FFT utterfly module () Normlized dely from chnge in inputs to chnge in outputs; () Normlized sttic power in stndy mode. 39 J. Low Power Electron. 13, 1 18,

10 Bck to the Future: Digitl Circuit Design in the FinFET Er Guo et l. () 16 4x 4x 4x 4x 4x Dely(ps) () Stck Height Fig. 13. () 16-input AND gte implemented with different stck height (1, 4 nd 16); () 16-input AND dely simultions with different stck height (interconnect cpcitnce is considered). even function correctly. For FinFET logic due to the insensitivity to the ody effect s discussed ove, the stck effect will e miniml nd this cn led to higher stck logic cells with potentil of incresing the fn-in nd reducing the logic depth, thus further reducing dely nd lekge pths. Our first ttempt of simulting 16-input AND gte confirms the ove ssumption. Shown in Figure 13() is 16-input AND gte implemented with different stck heights nd logic depths. Figure 13() shows the simulted dely in 1 nm FinFET technology corresponding to different stck height. The results suggest tht stck height of 16 nd corresponding logic depth of 2 stges chieves the est performnce. Another enefit of incresing the stck height is the reduction of lekge. If we ssume tht the lekge with stck height of 16 design is 16I, where I is the lekge of the unit-sized trnsistor, then the lekge for stck height of 2 is I, whichis much lrger. In summry, due to the fct tht the stck effect is wek in FinFET logic, designers cn increse the stck height with reltive relxed mrgin to lnce the trdeoffs of re, dely nd lekge Stndrd Cell Lirries There re mny trdeoffs tht need to e considered when developing stndrd cell lirries. For exmple, logic offerings such s the mx numer of logicl inputs on complex gtes, flip-flop nd ltch offerings, clk uffers, drive strength for ech cell nd so on. As discussed in the previous sections, FinFET devices hve severl unique intrinsic device chrcteristics, nd these ring severl chnges to the stndrd cell lirry designers. First, with plnr trnsistors, designers cn ritrrily chnge trnsistor width in order to mnge drive current. With FinFETs, due to the width quntiztion fct s discussed in Section 2.1.2, they cn only dd or sutrct fins to size it nd chnge the current. Second, since ody ising is generlly ineffective, s discussed in lst section, this might led to more logicl inputs on complex gtes in FinFET lirries. Coming to the physicl design, the FinFET devices hve periodic structures, nd the optiml W p /W n rtio is lmost 1:1, thus the FinFETs lyout looks more regulr, nd the PMOS nd NMOS regions re symmetric. The stndrd cell templte height (in the numer of M1 wiring trcks) usully comes in severl flvours. For exmple, high density lirry might e 9 trcks tll, high performnce lirry might e 13 trcks tll, nd power optimized lirry might e 10.5 trcks tll. But in FinFET, the dditionl constrint of fitting fixed numer of fins within cell complictes this Ref. [4]. Especilly in most FinFET technologies, fin nd metl pitches re different nd hve not tended to line up. Power ril connections t the top nd ottom of the cell typiclly force the removl of 1 fin ech, nd typiclly 2 dditionl fin trcks must e removed in the center of the cell to ccommodte gte input connections, ll of these mke compct FinFET cell design very complex. In ddition, 4 lso pointed out tht to meet the multiple ptterning requirement, the coloring process need to e conducted during the design of the stndrd cells, coloring lso needs to meet density solutions (ech color msk must hve resonly consistent density cross the chip) Logicl Effort The logicl effort method is n pproximte, simplified model to nlyze the dely of gte. The normlized dely is expressed s: d = f + p = g h + p (3) where p is the prsitic dely, i.e., the dely of the gte driving no externl lod, nd f is the effort dely, expressed s the product of logicl effort g nd fnout h. The logicl effort g is proportionl to the complexity of gte s more complex gte leds to higher gte dely. The fnout h is the rtio of the output lod cpcitnce to the input cpcitnce of gte. We estimted the g nd p for n inverter, 2-input NAND nd 2-input NOR for different technologies using simultion. For this, we use simple simultion setup consisting of fnout of 1 nd fnout of 4 gte dely chins. The results otined re summrized in Tle II. The vlues of g nd p hve een normlized to the respective inverter vlues for ech technology. The tle shows tht the g nd p vlues vry slightly cross technologies 10 J. Low Power Electron. 13, 1 18, 2017

11 Guo et l. Bck to the Future: Digitl Circuit Design in the FinFET Er Tle II. Normlized logicl effort g nd prsitic dely p vlues. 7 nm FinFET 1 nm FinFET 28 nm FDSOI 130 nm Bulk Textook INV NAND NOR INV NAND NOR INV NAND NOR INV NAND NOR INV NAND NOR g p depending on trnsistor sizing for different technologies. Mesured normlized delys for different gtes re presented in Figure 14 which shows tht gtes mintin similr trend for increse in complexity cross different technologies. NOR gtes with stcked PMOS re slower thn NANDs (stcked NMOS) even in FinFETs where the rtio of ON current in NMOS to PMOS is close to 1 s shownintlei Therml Effect Inversion (TEI) Therml ehvior is one of the importnt device chrcteristics tht ffect the design decisions like mrgins, floorpln nd cooling costs. It hs een shown in the literture tht temperture chrcteristics of FinFET-sed circuits re fundmentlly different from those of conventionl ulk CMOS circuits. 41 In ulk technology, if the trnsistor opertes in the super-threshold region, the dely increses with the temperture, nd in the ner/suthreshold region, the dely decreses with the incresing temperture. While in FinFET, it hs een reported tht the circuits run fster t higher tempertures in ll supply voltge regimes (including the super-threshold one), nd this is clled the Temperture Effect Inversion (TEI) phenomenon. 41 In oth plnr devices nd FinFET devices, the threshold voltge decreses t the higher temperture, nd the moility of chrge crriers in the chnnel decreses due to the ionized impurity nd phonon scttering. 42 TEI Dely (Normlized to 7nm F04 INV) FO4 INV FO4 NAND FO4 NOR 130nm 28nm 1xnm 7nm Fig. 14. Simulted FO4 delys for Inverter, 2-input NAND nd 2-input NOR gtes in different technology nodes (ll vlues re normlized to the 7nm FO4 INV dely). hppens due to the fct tht FinFET chnnels re usully undoped or lightly doped, so they exhiit only smll chnge in moility with temperture. It hs een shown in Ref. [43] tht TEI s inflection voltge pproches nominl supply nd the impct of this effect cn no longer e sfely discounted when scling into future FinFET nd FDSOI devices with smller feture sizes. To vlidte this, we simulte the dely vs. temperture for 9-stge ring oscilltor in multiple technology nodes. The simultion results re shown in Figure 15; the results show tht for ll technologies, the incresed temperture slow down the devices if they work under ner nd su-threshold region. Interestingly, for the 28 nm FDSOI node, TEI ppers cross ll voltges, nd for 1xnm ulk FinFET node, the TEI effect hs lredy pproched 0.7 V, which is only 0.1 V elow the nominl voltge (0.8 V). Similrly, for 7 nm ulk Fin- FET, the inversion strts from round 0.6 V (0.1 V elow the nominl voltge of 0.7 V). We cn conclude tht the TEI effect is indeec ecoming incresingly importnt in current nd future technologies s it will cover ll of the operting voltge rnges. The TEI effect introduces new trdeoffs nd lso chllenges in circuit design. On one hnd, higher temperture increses the lekge nd cooling udget, ut, on the nother hnd, it helps with the performnce. The enefits of TEI cn e mximized with the ssist of novel power mngement techniques tht cn dynmiclly tune the voltge or frequency sed on the rel-time temperture 43 or novel lgorithms tht cn determine the mximum performnce under power constrints. 44 Since therml issues lso emerge s importnt reliility concerns throughout the system lifetime, the TEI effect cn compenste some of the performnce degrdtion introduced y reliility threts such s BTI nd EM. 42,45 The optiml operting temperture cn e exploited to reduce design cost nd runtime operting power for overll cooling with the proper utiliztion of the TEI effect SRAM Design SRAMs re one of the most re nd power hungry components on chip. The never-ending demnd for pcking more functionlity per re nd the requirement of higher performnce from processing units leds to continuous scling of devices. 46 This scling trickles down to smller itcells nd enles n increse in memory rry density in terms of numer of its stored per re. Hence from the density point of view, minimum sized trnsistors re desired in itcells. This trnsltes to 1:1:1 J. Low Power Electron. 13, 1 18,

12 Bck to the Future: Digitl Circuit Design in the FinFET Er Guo et l. 3.7x x x nm Bulk, Vdd =1.2V (Nominl) x nm Bulk, Vdd = 0.7V (Nerthreshold) 1.0x x nm Bulk, Vdd = 0.4V (Suthreshold) 3.4x x x x x x x x x x x x x x nm FDSOI, Vdd = 1V (Nominl) 4.0x nm FDSOI, Vdd = 0.5V (Ner-threshold) 1.8x x nm FDSOI, Vdd = 0.3V (Su-threshold) 7.6x x x x x x x x x x x x x x xnm FinFET, Vdd = 0.8V (Nominl) 2.160x x xnm FinFET, Vdd = 0.7V (Nominl) 2.600x x x x10-7 1xnm FinFET, Vdd = 0.4V (Ner-threshold) x x10-7 1xnm FinFET, Vdd = 0.2V (Su-threshold) 1.730x x x x x x x x x x x x x x x x x x x x x x nm FinFET, Vdd = 0.7V (Nominl) 7nm FinFET, Vdd = 0.5V 8.0x10-9 7nm FinFET, Vdd = 0.1V (Suthrehsold) 7nm FinFET, Vdd = 0.3V (Ner-threshold) 3.5x x x x x x x x x x x x x x x x x x x x x Fig. 15. Simulted temperture chrcteristics (dely vs. temperture) in multiple technology nodes for 9-stge ring oscilltor. (PU:PG:PD) fin itcell for FinFETs (where PU is the size of the Pull-up PMOS, PD is the size of the Pull-down NMOS, nd PG is the size of the pss-gte NMOS in 6T SRAM cell). The 1:1:1 itcell provides highest rry density ut it suffers from flws in terms of lower red stility nd writility. 46,47 The constnt need for voltge scling to lower power further excertes SRAM redility nd writility issues. This clls for lternte itcells like the Low Voltge (LV) 1:1:2 cell nd High Performnce (HP) 1:2:2 cell 46 long with red nd write ssist techniques to improve SRAM metrics. Severl ssist techniques 48,49 hve een proposed nd studied to improve SRAM performnce nd lower opertionl V min. These techniques focus on improving PD:PG strength rtio for red ssists nd PG:PU strength rtio for write ssists. These techniques ecome incresingly necessry in the er of FinFET SRAM design ecuse trnsistor width quntiztion in terms of numer of fins decreses device level sizing options to improve SRAM itcell functionlity Vriility nd Reliility A reduced feture size cuses sttisticl fluctutions in nnoscle device prmeters which re known s process vritions. They led to mismtched device ehviors nd 12 J. Low Power Electron. 13, 1 18, 2017

13 Guo et l. degrde the yield of the entire die. In plnr devices, numer of dopnts must e inserted in the chnnel which led to Rndom Doping Fluctutions (RDF) cusing significnt vritions in threshold voltge. In FinFETs, since the chnnel is undoped or lightly doped, this reduces the sttisticl impct of RDF on V t. The vriility ssocited with line-edge roughness (LER), the rndom devition of gte line edges from the intended idel shpe, which results in non-uniform chnnel lengths, is lso lower in FinFETs. But other process vritions do pper in Fin- FETs. Since they hve smll dimensions nd lithogrphic limittions, these devices suffer physicl fluctutions on gte length, fin thickness or oxide thickness. 1,50,51 Overll, FinFETs emerge superior to plnr devices y overcoming RDF nd LER, which re two mjor sources of process vrition. Besides process vritions, which represent the timezero process vriility, time-dependent vritions (ging) such s Bis Temperture Instility (BTI), Hot Crrier Injection (HCI) nd Electromigrtion (EM) lso pper to e criticl for reliility considertions. These ging issues conspire to worsen metrics like performnce, power nd lifetime. As the technology scling is reching the nnoscle FinFET regime, the trnsistors ecome more susceptile to voltge stress due to the incresed effective field ssocited with the scling of the thin oxide. Similrly, the shrinking geometries of metl lyers render higher current densities, nd the tremendous numer of trnsistors within compct re results in higher power densities. Together, these led to incresed onchip tempertures which potentilly ccelerte the werout effects. 52,53 Besides, the therml resistnce (R th ) of the multi-gte topology nd the reduced gte pitch in Fin- FET devices excerte self-heting which will ccelerte ging. 54 Figure 16 shows our simultion results with the industril ging models; the results show very significnt performnce degrdtion under ccelerted stress condition, nd if we scle this to the norml operting condition (nominl V dd nd norml on-chip temperture), the degrdtion is still much lrger thn tht in the plnr devices. For interconnect reliility, EM no longer cn e signed off using ggressive mrgins, comprehensive thermlwre EM signoff methodology needs to e dopted for FinFET designs. New types of EM rules tht re dependent on the direction of current flow, metl topology, vi types, co-verticl metl overlps etc. re required to ddress the potentil reliility issues Interconnect As the devices ecome smller nd smller, the interconnect ecomes more nd more dominnt in determining circuit performnce. This is ecuse of the yield nd EM requirements, the interconnect cn t scle t the sme rte s the trnsistors. As interconnect is ecoming more compct t ech node elow 20 nm, 56,57 the interconnect RC Bck to the Future: Digitl Circuit Design in the FinFET Er Frequency (MHz) Vdd: 1V (Nominl - 0.8V ) Temperture: 100 C Test Structure: 17-Stge RO with 1XINV 34.3% Degrdtion Time (yer) Fig. 16. Aging simultion with 1 nm ulk FinFET with foundryprovided ging models (BTI + HCI). prsitic dely will ffect the performnce in more significnt wy nd ecome one of the ottlenecks on the scling rodmp. To ddress this, interconnect mterils such s Aluminum, colt (Co) or ruthenium (Ru) could e etter lterntives due to the etter sheet resistnce, ut there re lso cost nd reliility considertions in the interconnect scheme design. 58 The pitch size of the metl lines lso doesn t scle down tht much s the technology moves into the su-20 nm regime due to the RC prsitic nd coupling considertion s well. For designers, since they don t hve control over the mterils nd design rules, the only kno they hve is the dimension of the wire. This requires to consider interconnect cpcitnce in the erly design phse even efore the physicl design. The FinFET PDKs usully provide reltively ccurte wire models to ccount this Power nd Energy FinFETs provide improvements in power nd energy consumption since they overcome the lekge prolems of plnr devices nd deliver etter performnce. To further investigte this spect, we simulte NAND-sed ring oscilltor 59 cross multiple technologies. The duty cycle of the ring oscilltor cn e tuned nd in our cse, it is set s 10%. Shown in Figure 17() is the simulted dely versus V dd, in which the vlues of ech node re normlized to the dely t their own nominl voltges. It shows tht FinFETs provide significnt performnce dvntge t ny operting voltges, nd the reduced performnce due to lowering the voltge is much lower in FinFETs compred to other technology nodes s well. Figure 17() presents the energy versus V dd plot, similr normliztion is pplied. As it shows, lthough the minimum energy optiml points re similr for ll the technologies (round V rnge), the energy of J. Low Power Electron. 13, 1 18,