Introduction. 1.1 A Brief History

Transcription

1 Introduction. Brief History In 958, Jck Kily uilt the first integrted circuit flip-flop with two trnsistors t Texs Instruments. In 28, Intel s Itnium microprocessor contined more thn 2 illion trnsistors nd 6 G Flsh memory contined more thn 4 illion trnsistors. This corresponds to compound nnul growth rte of 53% over 5 yers. No other technology in history hs sustined such high growth rte lsting for so long. This incredile growth hs come from stedy minituriztion of trnsistors nd improvements in mnufcturing processes. Most other fields of engineering involve trdeoffs etween performnce, power, nd price. However, s trnsistors ecome smller, they lso ecome fster, dissipte less power, nd re cheper to mnufcture. This synergy hs not only revolutionized electronics, ut lso society t lrge. The processing performnce once dedicted to secret government supercomputers is now ville in disposle cellulr telephones. The memory once needed for n entire compny s ccounting system is now crried y teenger in her ipod. Improvements in integrted circuits hve enled spce explortion, mde utomoiles sfer nd more fuelefficient, revolutionized the nture of wrfre, rought much of mnkind s knowledge to our We rowsers, nd mde the world fltter plce. Figure. shows nnul sles in the worldwide semiconductor mrket. Integrted circuits ecme $ illion/yer usiness in 994. In 27, the industry mnufctured pproximtely 6 quintillion (6 8 ) trnsistors, or nerly illion for every humn eing on the plnet. Thousnds of engineers hve mde their fortunes in the field. New fortunes lie hed for those with innovtive ides nd the tlent to ring those ides to relity. uring the first hlf of the twentieth century, electronic circuits used lrge, expensive, power-hungry, nd unrelile vcuum tues. In 947, John Brdeen nd Wlter Brttin uilt the first functioning point contct trnsistor t Bell Lortories, shown in Figure.2 [Riordn97]. It ws nerly clssified s militry secret, ut Bell Ls pulicly introduced the device the following yer. We hve clled it the Trnsistor, T-R--N-S-I-S-T-O-R, ecuse it is resistor or semiconductor device which cn mplify electricl signls s they re trnsferred through it from input to output terminls. It is, if you will, the electricl equivlent of vcuum tue mplifier. But there the similrity ceses. It hs no vcuum, no filment, no glss tue. It is composed entirely of cold, solid sustnces.

2 2 Chpter Introduction Glol Semiconductor Billings (Billions of US$) er FIGURE. ze of worldwide semiconductor mrket (Courtesy of Semiconductor Industry ssocition.) Ten yers lter, Jck Kily t Texs Instruments relized the potentil for minituriztion if multiple trnsistors could e uilt on one piece of silicon. Figure.2 shows his first prototype of n integrted circuit, constructed from germnium slice nd gold wires. The invention of the trnsistor erned the Noel Prize in Physics in 956 for Brdeen, Brttin, nd their supervisor Willim Shockley. Kily received the Noel Prize in Physics in 2 for the invention of the integrted circuit. Trnsistors cn e viewed s electriclly controlled switches with control terminl nd two other terminls tht re connected or disconnected depending on the voltge or current pplied to the control. Soon fter inventing the point contct trnsistor, Bell Ls developed the ipolr junction trnsistor. Bipolr trnsistors were more relile, less noisy, nd more power-efficient. Erly integrted circuits primrily used ipolr trnsistors. Bipolr trnsistors require smll current into the control (se) terminl to switch much lrger currents etween the other two (emitter nd collector) terminls. The quiescent power dissipted y these se currents, drwn even when the circuit is not switching, FIGURE.2 First trnsistor (Property of T&T rchives. Reprinted with permission of T&T.) nd first integrted circuit (Courtesy of Texs Instruments.)

3 . Brief History 3 limits the mximum numer of trnsistors tht cn e integrted onto single die. By the 96s, Metl Oxide Semiconductor Field Effect Trnsistors (MOSFETs) egn to enter production. MOSFETs offer the compelling dvntge tht they drw lmost zero control current while idle. They come in two flvors: nmos nd pmos, using n-type nd p-type silicon, respectively. The originl ide of field effect trnsistors dted ck to the Germn scientist Julius Lilienfield in 925 [US ptent,745,75] nd structure closely resemling the MOSFET ws proposed in 935 y Oskr Heil [British ptent 439,457], ut mterils prolems foiled erly ttempts to mke functioning devices. In 963, Frnk Wnlss t Firchild descried the first logic gtes using MOSFETs [Wnlss63]. Firchild s gtes used oth nmos nd pmos trnsistors, erning the nme Complementry Metl Oxide Semiconductor, or CMOS. The circuits used discrete trnsistors ut consumed only nnowtts of power, six orders of mgnitude less thn their ipolr counterprts. With the development of the silicon plnr process, MOS integrted circuits ecme ttrctive for their low cost ecuse ech trnsistor occupied less re nd the friction process ws simpler [Vdsz69]. Erly commercil processes used only pmos trnsistors nd suffered from poor performnce, yield, nd reliility. Processes using nmos trnsistors ecme common in the 97s [Med8]. Intel pioneered nmos technology with its 256-it sttic rndom ccess memory nd 44 4-it microprocessor, s shown in Figure.3. While the nmos process ws less expensive thn CMOS, nmos logic gtes still consumed power while idle. Power consumption ecme mjor issue in the 98s s hundreds of thousnds of trnsistors were integrted onto single die. CMOS processes were widely dopted nd hve essentilly replced nmos nd ipolr processes for nerly ll digitl logic pplictions. In 965, Gordon Moore oserved tht plotting the numer of trnsistors tht cn e most economiclly mnufctured on chip gives stright line on semilogrithmic scle [Moore65]. t the time, he found trnsistor count douling every 8 months. This oservtion hs een clled Moore s Lw nd hs ecome self-fulfilling prophecy. Figure.4 shows tht the numer of trnsistors in Intel microprocessors hs douled every 26 months since the invention of the 44. Moore s Lw is driven primrily y scling down the size of trnsistors nd, to minor extent, y uilding lrger chips. The level of integrtion of chips hs een clssified s smll-scle, medium-scle, lrge-scle, nd very lrgescle. Smll-scle integrtion (SSI) circuits, such s the 744 inverter, hve fewer thn FIGURE.3 Intel SRM ( IEEE 969 [Vdsz69]) nd 44 microprocessor (Reprinted with permission of Intel Corportion.)

4 4 Chpter Introduction,,,,, Pentium 4 Core 2 ud Core 2 uo Pentium M Trnsistors,,,,,,, Intel386 Intel486 Pentium II Pentium Pro Pentium Pentium III FIGURE.4 Trnsistors in Intel microprocessors [Intel] er gtes, with roughly hlf dozen trnsistors per gte. Medium-scle integrtion (MSI) circuits, such s the 746 counter, hve up to gtes. Lrge-scle integrtion (LSI) circuits, such s simple 8-it microprocessors, hve up to, gtes. It soon ecme pprent tht new nmes would hve to e creted every five yers if this nming trend continued nd thus the term very lrge-scle integrtion (VLSI) is used to descrie most integrted circuits from the 98s onwrd. corollry of Moore s lw is ennrd s Scling Lw [ennrd74]: s trnsistors shrink, they ecome fster, consume less power, nd re cheper to mnufcture. Figure.5 shows tht Intel microprocessor clock frequencies hve douled roughly every 34 months.this frequency scling hit the power wll round 24, nd clock frequencies hve leveled off round 3 GHz. Computer performnce, mesured in time to run n ppliction, hs dvnced even more thn rw clock speed. Presently, the performnce is driven y the numer of cores on chip rther thn y the clock. Even though n individul CMOS trnsistor uses very little energy ech time it switches, the enormous numer of trnsistors switching t very high rtes of speed hve mde power consumption mjor design considertion gin. Moreover, s trnsistors hve ecome so smll, they cese to turn completely OFF. Smll mounts of current leking through ech trnsistor now led to significnt power consumption when multiplied y millions or illions of trnsistors on chip. The feture size of CMOS mnufcturing process refers to the minimum dimension of trnsistor tht cn e relily uilt. The 44 hd feture size of m in 97. The Core 2 uo hd feture size of 45 nm in 28. Mnufcturers introduce new process genertion (lso clled technology node) every 2 3 yers with 3% smller feture size to pck twice s mny trnsistors in the sme re. Figure.6 shows the progression of process genertions. Feture sizes down to.25 m re generlly specified in microns ( 6 m), while smller feture sizes re expressed in nnometers ( 9 m). Effects tht were reltively minor in micron processes, such s trnsistor lekge, vritions in chrcteristics of djcent trnsistors, nd wire resistnce, re of gret significnce in nnometer processes. Moore s Lw hs ecome self-fulfilling prophecy ecuse ech compny must keep up with its competitors. Oviously, this scling cnnot go on forever ecuse trnsistors cnnot e smller thn toms. ennrd scling hs lredy egun to slow. By the 45 nm

5 . Brief History 5, Clock Speed (MHz), Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 Pentium M Core 2 uo er 2 FIGURE.5 Clock frequencies of Intel microprocessors µm 6 µm 3 µm Feture ze (µm)..5 µm µm.8 µm.6 µm.35 µm.25 µm 8 nm 3 nm 9 nm 65 nm 45 nm 32 nm 22 nm er FIGURE.6 Process genertions. Future predictions from [SI27].

6 6 Chpter Introduction genertion, designers re hving to mke trde-offs etween improving power nd improving dely. lthough the cost of printing ech trnsistor goes down, the one-time design costs re incresing exponentilly, relegting stte-of-the-rt processes to chips tht will sell in huge quntities or tht hve cutting-edge performnce requirements. However, mny predictions of fundmentl limits to scling hve lredy proven wrong. Cretive engineers nd mteril scientists hve illions of dollrs to gin y getting hed of their competitors. In the erly 99s, experts greed tht scling would continue for t lest decde ut tht eyond tht point the future ws murky. In 29, we still elieve tht Moore s Lw will continue for t lest nother decde. The future is yours to invent..2 Preview s the numer of trnsistors on chip hs grown exponentilly, designers hve come to rely on incresing levels of utomtion to seek corresponding productivity gins. Mny designers spend much of their effort specifying functions with hrdwre description lnguges nd seldom look t ctul trnsistors. Nevertheless, chip design is not softwre engineering. ddressing the hrder prolems requires fundmentl understnding of circuit nd physicl design. Therefore, this ook focuses on uilding n understnding of integrted circuits from the ottom up. In this chpter, we will tke simplified view of CMOS trnsistors s switches. With this model we will develop CMOS logic gtes nd ltches. CMOS trnsistors re mssproduced on silicon wfers using lithogrphic steps much like printing press process. We will explore how to ly out trnsistors y specifying rectngles indicting where dopnts should e diffused, polysilicon should e grown, metl wires should e deposited, nd contcts should e etched to connect ll the lyers. By the middle of this chpter, you will understnd ll the principles required to design nd ly out your own simple CMOS chip. The chpter concludes with n extended exmple demonstrting the design of simple 8- it MIPS microprocessor chip. The processor rises mny of the design issues tht will e developed in more depth throughout the ook. The est wy to lern VLSI design is y doing it. set of lortory exercises re ville t to guide you through the design of your own microprocessor chip..3 MOS Trnsistors licon (), semiconductor, forms the sic strting mteril for most integrted circuits [Tsividis99]. Pure silicon consists of three-dimensionl lttice of toms. licon is Group IV element, so it forms covlent onds with four djcent toms, s shown in Figure.7. The lttice is shown in the plne for ese of drwing, ut it ctully forms cuic crystl. s ll of its vlence electrons re involved in chemicl onds, pure silicon is poor conductor. The conductivity cn e rised y introducing smll mounts of impurities, clled dopnts, into the silicon lttice. dopnt from Group V of the periodic tle, such s rsenic, hs five vlence electrons. It replces silicon tom in the lttice nd still onds to four neighors, so the fifth vlence electron is loosely ound to the rsenic tom, s shown in Figure.7. Therml virtion of the lttice t room temperture is enough to set the electron free to move, leving positively chrged s + ion nd free electron. The free electron cn crry current so the conductivity is higher. We cll this n n-type

7 .3 MOS Trnsistors s B - FIGURE.7 licon lttice nd dopnt toms (c) semiconductor ecuse the free crriers re negtively chrged electrons. milrly, Group III dopnt, such s oron, hs three vlence electrons, s shown in Figure.7(c). The dopnt tom cn orrow n electron from neighoring silicon tom, which in turn ecomes short y one electron. Tht tom in turn cn orrow n electron, nd so forth, so the missing electron, or hole, cn propgte out the lttice. The hole cts s positive crrier so we cll this p-type semiconductor. junction etween p-type nd n-type silicon is clled diode, s shown in Figure.8. When the voltge on the p-type semiconductor, clled the node, is rised ove the n- type cthode, the diode is forwrd ised nd current flows. When the node voltge is less thn or equl to the cthode voltge, the diode is reverse ised nd very little current flows. Metl-Oxide-Semiconductor (MOS) structure is creted y superimposing severl lyers of conducting nd insulting mterils to form sndwich-like structure. These structures re mnufctured using series of chemicl processing steps involving oxidtion of the silicon, selective introduction of dopnts, nd deposition nd etching of metl wires nd contcts. Trnsistors re uilt on nerly flwless single crystls of silicon, which re ville s thin flt circulr wfers of 5 3 cm in dimeter. CMOS technology provides two types of trnsistors (lso clled devices): n n-type trnsistor (nmos) nd p-type trnsistor (pmos). Trnsistor opertion is controlled y electric fields so the devices re lso clled Metl Oxide Semiconductor Field Effect Trnsistors (MOSFETs) or simply FETs. Cross-sections nd symols of these trnsistors re shown in Figure.9. The n+ nd p+ regions indicte hevily doped n- or p-type silicon. p-type node n-type Cthode FIGURE.8 p-n junction diode structure nd symol Source Gte rin Polysilicon Source Gte rin O 2 n+ n+ p+ p+ p ulk n ulk FIGURE.9 nmos trnsistor nd pmos trnsistor

8 8 Chpter Introduction nmos pmos g g d s d s FIGURE. Trnsistor symols nd switch-level models Ech trnsistor consists of stck of the conducting gte, n insulting lyer of silicon dioxide (O 2, etter known s glss), nd the silicon wfer, lso clled the sustrte, ody, or ulk. Gtes of erly trnsistors were uilt from metl, so the stck ws clled metloxide-semiconductor, or MOS. nce the 97s, the gte hs een formed from polycrystlline silicon (polysilicon), ut the nme stuck. (Interestingly, metl gtes reemerged in 27 to solve mterils prolems in dvnced mnufcturing processes.) n nmos trnsistor is uilt with p-type ody nd hs regions of n-type semiconductor djcent to the gte clled the source nd drin. They re physiclly equivlent nd for now we will regrd them s interchngele. The ody is typiclly grounded. pmos trnsistor is just the opposite, consisting of p-type source nd drin regions with n n-type ody. In CMOS technology with oth flvors of trnsistors, the sustrte is either n-type or p-type. The other flvor of trnsistor must e uilt in specil well in which dopnt toms hve een dded to form the ody of the opposite type. The gte is control input: It ffects the flow of electricl current etween the source nd drin. Consider n nmos trnsistor. The ody is generlly grounded so the p n junctions of the source nd drin to ody re reverse-ised. If the gte is lso grounded, no current flows through the reverse-ised junctions. Hence, we sy the trnsistor is OFF. If the gte voltge is rised, it cretes n electric field tht strts to ttrct free electrons to the underside of the O 2 interfce. If the voltge is rised enough, the electrons outnumer the holes nd thin region under the gte clled the chnnel is inverted to ct s n n-type semiconductor. Hence, conducting pth of electron crriers is formed from source to drin nd current cn flow. We sy the trnsistor is ON. For pmos trnsistor, the sitution is gin reversed. The ody is held t positive voltge. When the gte is lso t positive voltge, the source nd drin junctions re reverse-ised nd no current flows, so the trnsistor is OFF. When the gte voltge is lowered, positive chrges re ttrcted to the underside of the O 2 interfce. sufficiently low gte voltge inverts the chnnel nd conducting pth of positive crriers is formed from source to drin, so the trnsistor is ON. Notice tht the symol for the pmos trnsistor hs ule on the gte, indicting tht the trnsistor ehvior is the opposite of the nmos. The positive voltge is usully clled V or POWER nd represents logic vlue in digitl circuits. In populr logic fmilies of the 97s nd 98s, V ws set to 5 volts. Smller, more recent trnsistors re unle to withstnd such high voltges nd hve used supplies of 3.3 V, 2.5 V,.8 V,.5 V,.2 V,. V, nd so forth. The low voltge is clled GROUN (GN) or V SS nd represents logic. It is normlly volts. In summry, the gte of n MOS trnsistor controls the flow of current etween the source nd drin. mplifying this to the extreme llows the MOS trnsistors to e viewed s simple ON/OFF switches. When the gte of n nmos trnsistor is, the trnsistor is ON nd there g = g = is conducting pth from source to drin. When the gte is low, the nmos trnsistor is OFF nd lmost d d zero current flows from source to drin. pmos OFF ON trnsistor is just the opposite, eing ON when the s s gte is low nd OFF when the gte is high. This switch model is illustrted in Figure., where g, s, d d nd d indicte gte, source, nd drin. This model OFF ON will e our most common one when discussing circuit ehvior. s s

9 .4 CMOS Logic 9.4 CMOS Logic.4. The Inverter Figure. shows the schemtic nd symol for CMOS inverter or NOT gte using one nmos trnsistor nd one pmos trnsistor. The r t the top indictes V nd the tringle t the ottom indictes GN. When the input is, the nmos trnsistor is OFF nd the pmos trnsistor is ON. Thus, the output is pulled up to ecuse it is connected to V ut not to GN. Conversely, when is, the nmos is ON, the pmos is OFF, nd is pulled down to. This is summrized in Tle.. TBLE. Inverter truth tle.4.2 The NN Gte Figure.2 shows 2-input CMOS NN gte. It consists of two series nmos trnsistors etween nd GN nd two prllel pmos trnsistors etween nd V. If either input or B is, t lest one of the nmos trnsistors will e OFF, reking the pth from to GN. But t lest one of the pmos trnsistors will e ON, creting pth from to V. Hence, the output will e. If oth inputs re, oth of the nmos trnsistors will e ON nd oth of the pmos trnsistors will e OFF. Hence, the output will e. The truth tle is given in Tle.2 nd the symol is shown in Figure.2. Note tht y emorgn s Lw, the inversion ule my e plced on either side of the gte. In the figures in this ook, two lines intersecting t T-junction re connected. Two lines crossing re connected if nd only if dot is shown. TBLE.2 NN gte truth tle B Pull-own Network Pull-Up Network OFF ON OFF ON OFF ON ON OFF FIGURE. Inverter schemtic nd symol = B V GN FIGURE.2 2-input NN gte schemtic nd symol = B k-input NN gtes re constructed using k series nmos trnsistors nd k prllel pmos trnsistors. For exmple, 3-input NN gte is shown in Figure.3. When ny of the inputs re, the output is pulled high through the prllel pmos trnsistors. When ll of the inputs re, the output is pulled low through the series nmos trnsistors. B C.4.3 CMOS Logic Gtes The inverter nd NN gtes re exmples of sttic CMOS logic gtes, lso clled complementry CMOS gtes. In generl, sttic CMOS gte hs n nmos pull-down network to connect the output to (GN) nd pmos pull-up network to connect the output to (V ), s shown in Figure.4. The networks re rrnged such tht one is ON nd the other OFF for ny input pttern. FIGURE.3 3-input NN gte schemtic = B C

10 Chpter Introduction Inputs pmos pull-up network nmos pull-down network FIGURE.4 Generl logic gte using pull-up nd pull-down networks The pull-up nd pull-down networks in the inverter ech consist of single trnsistor. The NN gte uses series pull-down network nd prllel pullup network. More elorte networks re used for more complex gtes. Two or more trnsistors in series re ON only if ll of the series trnsistors re ON. Two or more trnsistors in prllel re ON if ny of the prllel trnsistors re ON. This is illustrted in Figure.5 for nmos nd pmos trnsistor pirs. Output By using comintions of these constructions, CMOS comintionl gtes cn e constructed. lthough such sttic CMOS gtes re most widely used, Chpter 9 explores lternte wys of uilding gtes with trnsistors. In generl, when we join pull-up network to pull-down network to form logic gte s shown in Figure.4, they oth will ttempt to exert logic level t the output. The possile levels t the output re shown in Tle.3. From this tle it cn e seen tht the output of CMOS logic gte cn e in four sttes. The nd levels hve een encountered with the inverter nd NN gtes, where either the pull-up or pull-down is OFF nd the other structure is ON. When oth pull-up nd pull-down re OFF, the highimpednce or floting Z output stte results. This is of importnce in multiplexers, memory elements, nd tristte us drivers. The crowrred (or contention) X level exists when oth pull-up nd pull-down re simultneously turned ON. Contention etween the two networks results in n indeterminte output level nd dissiptes sttic power. It is usully n unwnted condition. g g2 OFF OFF OFF ON g g2 ON OFF OFF OFF g g2 (c) OFF ON ON ON g g2 (d) ON ON ON OFF FIGURE.5 Connection nd ehvior of series nd prllel trnsistors

11 .4 CMOS Logic TBLE.3 Output sttes of CMOS logic gtes pull-up OFF pull-up ON pull-down OFF Z pull-down ON crowrred (X).4.4 The NOR Gte 2-input NOR gte is shown in Figure.6. The nmos trnsistors re in prllel to pull the output low when either input is high. The pmos trnsistors re in series to pull the output high when oth inputs re low, s indicted in Tle.4. The output is never crowrred or left floting. B TBLE.4 NOR gte truth tle B FIGURE.6 2-input NOR gte schemtic nd symol = + B Exmple. Sketch 3-input CMOS NOR gte. SOLUTION: Figure.7 shows such gte. If ny input is high, the output is pulled low through the prllel nmos trnsistors. If ll inputs re low, the output is pulled high through the series pmos trnsistors..4.5 Compound Gtes compound gte performing more complex logic function in single stge of logic is formed y using comintion of series nd prllel switch structures. For exmple, the derivtion of the circuit for the function = ( B) + (C ) is shown in Figure.8. This function is sometimes clled N-OR-INVERT-22, or OI22 ecuse it performs the NOR of pir of 2-input Ns. For the nmos pull-down network, tke the uninverted expression (( B) + (C )) indicting when the output should e pulled to. The N expressions ( B) nd (C ) my e implemented y series connections of switches, s shown in Figure.8. Now ORing the result requires the prllel connection of these two structures, which is shown in Figure.8. For the pmos pull-up network, we must compute the complementry expression using switches tht turn on with inverted polrity. By emorgn s Lw, this is equivlent to interchnging N nd OR opertions. Hence, trnsistors tht pper in series in the pull-down network must pper in prllel in the pull-up network. Trnsistors tht pper in prllel in the pulldown network must pper in series in the pull-up network. This principle is clled conduction complements nd hs lredy een used in the design of the NN nd NOR gtes. In the pull-up network, the prllel comintion of nd B is plced in series with the prllel comintion of C nd. This progression is evident in Figure.8(c) nd Figure.8(d). Putting the networks together yields the full schemtic (Figure.8(e)). The symol is shown in Figure.8(f ). B C FIGURE.7 3-input NOR gte schemtic = + B + C

12 2 Chpter Introduction C C B B B C (c) C (d) B C B B C B C (e) FIGURE.8 CMOS compound gte for function = ( B) + (C ) (f) This OI22 gte cn e used s 2-input inverting multiplexer y connecting C = s select signl. Then, = B if C is, while = if C is. Section.4.8 shows wy to improve this multiplexer design. B C B C FIGURE.9 CMOS compound gte for function = ( + B + C) Exmple.2 Sketch sttic CMOS gte computing = ( + B + C). SOLUTION: Figure.9 shows such n OR-N-INVERT-3- (OI3) gte. The nmos pull-down network pulls the output low if is nd either or B or C re, so is in series with the prllel comintion of, B, nd C. The pmos pull-up network is the conduction complement, so must e in prllel with the series comintion of, B, nd C..4.6 Pss Trnsistors nd Trnsmission Gtes The strength of signl is mesured y how closely it pproximtes n idel voltge source. In generl, the stronger signl, the more current it cn source or sink. The power supplies, or rils, (V nd GN) re the source of the strongest s nd s. n nmos trnsistor is n lmost perfect switch when pssing nd thus we sy it psses strong. However, the nmos trnsistor is imperfect t pssing. The high voltge level is somewht less thn V, s will e explined in Section We sy it psses degrded or wek. pmos trnsistor gin hs the opposite ehvior, pssing strong s ut degrded s. The trnsistor symols nd ehviors re summrized in Figure.2 with g, s, nd d indicting gte, source, nd drin. When n nmos or pmos is used lone s n imperfect switch, we sometimes cll it pss trnsistor. By comining n nmos nd pmos trnsistor in prllel (Figure.2), we otin switch tht turns on when is pplied to g (Figure.2) in which s nd s re oth pssed in n cceptle fshion (Figure.2(c)). We term this trnsmission gte or pss gte. In circuit where only or hs to e pssed, the pproprite trnsistor (n or p) cn e deleted, reverting to single nmos or pmos device.

13 .4 CMOS Logic 3 nmos g g = Input g = Output s d strong s d g = g = s d degrded (c) g g = Input Output g = pmos s d degrded s d g = g = s d strong (d) (e) (f) FIGURE.2 Pss trnsistor strong nd degrded outputs Note tht oth the control input nd its complement re required y the trnsmission gte. This is clled doule ril logic. Some circuit symols for the trnsmission gte re shown in Figure.2(d). None re esier to drw thn the simple schemtic, so we will use the schemtic version to represent trnsmission gte in this ook. In ll of our exmples so fr, the inputs drive the gte terminls of nmos trnsistors in the pull-down network nd pmos trnsistors in the complementry pull-up network, s ws shown in Figure.4. Thus, the nmos trnsistors only need to pss s nd the pmos only pss s, so the output is lwys strongly driven nd the levels re never degrded. This is clled fully restored logic gte nd simplifies circuit design considerly. In contrst to other forms of logic, where the pull-up nd pull-down switch networks hve to e rtioed in some mnner, sttic CMOS gtes operte correctly independently of the physicl sizes of the trnsistors. Moreover, there is never pth through ON trnsistors from the to the supplies for ny comintion of inputs (in contrst to single-chnnel MOS, Gs technologies, or ipolr). s we will find in susequent chpters, this is the sis for the low sttic power dissiption in CMOS. g g g =, g = g =, g = Input Output g =, g = strong g =, g = strong (c) g g g g (d) FIGURE.2 Trnsmission gte g g We cll the left nd right terminls nd ecuse ech is techniclly the source of one of the trnsistors nd the drin of the other.

14 4 Chpter Introduction B V GN FIGURE.22 Bd noninverting uffer consequence of the design of sttic CMOS gtes is tht they must e inverting. The nmos pull-down network turns ON when inputs re, leding to t the output. We might e tempted to turn the trnsistors upside down to uild noninverting gte. For exmple, Figure.22 shows noninverting uffer. Unfortuntely, now oth the nmos nd pmos trnsistors produce degrded outputs, so the technique should e voided. Insted, we cn uild noninverting functions from multiple stges of inverting gtes. Figure.23 shows severl wys to uild 4-input N gte from two levels of inverting sttic CMOS gtes. Ech design hs different speed, size, nd power trde-offs. milrly, the compound gte of Figure.8 could e uilt with two N gtes, n OR gte, nd n inverter. The N nd OR gtes in turn could e constructed from NN/NOR gtes nd inverters, s shown in Figure.24, using totl of 2 trnsistors, s compred to eight in Figure.8. Good CMOS logic designers exploit the efficiencies of compound gtes rther thn using lrge numers of N/OR gtes. B C N FIGURE.24 Inefficient discrete gte implementtion of OI22 with trnsistor counts indicted 4 OR 2 2 FIGURE.23 Vrious implementtions of CMOS 4-input N gte EN EN.4.7 Tristtes Figure.25 shows symols for tristte uffer. When the enle input EN is, the output equls the input, just s in n ordinry uffer. When the enle is, is left floting ( Z vlue). This is summrized in Tle.5. Sometimes oth true nd complementry enle signls EN nd EN re drwn explicitly, while sometimes only EN is shown. EN FIGURE.25 Tristte uffer symol EN EN FIGURE.26 Trnsmission gte TBLE.5 Truth tle for tristte EN / EN / Z / Z / / The trnsmission gte in Figure.26 hs the sme truth tle s tristte uffer. It only requires two trnsistors ut it is nonrestoring circuit. If the input is noisy or otherwise degrded, the output will receive the sme noise. We will see in Section tht the dely of series of nonrestoring gtes increses rpidly with the numer of gtes.

15 .4 CMOS Logic 5 Figure.27 shows tristte inverter. The output is ctively driven from V or GN, so it is restoring logic gte. Unlike ny of the gtes considered so fr, the tristte inverter does not oey the conduction complements rule ecuse it llows the output to flot under certin input comintions. When EN is (Figure.27), oth enle trnsistors re OFF, leving the output floting. When EN is (Figure.27(c)), oth enle trnsistors re ON. They re conceptully removed from the circuit, leving simple inverter. Figure.27(d) shows symols for the tristte inverter. The complementry enle signl cn e generted internlly or cn e routed to the cell explicitly. tristte uffer cn e uilt s n ordinry inverter followed y tristte inverter. Tristtes were once commonly used to llow multiple units to drive common us, s long s exctly one unit is enled t time. If multiple units drive the us, contention occurs nd power is wsted. If no units drive the us, it cn flot to n invlid logic level tht cuses the receivers to wste power. Moreover, it cn e difficult to switch enle signls t exctly the sme time when they re distriuted cross lrge chip. ely etween different enles switching cn cuse contention. Given these prolems, multiplexers re now preferred over tristte usses. EN EN FIGURE.27 Tristte Inverter EN = = 'Z' (c) (d) EN = =.4.8 Multiplexers Multiplexers re key components in CMOS memory elements nd dt mnipultion structures. multiplexer chooses the output from mong severl inputs sed on select signl. 2-input, or 2: multiplexer, chooses input when the select is nd input when the select is. The truth tle is given in Tle.6; the logic function is = S + S. TBLE.6 Multiplexer truth tle S / S / X / X / X / X Two trnsmission gtes cn e tied together to form compct 2-input multiplexer, s shown in Figure.28. The select nd its complement enle exctly one of the two trnsmission gtes t ny given time. The complementry select S is often not drwn in the symol, s shown in Figure.28. gin, the trnsmission gtes produce nonrestoring multiplexer. We could uild restoring, inverting multiplexer out of gtes in severl wys. One is the compound gte of Figure.8(e), connected s shown in Figure.29. nother is to gng together two tristte inverters, s shown in Figure.29. Notice tht the schemtics of these two pproches re nerly identicl, sve tht the pull-up network hs een slightly simplified nd permuted in Figure.29. This is possile ecuse the select nd its complement re mutully exclusive. The tristte pproch is slightly more compct nd fster ecuse it S S S S FIGURE.28 Trnsmission gte multiplexer

16 6 Chpter Introduction S S S S S S S S S FIGURE.29 Inverting multiplexer (c) requires less internl wire. gin, if the complementry select is generted within the cell, it is omitted from the symol (Figure.29(c)). Lrger multiplexers cn e uilt from multiple 2-input multiplexers or y directly gnging together severl tristtes. The ltter pproch requires decoded enle signls for ech tristte; the enles should switch simultneously to prevent contention. 4-input (4:) multiplexers using ech of these pproches re shown in Figure.3. In prctice, oth inverting nd noninverting multiplexers re simply clled multiplexers or muxes..4.9 Sequentil Circuits So fr, we hve considered comintionl circuits, whose outputs depend only on the current inputs. Sequentil circuits hve memory: their outputs depend on oth current nd previous inputs. Using the comintionl circuits developed so fr, we cn now uild sequentil circuits such s ltches nd flip-flops. These elements receive clock,, nd dt input,, nd produce n output,. ltch is trnsprent when =, mening tht follows. It ecomes opque when =, mening retins its previous vlue nd ignores chnges in. n edge-triggered flip-flop copies to on the rising edge of nd rememers its old vlue t other times. SS SS SS SS S S FIGURE.3 4: multiplexer

17 .4 CMOS Logic Ltches ltch uilt from 2-input multiplexer nd two inverters is shown in Figure.3. The multiplexer cn e uilt from pir of trnsmission gtes, shown in Figure.3, ecuse the inverters re restoring. This ltch lso produces complementry output,. When =, the ltch is trnsprent nd flows through to (Figure.3(c)). When flls to, the ltch ecomes opque. feedck pth round the inverter pir is estlished (Figure.3(d)) to hold the current stte of indefinitely. The ltch is lso known s level-sensitive ltch ecuse the stte of the output is dependent on the level of the clock signl, s shown in Figure.3(e). The ltch shown is positive-level-sensitive ltch, represented y the symol in Figure.3(f ). By inverting the control connections to the multiplexer, the ltch ecomes negtive-level-sensitive Flip-Flops By comining two level-sensitive ltches, one negtive-sensitive nd one positive-sensitive, we construct the edge-triggered flip-flop shown in Figure.32( ). The first ltch stge is clled the mster nd the second is clled the slve. While is low, the mster negtive-level-sensitive ltch output (M) follows the input while the slve positive-level-sensitive ltch holds the previous vlue (Figure.32(c)). When the clock trnsitions from to, the mster ltch ecomes opque nd holds the vlue t the time of the clock trnsition. The slve ltch ecomes trnsprent, pssing the stored mster vlue (M) to the output of the slve ltch (). The input is locked from ffecting the output ecuse the mster is disconnected from the input (Figure.32(d)). When the clock trnsitions from to, the slve ltch holds its vlue nd the mster strts smpling the input gin. While we hve shown trnsmission gte multiplexer s the input stge, good design prctice would uffer the input nd output with inverters, s shown in Figure.32(e), to = = (c) (d) (e) (f) Ltch FIGURE.3 CMOS positive-level-sensitive ltch

18 8 Chpter Introduction Ltch M Ltch M M (c) = M (d) = M (e) (f) (g) Flop FIGURE.32 CMOS positive-edge-triggered flip-flop preserve wht we cll modulrity. Modulrity is explined further in Section.6.2 nd roust ltches nd registers re discussed further in Section.3. In summry, this flip-flop copies to on the rising edge of the clock, s shown in Figure.32(f). Thus, this device is clled positive-edge triggered flip-flop (lso clled flip-flop, register, or mster slve flip-flop). Figure.32(g) shows the circuit symol for the flip-flop. By reversing the ltch polrities, negtive-edge triggered flip-flop my e

19 .5 CMOS Friction nd Lyout 9 constructed. collection of flip-flops shring common clock input is clled register. register is often drwn s flip-flop with multi-it nd usses. In Section.2.5 we will see tht flip-flops my experience hold-time filures if the system hs too much clock skew, i.e., if one flip-flop triggers erly nd nother triggers lte ecuse of vritions in clock rrivl times. In industril designs, gret del of effort is devoted to timing simultions to ctch hold-time prolems. When design time is more importnt (e.g., in clss projects), hold-time prolems cn e voided ltogether y distriuting two-phse nonoverlpping clock. Figure.33 shows the flip-flop clocked with two nonoverlpping phses. s long s the phses never overlp, t lest one ltch will e opque t ny given time nd hold-time prolems cnnot occur..5 CMOS Friction nd Lyout Now tht we cn design logic gtes nd registers from trnsistors, let us consider how the trnsistors re uilt. esigners need to understnd the physicl implementtion of circuits ecuse it hs mjor impct on performnce, power, nd cost. Trnsistors re fricted on thin silicon wfers tht serve s oth mechnicl support nd n electricl common point clled the sustrte. We cn exmine the physicl lyout of trnsistors from two perspectives. One is the top view, otined y looking down on wfer. The other is the cross-section, otined y slicing the wfer through the middle of trnsistor nd looking t it edgewise. We egin y looking t the cross-section of complete CMOS inverter. We then look t the top view of the sme inverter nd define set of msks used to mnufcture the different prts of the inverter. The size of the trnsistors nd wires is set y the msk dimensions nd is limited y the resolution of the mnufcturing process. Continul dvncements in this resolution hve fueled the exponentil growth of the semiconductor industry..5. Inverter Cross-Section Figure.34 shows cross-section nd corresponding schemtic of n inverter. (See the inside front cover for color cross-section.) In this digrm, the inverter is uilt on p-type sustrte. The pmos trnsistor requires n n-type ody region, so n n-well is diffused into the sustrte in its vicinity. s descried in Section.3, the nmos trnsistor φ 2 φ M φ 2 φ 2 φ φ φ 2 φ φ φ 2 FIGURE.33 CMOS flip-flop with two-phse nonoverlpping clocks

20 2 Chpter Introduction O 2 p+ Sustrte Tp GN V Gte Gte n+ n+ p+ p+ Source rin rin Source nmos Trnsistor n-well pmos Trnsistor p-sustrte n+ Well Tp n+ diffusion p+ diffusion polysilicon metl GN V FIGURE.34 Inverter cross-section with well nd sustrte contcts. Color version on inside front cover. hs hevily doped n-type source nd drin regions nd polysilicon gte over thin lyer of silicon dioxide (O 2, lso clled gte oxide). n+ nd p+ diffusion regions indicte hevily doped n-type nd p-type silicon. The pmos trnsistor is similr structure with p-type source nd drin regions. The polysilicon gtes of the two trnsistors re tied together somewhere off the pge nd form the input. The source of the nmos trnsistor is connected to metl ground line nd the source of the pmos trnsistor is connected to metl V line. The drins of the two trnsistors re connected with metl to form the output. thick lyer of O 2 clled field oxide prevents metl from shorting to other lyers except where contcts re explicitly etched. junction etween metl nd lightly doped semiconductor forms Schottky diode tht only crries current in one direction. When the semiconductor is doped more hevily, it forms good ohmic contct with metl tht provides low resistnce for idirectionl current flow. The sustrte must e tied to low potentil to void forwrd-ising the p-n junction etween the p-type sustrte nd the n+ nmos source or drin. Likewise, the n-well must e tied to high potentil. This is done y dding hevily doped sustrte nd well contcts, or tps, to connect GN nd V to the sustrte nd n-well, respectively..5.2 Friction Process For ll their complexity, chips re mzingly inexpensive ecuse ll the trnsistors nd wires cn e printed in much the sme wy s ooks. The friction sequence consists of series of steps in which lyers of the chip re defined through process clled photolithogrphy. Becuse whole wfer full of chips is processed in ech step, the cost of the chip is proportionl to the chip re, rther thn the numer of trnsistors. s mnufcturing dvnces llow engineers to uild smller trnsistors nd thus fit more in the sme re, ech trnsistor gets cheper. Smller trnsistors re lso fster ecuse electrons don t hve to trvel s fr to get from the source to the drin, nd they consume less energy ecuse fewer electrons re needed to chrge up the gtes! This explins the remrkle trend for computers nd electronics to ecome cheper nd more cple with ech genertion. The inverter could e defined y hypotheticl set of six msks: n-well, polysilicon, n+ diffusion, p+ diffusion, contcts, nd metl (for friction resons discussed in Chpter 3, the ctul msk set tends to e more elorte). Msks specify where the components will e mnufctured on the chip. Figure.35 shows top view of the six msks. (See lso the inside front cover for color picture.) The cross-section of the inverter from Figure.34 ws tken long the dshed line. Tke some time to convince yourself how the top view nd cross-section relte; this is criticl to understnding chip lyout.

21 .5 CMOS Friction nd Lyout 2 GN V Sustrte Tp nmos Trnsistor pmos Trnsistor Well Tp n-well (c) Polysilicon (d) n+ iffusion (e) p+ iffusion (f) Contct Metl (g) FIGURE.35 Inverter msk set. Color version on inside front cover. Consider simple friction process to illustrte the concept. The process egins with the cretion of n n-well on re p-type silicon wfer. Figure.36 shows cross-sections of the wfer fter ech processing step involved in forming the n-well; Figure.36 illustrtes the re sustrte efore processing. Forming the n-well requires dding enough Group V dopnts into the silicon sustrte to chnge the sustrte from p-type to n-type in the region of the well. To define wht regions receive n-wells, we grow protective lyer of

22 22 Chpter Introduction oxide over the entire wfer, then remove it where we wnt the wells. We then dd the n- type dopnts; the dopnts re locked y the oxide, ut enter the sustrte nd form the wells where there is no oxide. The next prgrph descries these steps in detil. The wfer is first oxidized in high-temperture (typiclly 9 2 C) furnce tht cuses nd O 2 to rect nd ecome O 2 on the wfer surfce (Figure.36). The oxide must e ptterned to define the n-well. n orgnic photoresist 2 tht softens where p-sustrte O 2 p-sustrte Photoresist O 2 (c) p-sustrte Photoresist O 2 (d) p-sustrte Photoresist O 2 (e) p-sustrte O 2 (f) p-sustrte O 2 n-well (g) (h) p-sustrte FIGURE.36 Cross-sections while mnufcturing the n-well n-well 2 Engineers hve experimented with mny orgnic polymers for photoresists. In 958, Brumford nd Wlker reported tht Jello could e used for msking. They did extensive testing, oserving tht vrious Jellos were evluted with lemon giving the est result.

23 exposed to light is spun onto the wfer (Figure.36(c)). The photoresist is exposed through the n-well msk (Figure.35) tht llows light to pss through only where the well should e. The softened photoresist is removed to expose the oxide (Figure.36(d)). The oxide is etched with hydrofluoric cid (HF) where it is not protected y the photoresist (Figure.36(e)), then the remining photoresist is stripped wy using mixture of cids clled pirnh etch (Figure.36(f)). The well is formed where the sustrte is not covered with oxide. Two wys to dd dopnts re diffusion nd ion implnttion. In the diffusion process, the wfer is plced in furnce with gs contining the dopnts. When heted, dopnt toms diffuse into the sustrte. Notice how the well is wider thn the hole in the oxide on ccount of lterl diffusion (Figure.36(g)). With ion implnttion, dopnt ions re ccelerted through n electric field nd lsted into the sustrte. In either method, the oxide lyer prevents dopnt toms from entering the sustrte where no well is intended. Finlly, the remining oxide is stripped with HF to leve the re wfer with wells in the pproprite plces. The trnsistor gtes re formed next. These consist of polycrystlline silicon, generlly clled polysilicon, over thin lyer of oxide. The thin oxide is grown in furnce. Then the wfer is plced in rector with silne gs (H 4 ) nd heted gin to grow the polysilicon lyer through process clled chemicl vpor deposition. The polysilicon is hevily doped to form resonly good conductor. The resulting cross-section is shown in Figure.37. s efore, the wfer is ptterned with photoresist nd the polysilicon msk (Figure.35(c)), leving the polysilicon gtes top the thin gte oxide (Figure.37). The n+ regions re introduced for the trnsistor ctive re nd the well contct. s with the well, protective lyer of oxide is formed (Figure.37(c)) nd ptterned with the n-diffusion msk (Figure.35(d)) to expose the res where the dopnts re needed (Figure.37(d)). lthough the n+ regions in Figure.37(e) re typiclly formed with ion implnttion, they were historiclly diffused nd thus still re often clled n-diffusion. Notice tht the polysilicon gte over the nmos trnsistor locks the diffusion so the source nd drin re seprted y chnnel under the gte. This is clled self-ligned process ecuse the source nd drin of the trnsistor re utomticlly formed djcent to the gte without the need to precisely lign the msks. Finlly, the protective oxide is stripped (Figure.37(f )). The process is repeted for the p-diffusion msk (Figure.35(e)) to give the structure of Figure.38. Oxide is used for msking in the sme wy, nd thus is not shown. The field oxide is grown to insulte the wfer from metl nd ptterned with the contct msk (Figure.35(f )) to leve contct cuts where metl should ttch to diffusion or polysilicon (Figure.38). Finlly, luminum is sputtered over the entire wfer, filling the contct cuts s well. Sputtering involves lsting luminum into vpor tht evenly cots the wfer. The metl is ptterned with the metl msk (Figure.35(g)) nd plsm etched to remove metl everywhere except where wires should remin (Figure.38(c)). This completes the simple friction process. Modern friction sequences re more elorte ecuse they must crete complex doping profiles round the chnnel of the trnsistor nd print fetures tht re smller thn the wvelength of the light eing used in lithogrphy. However, msks for these elortions cn e utomticlly generted from the simple set of msks we hve just exmined. Modern processes lso hve 5 + lyers of metl, so the metl nd contct steps must e repeted for ech lyer. Chip mnufcturing hs ecome commodity, nd mny different foundries will uild designs from sic set of msks..5 CMOS Friction nd Lyout 23

24 24 Chpter Introduction Polysilicon Thin gte oxide p-sustrte n-well Polysilicon Thin gte oxide p-sustrte n-well (c) p-sustrte n-well (d) p-sustrte n-well (e) n+ n+ n+ p-sustrte n-well (f) n+ n+ n+ p-sustrte n-well FIGURE.37 Cross-sections while mnufcturing polysilicon nd n-diffusion.5.3 Lyout esign Rules Lyout design rules descrie how smll fetures cn e nd how closely they cn e relily pcked in prticulr mnufcturing process. Industril design rules re usully specified in microns. This mkes migrting from one process to more dvnced process or different foundry s process difficult ecuse not ll rules scle in the sme wy. Universities sometimes simplify design y using sclle design rules tht re conservtive enough to pply to mny mnufcturing processes. Med nd Conwy [Med8] populrized sclle design rules sed on single prmeter,, tht chrcterizes the resolution of the process. is generlly hlf of the minimum drwn trnsistor chnnel length. This length is the distnce etween the source nd drin of trnsistor nd is set y the minimum width of polysilicon wire. For exmple, 8 nm process hs minimum polysilicon width (nd hence trnsistor length) of.8 m nd uses design rules with

25 .5 CMOS Friction nd Lyout 25 p+ n+ n+ p+ p+ n+ n-well p-sustrte (c) p+ p+ n+ n+ p+ p+ n+ n-well p-sustrte n+ n+ p+ p+ n+ n-well p-sustrte Thick field oxide Metl Thick field oxide FIGURE.38 Cross-sections while mnufcturing p-diffusion, contcts, nd metl =.9 m. 3 Lmd-sed rules re necessrily conservtive ecuse they round up dimensions to n integer multiple of. However, they mke scling lyout trivil; the sme lyout cn e moved to new process simply y specifying new vlue of. This chpter will present design rules in terms of. The potentil density dvntge of micron rules is scrificed for simplicity nd esy sclility of lmd rules. esigners often descrie process y its feture size. Feture size refers to minimum trnsistor length, so is hlf the feture size. Unfortuntely, elow 8 nm, design rules hve ecome so complex nd processspecific tht sclle design rules re difficult to pply. However, the intuition gined from simple set of sclle rules is still vlule foundtion for understnding the more complex rules. Chpter 3 will exmine some of these process-specific rules in more detil. The MOSIS service [Piñ2] is low-cost prototyping service tht collects designs from cdemic, commercil, nd government customers nd ggregtes them onto one msk set to shre overhed costs nd generte production volumes sufficient to interest friction compnies. MOSIS hs developed set of sclle lmd-sed design rules tht covers wide rnge of mnufcturing processes. The rules descrie the minimum width to void reks in line, minimum spcing to void shorts etween lines, nd minimum overlp to ensure tht two lyers completely overlp. conservtive ut esy-to-use set of design rules for lyouts with two metl lyers in n n-well process is s follows: Metl nd diffusion hve minimum width nd spcing of 4. Contcts re 2 2 nd must e surrounded y on the lyers ove nd elow. Polysilicon uses width of 2. 3 Some 8 nm lmd-sed rules ctully set =. m, then shrink the gte y 2 nm while generting msks. This keeps 8 nm gte lengths ut mkes ll other fetures slightly lrger.

26 26 Chpter Introduction Polysilicon overlps diffusion y 2 where trnsistor is desired nd hs spcing of wy where no trnsistor is desired. Polysilicon nd contcts hve spcing of 3 from other polysilicon or contcts. N-well surrounds pmos trnsistors y 6 nd voids nmos trnsistors y 6. Figure.39 shows the sic MOSIS design rules for process with two metl lyers. Section 3.3 elortes on these rules nd compres them with industril design rules. In three-level metl process, the width of the third lyer is typiclly 6 nd the spcing 4. In generl, processes with more lyers often provide thicker nd wider toplevel metl tht hs lower resistnce. Trnsistor dimensions re often specified y their Width/Length (W/L) rtio. For exmple, the nmos trnsistor in Figure.39 formed where polysilicon crosses n-diffusion hs W/L of 4/2. In.6 m process, this corresponds to n ctul width of.2 m nd length of.6 m. Such minimum-width contcted trnsistor is often clled unit trnsistor. 4 pmos trnsistors re often wider thn nmos trnsistors ecuse holes move more slowly thn electrons so the trnsistor hs to e wider to deliver the sme current. Figure.4 shows unit inverter lyout with unit nmos trnsistor nd doule-sized pmos trnsistor. Figure.4 shows schemtic for the inverter nnotted with Width/ Length for ech trnsistor. In digitl systems, trnsistors re typiclly chosen to hve the minimum possile length ecuse short-chnnel trnsistors re fster, smller, nd consume less power. Figure.4(c) shows shorthnd we will often use, specifying multiples of unit width nd ssuming minimum length. Metl Metl2 iffusion Polysilicon spcing width 3 2 n-well Metl- iffusion Contct Metl- Polysilicon Contct Metl- Metl2 Vis 3 FIGURE.39 mplified -sed design rules 4 Such smll trnsistors in modern processes often ehve slightly differently thn their wider counterprts. Moreover, the trnsistor will not operte if either contct is dmged. Industril designers often use trnsistor wide enough for two contcts (9 ) s the unit trnsistor to void these prolems.