High Speed On-Chip Interconnects: Trade offs in Passive Termination

Transcription

1 High Speed On-Chip Interconnects: Trde offs in Pssive Termintion Rj Prihr University of Rochester, NY, USA Abstrct In this pper, severl pssive termintion schemes for high speed on-chip seril interconnect nd trde offs ssocited with them re presented. Signl declension due to reflections in high speed trnsmission lines (TL) cn be minimized by introducing dequte termintion circuit. Primry trde off involved in terminted TL is with the optimiztion of bndwidth power consumption. Secondry trdes off i.e. re bndwidth, noise mrgin power consumption re lso discussed in brief. Few guidelines re proposed which re useful in chieving contentious objectives i.e. low ltency, high bndwidth, nd low power consumption in on-chip high speed communiction. Bsis of qulittive nd quntittive nlysis presented here is the stte-of-thert literture of recent reserch. In most of the cses, it is ssumed tht reflections occur minly due to mismtching t receiver end nd proper termintion is provided t trnsmitter end. Keywords: Trnsmission Line, Pssive Termintion, On-Chip Interconnects, High Speed links. 1. Introduction Due to vrious dvntges of seril links over prllel buses they re preferred in high speed on-chip communiction. Few other obvious dvntges re lesser re on chip, lest crosstlk noise, nd reduced design complexity [1]. However, on-chip interconnect dely doesn t scle down very well s compre to gte delys with reduced feture size. This is one of the biggest bottleneck in designing low ltency on-chip interconnects. The mgnitude of problem is enormous nd often it is termed s interconnect wll problem [3]. In order to overcome on the interconnect problem designers re forced to devise high speed signling medium for on-chip ppliction. Few potentil solutions of high speed link re opticl link, wveguides, ft wires etc. These solutions fll into two ctegories some re esy to implement but not fst enough, while others re quite fst but integrtion is not esy. On contrry to this, trnsmission lines cn be esily implemented s on-chip thick trces similr to ft RC wires. One of the disdvntges of seril communiction is tht serilized dt increses the switching ctivity. This incresed switching ctivity on signl line results into incresed power consumption. Keeping this in mind, the interconnect wll problem lso forces designer to cre bout power consumption in ddition to low ltency nd high bndwidth. Due to the fct tht RC wires re not fst enough s compre to gtes for sme technology node so they re on the verge of becoming obsolete. Trnsmission lines on the other hnd inherently fst due to the fct tht signl trvels s wve re one of the most promising lterntive for fst on-chip ppliction s long s other fst wy of communiction i.e. opticl wveguides re not economicl. If we reinforce the lossless condition the trnsmission lines, s oppose to simple wires, cn operte t much higher speed virtully close to speed of light. However, trnsmission lines hve their own shortcomings i.e. reflections from lod on mismtch, ttenution during propgtion. Focus of this survey pper is to study the vrious undesired effects which degrde the performnce of trnsmission line. Section 2 is n overview of on-chip interconnects modeling. Section 3 presents brief description of trnsmission line theory nd metrics of trnsmission line. In section 4, vrious on-chip termintion schemes re discussed with their dvntges nd disdvntges. These bsic schemes re the core of the most of the stte-of-rt work in designing high speed on-chip links using trnsmission lines. Qulittive nlysis nd reltionships of vrious prmeters re presented in section 5. Section 6 concludes the study nd serves s rough high-level guideline for designing the high speed systems. Observtions nd findings re bsed on most recent reserch work.

2 2. On-Chip Interconnects: Modeling Mjor problem with prllel bus rise due to clock skew nd crosstlk noise. This mndtes designers to look for seril interconnects for high speed pplictions. This section focuses on vrious models of interconnects rnging from the simplest nd lest ccurte to most complex nd most ccurte. Most of the models discussed here re in distributed in nture s oppose to lumped models where the whole interconnect is represented using one single component. Simplest seril on-chip interconnects cn be thought of distributed RC network, shown in fig 1 below. This modeling is more ccurte thn lumped component modeling where distributed cpcitnce nd resistnces re modeled with just single resistnce nd one cpcitnce. R wire C wire Fig. 1 Distributed RC wire model Although Lump RC model is esy to comprehend but it is lest ccurte nd fr from the rel behvior of todys interconnects. This is the reson precisely tht lumped RC model hven t been considered in this study t the first plce. Distributed RC model is most ccurte for low frequency thus low speed ppliction. The threshold of low nd high is decided by the overll wire impednce. It lies t the point where the overll impednce is dominted by wire resistnce insted of wire inductnce. In RC wire, electricl signl propgtion is somewht similr to diffusion phenomen. Time response of RC model is similr to cscded RC first order system. Dely nd rise time re proportionl to the squre of the length of the wire. One obvious observtion is tht s feture size shrinks, globl wires don t tend to scle down, the propgtion dely nd rise time both degrde rpidly. This degrdtion in dely, proportionl to squre of length, poses serious chllenges on chieving low ltency with high bndwidth [7]. A simple solution to enhnce the performnce of RC wires is to insert the repeters. Repeters re kind of signl booster inserted, in pipelined mnner, t regulr intervls s shown below in fig 2. d Repeter C wire d R wire Fig. 2 Repeted RC wire with regulr repeters Insertion of repeters solves problem to some extent. It breks down big RC problem into n smll RC problems. Dely now becomes proportionl to length of wire which ws originlly proportionl to squre of length [7]. However, this performnce gin comes t the cost of incresed die-re repeters re some sort of logic blocks nd higher power consumption. In some cses, the incresed re nd power is beyond the cceptble limits so this implementtion my not be prgmtic in those cses. As the frequency of opertion increses RC wire models re no more ccurte. The reson is tht wire impednce is dominted by overll inductnce (ωl>>r) rther thn resistnce. This region of opertion is referred LC region. In LC region wire behves like trnsmission line rther thn RC wire. As oppose to RC wires, in trnsmission line propgtion of signl hppens very similr to electromgnetic wve propgtion. This propgtion is much fster inherently lmost close to the speed of light s compre to RC wire signl propgtion. Need of repeters is lso eliminted when interconnects re modeled s trnsmission line. A lossless trnsmission line cn be modeled s distributed LC network without ny resistive component, shown in fig 3. Inherently fst trnsmission lines suffer from their own problems i.e. reflections due to mismtching, dispersion due to line resistnce in non-idel cses. L Fig. 3 Lossless LC trnsmission line In the following subsequent sections we would look more closely into trnsmission line model nd try to C

3 understnd the trde offs involved into implementtion of trnsmission lines. As energy trvels in TL towrds the lod it is dispersed rther thn dissipted s it does in RC wire. Per unit length dely (D) of lossless line is given by following expression. D = plc w 1 On-chip trnsmission lines re implemented either using metllic micro strips or co-plner trces. These trces hve their own sheet resistnce thus trnsmission lines re not completely lossless. A more ccurte model s oppose to fig. 3 is shown below with series resistnce. R Fig. 4 Lossy RLC trnsmission line Another more ccurte model RLGC model includes prllel conductnce pth from line to ground fter every series R nd L. Although RLC model is not most ccurte even then Telegrphers equtions for the nlysis of trnsmission line still hold vlid. This dispersion cused by series resistnce my result into Inter Symbol Interference (ISI) for high speed communiction. One of the solutions to llevite the ISI nd del with dispersion problem is optimum termintion of trnsmission line. In generl, on-chip interconnects re connected to receiver stge without ny termintion s shown in figure below. Fig. 5 On-Chip TL without termintion Optimum termintion elimintes the ISI possibility nd llows source to deliver the mximum power to the lod. It lso removes the reflections which re present when chrcteristic impednce of trnsmission line is not mtched with the lod impednce. Another dvntge of optimum termintion is tht it voids the source oscilltion which cn rise due to dditive nture of reflective wve from fr end. L C Pssive termintion mtches the chrcteristic impednce of trnsmission line to the input impednce of receiver stge. Introduction of lossy pssive components such s resistnce (R) nd conductnce (G) increses the bndwidth tremendously. However, the introduction of such components increses the power dissiption s well. One wy to counter the effect is to operte the signl line t lowered voltge swing thus minimize the power consumption. Also terminted line exhibits low rise time which helps in chieving the high bit rte [1]. Improved ISI nd low power consumption comes t the cost of sophisticted complex receiver design more specificlly sense mplifier t the receiver end becuse the output voltge swing is now smller compred to open-circuit trnsmission line cse. A clssicl chllenge in designing of trnsmission line bsed on-chip interconnect is minimize the power consumption while mintining the low ltency nd high throughput. Next severl sections would discuss the vrious termintion schemes using pssive components nd their pros nd cons. 3. Metrics of Trnsmission Line This section is brief overview of vrious mtrices nd chrcteristics of trnsmission line before. Content of this section is simple enough nd detiled prtil wve equtions for trnsmission line nd their solutions re voided Chrcteristic Impednce Chrcteristic Impednce (Z o ) of trnsmission line is defined s the rtio of voltge (V + ) nd current wve (I + ) propgting in forwrd direction from source to lod [6]. Z o = V + w f R + jωl = s f G + jωc I ` 2 Eqution (1) is vlid for RLGC trnsmission line. Where R, L, G, C re resistnce, inductnce, conductnce nd cpcitnce per unit-length of trnsmission line. This cn be esily modified for RLC model by substituting G = 0. For lossless trnsmission line (R = G = 0) expression (2) reduces to expression (3) s below [3].

4 Z o = w s f L ` 3 ` V z =V + ` o z e γz + ` o z e 5 ` 3.2. Voltge Stnding Wve Rtio The voltge component of stnding wve in uniform trnsmission line consists of the forwrd wve (with mplitude V + ) superimposed on the reflected wve (with mplitude V - ). Reflections occur s result of discontinuities, such s n imperfection due to impednce mismtching either t the lod or long the line. VSWR is defined s following. VSWR = V ` z mx f 1 + Γ ` = f 4 V z min Γ Figure below depicts propgtion of EM wve in mismtched TL. Yellow vectors re ctul signl while EM wve propgtes from source to lod. Cyn vectors re mplitude of reflected wve which is due to mismtching t lod end. First term in expression (5) is wve propgting in forwrd direction wheres second term denotes wve propgting in bckwrd direction. γ is propgtion constnt which cn be expressed s following. b cb wc γ=α+jβ = r R + jωl G + ` 6 α is ttenution constnt which is n indiction of deteriortion of voltge cross the line. Attenution constnt is function of frequency nd increses with the frequency. 4. High Speed TL Termintion Schemes In this section, vrious remedies of reflection problem re described. In generl ny interconnect opertes either in RC region (low frequency mode) or LC region (high frequency mode). Effective impednce in either of the region is dominted either by resistnce or by inductnce. Qulittive plot below depicts the two regions. Fig. 7 LC nd RC region: On-Chip Interconnect Fig. 6 VSWR nd reflections in mismtched TL Voltge t ny point in the TL is resultnt of two vectors forwrd nd reflected which is depicted by green curve Reflection nd Attenution In RLGC model voltge nd current t ny point in trnsmission line re the solution of fmous telegrpher s prtil differentil equtions. Generl solution of telegrpher s eqution cn be expressed s below. In RC region, the overll impednce is lmost constnt becuse the frequency dependent component is still smll. As the frequency increses, frequency dependent component grows in mgnitude nd overll impednce is dominted by inductnce. Vrying nture of impednce increses the reflection which is due to mismtch of impednces. In open-circuit TL reflection losses due to this mismtch re quite high nd t some point the whole signl is reflected bck. This requires some sort of termintion before the receiver stge. Once line impednce is dominted by inductnce we need to tret the ordinry wires s trnsmission lines. Reflections which occur from discontinuity mke

5 line noisy nd my lso led to source oscilltion. Fr end nd ner end voltge wveform re no more sme s input signl rther it is superimposed wveform of forwrd nd bckwrd voltge wveform. In open circuited trnsmission line the ner nd fr end voltges t stedy sttes re given by following expressions. It is ssumed tht trnsmission line is properly mtched t ner end. V ner =V fr =V ` 7 Expression (7) is vlid for low frequency of opertion. At high frequency due to the reflections the fr end stedy stte voltge reches to zero. Due to this, ordinry un-terminted wires cn t be used for high speed communiction. For optimlly terminted TL the equivlent expressions for ner nd fr end voltges re s following. V ner = V dd f ; V 2 fr =V ner ` 8 It is ssumed tht trnsmission line is properly terminted t trnsmitter end. This is typiclly the cse in generl becuse the intention is to dmp the second nd subsequent reflections. In rest of the section we present some simple techniques to reduce the reflections. suffers from few drwbcks. After introduction of shunt resistnce there is pth between signl line nd ground which lwys dissiptes the power. Another concern is tht due to voltge divider the voltge swing t the output is smller thn wht it ws in open-circuit cse. This sounds like drwbck in some sense but it is not. First, typicl voltge drop required eye opening voltge cn be chieved with the right choice of termintion. Second, stte-of-rt sense mplifier cn esily detect the low swing signl with typicl vlue is 200 mv pek-to-pek. The dvntge of reduced swing is tht the power consumption is lso low. Trde off for low power is reduced noise mrgin which would require sophisticted trnsceiver design. Another concern is tht due to process vrition the vlue of on-chip resistnce my chnge nd which my led to mismtch. The good news is tht exct vlue of resistnce relly doesn t mtter. Only constrint in choosing the resistnce vlue is tht it should be more thn optiml vlue Distributed Shunt Resistnce This technique is proposed by reserch group t University of Cliforni, Sn Diego. The ide is to introduce the dditionl conductnce pths to compenste for the ttenution due to series resistnces [3]. They cll it Surfliner rchitecture due the reson tht it looks similr to rilwy trck. The nme of rilwy trck from Sn Diego to Sn Luis Obispo is Surfliner Shunt Resistnce The simplest wy to eliminte the reflections is to mtch the line impednce by plcing prllel termintion t receiver side. Reflection coefficient is zero t the fr end fter perfect termintion. However, it is not lwys expected to terminte the line with the impednce exctly sme s chrcteristic impednce. Fig. 9 Surfliner rchitecture for high speed TL Lekge conductnce per unit-length G is chosen in such wy so tht it stisfies the condition of distortion less trnsmission. Following expression is for distortion less trnsmission line. G = RC L f 9 Fig. 8 Prllel termintion using resistnce This technique increses the bndwidth by reducing the reflections nd rise time. However, t sme time it According to uthors, Simultion results show tht using 65nm technology, the proposed scheme cn chieve 15Gbits/s bndwidth over 20mm on-chip seril link without ny equliztion. Also they clim

6 tht this pproch offers 6x improvement in dely nd 85% reduction in power consumption over conventionl RC wire with repeted buffers. conductnce nd put termintion resistor in the receiver end. This is proposed by sme group who proposed Surfliner rchitecture Series Resistnce Series termintion hs become very common in tody s high-speed designs especilly in multireceiver systems. It hs the two desirble ttributes of termintion schemes single component nd no DC current drw t ll. The series termintion resistor is plced t the front end s oppose to prllel termintion t the fr end [5]. Fig. 12 Distributed conductnce with shunt R According to uthors, this technique hs 15x improved jitter compre to nked TL. 5. Qulittive Anlysis nd Plots 5.1. Anlysis nd Trde offs Fig. 10 Series termintion in high speed TL In this cse the fr end is left open-circuit. Therefore, there is 100% positive reflection from the fr end of the TL. However, the series resistnce dmps the second nd subsequent reflections t ner end nd voids the perturbtion in signl line. This kind of termintion is especilly dvntges when there re multiple receivers nd single trnsceivers Shunt Resistnce with Cpcitor Yet nother vrition of prllel termintion is the ddition of cpcitor in series with the prllel resistnce. The primry dvntge of this is tht the cpcitor blocks DC current t low frequency, so there is no stedy-stte current flowing through the termintion t the low speed. At first glnce it would pper tht this strtegy otherwise hs ll the dvntges of the prllel termintion strtegy. However, the cost of this, of course, is the dded component. Fig. 11 Prllel RC termintion 4.5. Distributed Conductnce with Shunt R This is essentilly combintion of two techniques mentioned before. The ide is to evenly insert shunt Work reported in this section is qulittive in nture rther thn quntittive. Results re lso derived nlyticlly from simplifiction of complex expressions. Most of the results re vlid for stte-ofthe-rt systems. Verifiction of the chrcteristics nd results through simultion wsn t possible due to time constrints Eye Opening Voltge nd Bit Rte Eye opening voltge depends very much on the bit rte. For two different trnsmission lines the reltionship is depicted in plot below. Fig. 13 Eye opening voltge for vrious bit rte Eye opening voltge is inversely proportionl to the bit rte. Eye opening voltge reches to 0 for opencircuit TL t pprox 50 Gbps. This is due the fct tht t this speed the reflections re so prominent tht whole incident wve is reflected bck. In contrry to this, terminted TL lthough hs lower eye voltge t low bit rte but it is pretty consistent nd provides high bndwidth. Some study reports tht bout 100mV eye-opening t 100Gbps signling cn be chieved with pssive termintion. Thus resistive termintion is necessry for high-speed signling.

7 Energy/ Bit nd Termintion Impednce One serious concern in using resistive termintion is incresed sttic power dissiption. When resistor is connected between the signl line nd the ground, sttic current flows through the termintor. Figure below shows the energy per bit of 20Gbps signling [2]. Interconnect under test is 5mm long nd the chrcteristic impednce is 100Ω. Fig. 15 Eye opening vs normlized termintion Three different curves re for vrious ttenution constnts. As ttenution increses the eye-opening voltge degrdes [2]. However, the conclusion is tht towrds the right side the curves re flts fter some optiml vlue of termintions. This lso verifies the clim tht exct vlue of impednce doesn t mtter s long s it is more thn optiml vlue. Fig. 14 Energy/ Bit for vrious impednces The key observtion from bove plot is tht s we increse the termintion impednce the energy consumption decreses nd eventully we rech to open-circuit cse. This mens lrge impednce is not right choice becuse it would consume more silicon re nd still the reflections would be present. On the other hnd, if we choose the impednce smll vlue it increses the power consumption. The broken verticl line represents the optimum vlue of termintion impednce which is equl to TL impednce. However, designer my choose vlue grter thn optiml termintion in order to minimize the energy consumption nd yet chieve the benefits of pssive termintion i.e. high bndwidth etc Eye opening nd Normlized Impednce Normlized impednce is the rtio of ny impednce in the system to the chrcteristic impednce of TL. Figure 15 shows the reltionship between mximum eye-opening voltges for vrious ttenution prmeters. The ttenution constnt is the function of normlized termintion impednce. The x- xis is the normlized impednce nd the input bit rte is fixed to some specific vlue, 20Gbps in this cse [2] Step Response of Lossy Trnsmission Line The plot below shows the step response of vrious trnsmission lines. Typicl lengths of these TLs re from few mm to tens of mm. Fig. 16 Step response of vrious trnsmission lines Smller TL hs smll rise time thus signl propgtion hppens rpidly. However, longer TL exhibit slow RC response thus they re not dequte for fst switching ppliction Chllenges in Implementtions One of the mjor chllenges in designing the system with trnsmission lines s on-chip interconnects is modeling of TL components using current CAD tools [1]. Optimiztion of trnsmission lines with lots of prmeters nd vrious trdes off involved could be dunting thus complexity nd efforts is incresed. To llevite this problem to some extent, designers my prioritize their performnce metrics nd optimize for s per the requirement rther thn optimizing for bsolute performnce.

8 Modeling of lossy trnsmission line involves finding the vlues of inductnces. Inductnce extrction in itself is mjor chllenge to current EDA tools. It involves finding the return pth for current to estimte the loop which is bsis of on-chip inductnce estimtion. Current tries to find minimum impednce pth to return in order to complete the loop. The return pth is not simple to figure out becuse it chnges with the frequency s overll impednce chnges. In ddition to this, modeling of skin effects nd other losses re not trivil by ny mens. The serious chllenges re to decide bout the fctors such s cceptble ttenution, reflection nd dispersion. Also deciding the optimum termintion vlue is not trivil becuse lower vlue of termintion resistnce, close to Z o, would increse the power consumption with incresed bndwidth. Incresing the resistnce, pproching towrds open-circuit cse, would require lrger re on chip nd lso result into incresed reflection. Overll, CAD modeling, simultion nd optimiztion of such systems is complex nd chllenging. 6. Conclusion 6.1. Prllel versus Seril Mjor chllenge in prllel buses ws to minimize the noise induced by prllel running wires. Also mjor portion of power is consumed by repeters in prllel bus rchitecture system. Power consumed by ll on-chip interconnects could be s high s 30% of the totl chip power consumption [7]. These problems hve been solved by seril interconnects to gret extent. Seril trnsmission line uses significntly less number of repeters thus mjor portion of power is sved. Another significnt frction of power is sved from the proper termintion of trnsmission lines becuse the optimlly terminted trnsmission lines operte t low voltge with high rise time Pssive Termintion nd Reflections Two mjor chllenges in implementtion of trnsmission line re voiding the reflections nd ttenutions. Reflections re overcome by proper optiml termintion. However, these termintions involve the pssive components like resistnces nd cpcitnces. Implementtion of on chip cpcitor with precision is not gurnteed due to process vrition. Also s cpcitor consumes lot of on chip rel stte it my not be good ide to implement some of these termintion schemes in re constrined designs. Onchip resistnce lso consumes significnt re. In this cse, one needs to gurntee the tolernces of resistnce vlue nd sensitivity of compenstion circuit on resistnce vrition [2] Power sving using Trnsmission Lines Some experimentl results show tht trnsmission lines could esily chieve the dt rte s high s 50 Gbps [6]. It my not be required to run the circuits t this high speed ll the time. In such cses, some more power cn be sved by operting t low frequency by doing voltge-frequency scling or constnt voltge scling. The motivtion behind the ide is to design system for high speed nd either use for high performnce (with incresed power consumption) or low power (with decresed performnce) mode Trnsmission Lines nd Prmeters Plots in section 5 cn be used to design the systems for vrious needs. This section provides design guideline of resistive termintion from the fundmentl prmeters, i.e. bit rte, chrcteristic impednce nd ttenution. Termintion strtegies cn be effective in eliminting, or t lest minimizing, trnsmission line reflections. But no individul strtegy is perfect. Ech one hs trdeoff of some type. It is designers responsibility to come up with optiml solution. 7. References [1] Michel P. Flynn nd Joshu J. Kng, Globl Signling over Lossy Trnsmission Lines, IEEE ICCAD [2] A. Tsuchiy et l, Design Guideline for Resistive Termintion of On-Chip High-Speed Interconnects, in proceeding IEEE Custom Integrted Circuit Conf., [3] H. Chen, R. Shi, C. Cheng, nd D. Hrries, Surfliner: A distortion less electricl signling scheme for speed of light on-chip communictions, in Proc. Asi South Pcific Design Automtion Conf., [4] Chun-Chen Liu et l, Pssive Compenstion for High Performnce Inter-Chip Communiction IEEE ICCD [5] Yulei Zhng et l, On-Chip Bus Signling Using Pssive Compenstion, IEEE EPEP [6] H. Zhu et l, Approching Speed-of-light Distortion less Communiction for On-chip Interconnect, ASP DAC [7] R. Ho, K. Mi nd M. A. Horowitz, The future of wires, Proceedings of the IEEE, April 2001.