CMOS Current-Mode Circuits for Data Communications

Transcription

1 CMOS Current-Mode Circuits for Data Communications

2 ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN: ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del Rio, R., Medeiro, F., Perez-Verdu, B., de la Rosa, J.M., Rodriguez-Vazquez, A. ISBN SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: LOW-POWER LOW-VOLT AGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifanio da Franca, Jose Vol. 867, ISBN: DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, Jose (Eds.) Vol. 860, ISBN: ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC'S Claes and Sansen Vol. 854, ISBN: MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and Steyaert Vol. 843, ISBN: SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN:

3 CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS FEI YUAN Associate Professor Department of Electrical and Computer Engineering Ryerson University Toronto, Ontario, Canada ^Spri inger

4 Fei Yuan Department of Electrical and Computer Ryerson University Toronto, Ontario, Canada Engineering CMOS Current-Mode Circuits for Data Communications Library of Congress Control Number: ISBN e-isbn ISBN e-isbn Printed on acid-free paper Springer Science-hBusiness Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science-t-Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now know or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights springer.com

5 This book is dedicated to my parents for the sacrifice that they made for the education of their son

6 Contents Dedication Preface Acknowledgments v xiii xvii 1. VOLTAGE-MODE VERSUS CURRENT-MODE : A CRITICAL COMPARISON Ideal Current-Mode Circuits Topology Duality of Current-Mode Circuits Characteristics of Current-Mode Circuits Input and Output Impedances Bandwidth Slew Rate Propagation Delay Supply Voltage Sensitivity ESD Summary DESIGN TECHNIQUES FOR CURRENT-MODE CIRCUITS Basic Current Amplifiers Output Impedance Boosting Techniques Basic Cascodes Regulated and Multi-Regulated Cascodes Pseudo-Cascodes Low-Voltage Cascodes Input-Impedance Reduction Techniques Input-Capacitance Reduction Active Feedback Bootstrapping 21

7 viii CMOS CURRENT-MODE CIRCUITS FORDATA COMMUNICATIONS 2.4 Mismatch Compensation Techniques Power Reduction Techniques Bandwidth Enhancement Techniques Resistor Series Peaking Inductor Series Peaking Current Feedback Dynamic Range Improvement Techniques Active Inductors Topologies of Active Inductors Noise of Active Inductors Dynamic Range Summary WIRE CHANNELS Resistances Capacitances Inductances ModeHng of Wire Channels Lumped RC Model Distributed RC Model Elmore Model Transmission-Line Model Transmission Line Effects Termination Schemes Series Termination Parallel Termination Parallel AC Termination Thevenin Termination Broadband Impedance Matching Networks Passive Impedance Matching Active Impedance Matching Summary ELECTRICAL SIGNALING FOR HIGH-SPEED DATA LINKS Voltage-Mode Signaling versus Current-Mode Signaling - A Comparison Voltage-Mode Signaling 84

8 Contents ix Single-Ended Signaling Fully Differential Signaling Pseudo-Differential Signaling Voltage-Mode Incremental Signaling Current-Mode Signaling Unipolar Current-Mode Signaling Bipolar Current-Mode Signaling Current-Mode Incremental Signaling Summary CURRENT-MODE TRANSMITTERS Introduction Serialization Transmission-Gate Multiplexers Pseudo-nMOS Multiplexers Current-Steering Multiplexers Lee's Multiplexer Yang's Multiplexer Current-Mode Multiplexers Drivers Inverter Drivers Open-Drain Drivers Low-Voltage Differential-Signaling Drivers Class A Current-Mode Drivers Class AB Current-Mode Drivers Pre-Emphasis Voltage-Mode Pre-Emphasis Current-Mode Pre-Emphasis Current-Mode Power-Area Efficient Pre-Emphasis Current-Mode Direct Pre-Emphasis Serial Link Transmitters ADC-Based Transmitter Current-Mode Class A 2PAM Transmitter Current-Mode Class AB 2PAM Transmitter Current-Mode Power-Insensitive Class AB 2PAM Transmitter Current-Mode Area-Power Efficient 4PAM Transmitter 132

9 X CMOS CURRENT-MODE CIRCUITS FORDATA COMMUNICATIONS Current-Mode Direct Pre-Emphasis 4PAM Transmitters Summary CURRENT-MODE RECEIVERS Current-Mode Pre-Amplifiers Clock and Data Recovery Using Phase-Picking Samplers x-0versampling Clock and Data Recovery x-Over sampling Clock and Data Recovery x-0versampling Clock and Data Recovery Clock and Data Recovery Using Phase-Tracking Phase-Frequency Detectors Charge Pumps Voltage-Controlled Ring Oscillators Current-Controlled Ring Oscillators Current-Mode Phase-Locked Loops Data Recovery Using Current Integration Voltage-Mode Integrating Receivers Current-Mode Integrating Receivers Noise Characteristics of Phase-Locked Loops Phase Noise of Oscillators Phase Noise of Phase-Locked Loops Summary SWITCHING NOISE AND GROUNDING OF MIXED- MODE CIRCUITS Introduction Effects of Switching Noise On-Chip Supply Voltage Fluctuation and Ground Bouncing Noise Margin Reduction DC Operation Point of Analog Circuits Analysis of Switching Noise Triangle Waveform Approach a-power Law Approach Improved a-power Law Approach Partial Buff'er Switching Approach Peak Switching Noise Approach 229

10 Contents xi Application Specific Device Modeling Approach Switching Noise Reduction Techniques Multiple Bonding Pads and Pins Pre-Skewing Decoupling Capacitors Balanced Drivers Current-Mode Logic Circuits Grounding in Mixed-Mode Circuits Substrate Modeling Analog and Digital Grounding Substrate Grounding Passive Guard Rings Active Guard Rings Summary ESD PROTECTION ESD Sources Human-Body Model Machine Model Charged Device Model ESD Protection Principles Current Limiting of n-well Resistors Avalanche Multiplication of nmos Transistors ESD Protection Devices n-well Resistors Diodes Gate-Grounded nmos Transistors Gate-Coupled nmos transistors Silicon-Controlled Rectifiers ESD Protection Circuits Basic ESD Protection Circuits Challenges in ESD Protection Polysilicon Diodes Distributed ESD Protection Circuits ESD Protection with Negative Capacitors Poly Back-End Ballast with Segmentation Soft-Grounded-Gate nmos MET Domino nmos MET 265

11 xii CMOS CURRENT-MODE CIRCUITS FORD ATA COMMUNICATIONS 8.5 Chapter Summary 266 References 269 Index 287

12 Preface Current-mode circuits, where information is represented by the branch currents of the circuits rather than the nodal voltages as of voltage-mode circuits, possess many unique and attractive characteristics over their voltage-mode counterparts including a small nodal time constant, high current swing in the presence of a low supply voltage, reduced distortion, a low input impedance, a high output impedance, less sensitive to switching noise, and better ESD immunity. CMOS current-mode circuits have found increasing applications in telecommunication systems, instrumentation, analog signal processing, multiprocessors, highspeed computer interfaces, and the backplane of complex electronic systems. This book deals with the analysis and design of continuous-time CMOS current-mode circuits for data communications over wire channels. CMOS current-mode sampled-data networks, such as switchedcurrent circuits, and current-mode logic circuits, are excluded. The book is organized as the followings : Chapter 1 examines the distinct characteristics of ideal voltage-mode and current-mode circuits. The topology duauty of these two classes of circuits is investigated using the concept of inter-reciprocity and adjoint network. A critical comparison of the input and output impedances, bandwidth, slew rate, propagation delay, signal swing, supply voltage sensitivity, and ESD sensitivity of voltage-mode and current-mode circuits is provided. Chapter 2 investigates design techniques that improve the performance of low-voltage current-mode circuits including input impedance reduction, output impedance boosting, bandwidth enhancement, mismatch compensation, power consumption reduction, and swing improvement. Chapter 3 investigates the modeling of wire channels. The resistance, capacitance, and inductance of wire channels are examined. A special

13 XIV attention is given to the inductance of wire channels as it dominates the behavior of the channels at high frequencies. Lumped RC models, distributed RC models, Elmore models, and transmission-line models of wire channels are studied. Broadband termination schemes and impedance matching networks for data communications over wire channels are also investigated. Chapter 4 is concerned with the electrical signaling for high-speed data communications over wire channels. Voltage-mode signaling that includes single-ended, fully differential, pseudo-differential, and incremental signaling is addressed first. It is followed by an in-depth investigation of current-mode signaling that includes unipolar signahng, bipolar signaling, and incremental signaling. Chapter 5 focuses on the design of current-mode serial hnk transmitters. Parallel-to-serial data conversion, pre-emphasis for the compensation of the high-frequency loss of wire channels and its implementations, and serial-link drivers are investigated in detail. The design of Class A and Class AB current-mode transmitters and their performance are examined. Chapter 6 deals with the design of current-mode serial-link receivers. Current-mode pre-amplifiers are studied first. It is followed by an indepth investigation of three distinct clock and data recovery approaches, namely, phase-picking, phase-tracking, and current integrating. The building blocks of phase (delay)-locked loops including phase-frequency detectors, charge pumps, and voltage (current)-control oscillators are studied in detail. Current-mode phase-locked loops are introduced. The noise behavior of oscillators and that of phase-locked loops are also investigated. Chapter 7 investigates the characteristics and analysis of switching noise in mixed-mode circuits. Techniques that minimize switching noise are studied. The grounding of mixed-mode circuits including substrate grounding, passive and active guard rings, and their effect on the performance of mixed analog-digital circuits are investigated. Chapter 8 deals with both the principles, devices, and circuit techniques of ESD protection. An special attention is given to the recent advance in ESD protection of high-speed circuits. This book is developed from the lecture notes of senior undergraduate and graduate courses EE8502/ELE863 (VLSI systems) and EE8503 (VLSI circuits for data communications) that I introduced and taught in the Department of Electrical and Computer Engineering at Ryerson University. The materials of the book are presented with an emphasis on both the evolution of each class of circuits and an in-depth comparison of their advantages and limitations. The large number of research pa-

14 PREFACE XV pers cited in the book provide readers with a rich resource to carry out a further exploration in this fast-evolving field. The examples given in the book are implemented in either TSMC-0.18/im 1.8V and UMC-0.13/xm 1.2V CMOS technologies, and analyzed using Spectre and SpectreRF from Cadence Design Systems with BSIM3.3v device models that count for both the parasitics and high-order effects of MOS devices. Readers are assumed to be familiar with the basics of microelectronic devices and circuits, signals and systems, and the fundamentals of analog and digital communication systems. The book can serve as the text book of an one-semester senior undergraduate or junior graduate course on CMOS current-mode circuits for data communications. It can also serve as a reference book for IC design engineers in the area of data communications and computer interfaces. Although an immense amount of effort has been made in the preparation of the manuscript, flaws and errors might still exist due to erring human nature. Suggestions and corrections are gratefully appreciated. FEI YUAN MARCH 2006

15 Acknowledgments I would like to take this opportunity to express my sincere gratitude to the Natural Science and Engineering Research Council of Canada, Canadian Microelectronics Corporation, Ryerson University, and Micronet for their support to our research on integrated circuits and systems including our on-going exploration on CMOS-MEMS microsystems. Special thanks go to my graduate students B. Sun, J. Jiang, A. Li, T. Wang, D. DiClemente, and A. Tang for fruitful discussion in our weekly research meetings from which many of the original ideas on CMOS current-mode circuits, such as inductor series peaking, currentmode phase-locked loops, current-mode class A and class AB transmitters, current-mode incremental signaling, and current-mode integrating receivers emerged. The support from the Department of Electrical and Computer Engineering of Ryerson University where I introduced and taught senior undergraduate and graduate courses ELE734 (Low-power CMOS digital integrated circuits), ELE704/EE8501 (CMOS analog integrated circuits), ELE863/EE8502 (VLSI systems), and EE8503 (VLSI circuits for data communication) is gratefully acknowledged. The undergraduate and graduate students of these classes deserve a special recognition for many of their comments and corrections to the lecture notes of these courses upon which a large portion of this book is based. My heartfelt appreciation goes to the reviewers of the initial proposal of the book. Professor Mohammed Ismail (Ohio State University), the series editor of Analog Circuits and Signal Processing, deserves a special thank-you for his comments on the initial proposal of the book and on the manuscript of the book upon which revisions were made. The book could not have been in its present form without the comments and suggestions from the reviewers and the series editor on both the scope and focus of the book.

16 XVlll The editorial staff of Springer-Verlag, especially Mr. Alex Greene, the editorial director of engineering, have been wonderfully supportive and have made the writing of this book an enjoyable journey. Finally and most importantly, this book could not have been possible without the understanding and patient of my family. I am indebted to my wife Jing for her love and support during the writing of text, and to our daughter and son, Michelle and Jonathan, for the joy and wonderful violin concertos. The return of the warm weather and our planned trip to China this summer will give me the opportunity to make up the lost weekends and holidays in the last six months due to the writing of this text.

17 Chapter 1 VOLTAGE-MODE VERSUS CURRENT-MODE : A CRITICAL COMPARISON The information processed by lumped electric networks can be represented by either the nodal voltages or branch currents of the networks. The former are referred to as voltage-mode circuits whereas the latter are known as current-mode circuits. Together, they provide a complete characterization of the behavior of the networks. Voltage-mode circuits have received a much broader attention and found a much wider range of applications as compared with their currentmode counterparts despite the fact that the concept of ideal currentmode circuits, similar to that of ideal volt age-mode circuits, emerged approximately 40 years ago [1, 2]. This is reflected by a handful monographs on current-mode circuits [3-8] but countless texts on voltagemode circuits. The reasons for such a popularity that voltage-mode circuits have been enjoying can be summarized as follows : (i) The nodal voltage of electric networks can be measured conveniently using voltmeters without modifying the topology and affecting the operation of the networks. On the contrary, the measurement of the branch current of the networks are less convenient and often requires a change of the configuration of the networks or additional circuitry, (ii) The infinite impedance looking into the gate of MOS transistors makes these devices an ideal choice for the realization of voltage-mode circuits, especially in cascade configurations, such as multi-stage voltage amplifiers, (iii) The ease to obtain a high voltage gain of voltage-mode circuits using techniques such as cascodes and regulated cascodes. (iv) High supply voltages available in the past such that low-voltage design was not of a critical concern, (v) Switching noise was not a critical issue with the presence of a high supply voltage, (vi) Low speed requirements permit the charge and discharge of nodal capacitors over a long period of time.

18 2 Voltage-Mode Versus Current-Mode : A Critical Comparison The aggressive reduction in the supply voltage and the moderate reduction in the device threshold voltage of CMOS technology have greatly affected the performance of CMOS voltage-mode circuits, typically reflected by a reduced dynamic range, an increased propagation delay, and reduced low noise margins. The impact of supply voltage reduction on the performance of current-mode circuits, however, is less severe as compared with that of voltage-mode circuits. This is because the design emphasis of current-mode circuits is on branch currents rather than nodal voltages. The usefulness of CMOS current-mode circuits in combating the difficulties arising from the reduction of the supply voltage and the increase in the operation speed has received an increasing attention both from industry and academia recently. The different design focuses of voltage-mode and current-mode circuits, arising from the intrinsic characteristics of nodal voltages and branch currents, result in distinct design principles. This chapter provides a brief comparison of the characteristics of voltage-mode and current-mode circuits. Such a comparison is by no intention to enter the debate on whether current-mode is more superior over voltage-mode or vice versa. Rather, our goal is to provide a clear picture of the unique and distinct characteristics of these two classes of circuits such that circuit designers can make a full use of these distinct properties to achieve a specific design objective. The chapter is organized as follows : Section 1.1 introduces the concept of ideal voltage-mode and current-mode circuits from which the distinct characteristics of these circuits are unfold. Section 1.2 investigates the intrinsic relation between the topology of voltage-mode circuits and that of current-mode circuits using the theory of inter-reciprocity and adjoint network. In Section 1.3, the characteristics of voltage-mode and current-mode circuits in terms of input and output impedances, bandwidth, propagation delay, slew rate, sensitivity to power fluctuation and ground bouncing, and ESD are compared in detail. The chapter is summarized in Section Ideal Current-Mode Circuits An ideal voltage-mode circuit possesses an infinite input impedance, a zero output impedance, and a constant voltage gain. It can be best represented by an ideal operational amplifier introduced in 1960s [9]. The infinite input impedance and a zero output impedance of operational amplifiers not only enable a convenient cascade of operational amplifiers without a loading effect, they also ensure that the characteristics of these circuits are determined by the external elements only and are independent of the characteristics of the operational amplifiers.

19 Ideal Current-Mode Circuits X z iz Vx = 1 O' 0 Jz.,-:"" >-. \^y \ix, o±i oj [vz ^y Vx = 0 {0) 0 \^y\ 1 0* 0 Ux\ Jz^, Oil 01 IvzJ (a) (b) (c) Figure 1.1. (a) Current conveyors; (b) CCI±; (c) CCII±. Unlike ideal voltage-mode circuits, an ideal current-mode circuit has the characteristics of a zero input impedance, an infinite output impedance, and a constant current gain. Because current amphfication will result in a high level of static power consumption, the current gain of ideal current-mode circuits is set to unity historically. The first ideal currentmode circuits are the first generation current conveyors, denoted by CCI±, where the polarities specify whether the direction of the output current is the same as that of the current flowing into node x or not [1]. As shown in Fig. 1.1 (a), the current conveyor has three terminals : the current input terminal x, the control terminal y, and the output terminal z, and is characterized by the equations given in Fig. 1,1(b). Note that node y is the control node whose current and voltage are identical to those of the input node x. The impedance looking into nodes X and y is zero ideally. Node z is the output node with an infinite output impedance. The application of CCI± becomes difficult because both nodes x and y have a zero input impedance ideally in order to sink currents. The control node y needs to take a control current rather than a control voltage, which is usually difficult to obtain in practical designs. To alleviate this problem, the second-generation current conveyors, denoted by CCIIdb, where the control node y is changed from a current-control node to a voltage-control node, were proposed [2]. The behavior of CCII± is characterized by the equation given in Fig. 1.1(c). The voltage-control node y has an infinite input impedance ideally. The current-control node x, on the other hand, has a zero input impedance ideally, enabling a current to fiow into the node without any resistance. Because the output of the conveyer is a current, the load of the conveyer must be of a low impedance, Vz = 0 holds ideally. Similar to operational amplifiers that have numerous practical implementations, current conveyors can also be realized in a number of ways and new CCII± with an emphasis on speed, power consumption, and low supply voltage are emerging [10-14]. In addition, the apphcations of CCIIib bear a strong resemblance to those of operational amplifiers where the characteristics of systems employing CCIIib are determined by

20 4 Voltage-Mode Versus Current-Mode : A Critical Comparison the passive elements external to CCII± only. CCIIit have found a broad spectrum of applications such as active filters[15, 16], impedance conversion [13], oscillators [13, 17], and instrumentation amplifiers [11, 18], to name a few. 1,2 Topology Duality of Current-Mode Circuits Tellegen's theorem is a fundamental law for lumped electrical networks [19-22]. The weak form of Tellegen's theorem incorporates the branch voltages and currents of two different networks N and N having the identical topology and is given by Bi ^ B2 ^ Y^{vbk - ibvb) + X](^6^6 - ibh) = 0 (1.1) 6=1 6=1 where i^ and f^, i^ and v^ denote respectively the branch currents and voltages of N and iv, Bi and B2 denote the number of input/output branches and that of internal branches, respectively [23]. To find out the input-output relation oi N, N is constructed in such a way that the second summation in (1.1) vanishes. A natural way to achieve this is for each internal element of A^, we construct its counterpart in N such that Vbib -hvb = 0. (1.2) Elements that satisfy (1.2) are said to be inter-reciprocal. The circuit N constructed in this way is called the adjoint network of N [21, 23]. To derive the adjoint network of the second-generation current conveyers, consider CCII- shown in Fig We construct its adjoint network as per (1.1) and (1.2) {viii ~ iivi) + {v2i2 - i2h) + {vsh - hh) = 0. (1.3) Making use of ii = 0, t;i = V2^ is = 12^ and vs = 0, Eq.(1.3) becomes vi{k + h) + hih - V2) = 0. (1.4) To ensure that (1.4) holds for arbitrary v^ and z/., fc = 1,2,3, we impose h = h and 'O2 = 'O3. The adjoint network of CCII- is also a CCIIwith its terminal characteristics shown in Fig The output node of the adjoint network is node 1 and the two control nodes are nodes 2 and 3 with node 3 the voltage-control node and node 2 the current-control node. Similarly, one can shown that the adjoint network of CCII+ is

21 Characteristics of Current-Mode Circuits 5 depicted by ii = 12 and V2 = '63. The adjoint network of CCII+ is neither a CCII+ nor a CCT-[24]. It is both a negative current follower and a negative voltage follower, and is represented by the symbol CCII= hereafter to distinguish from CCII±. The output node of the adjoint network of CCII+ is node 1. The voltage-control node is node 3 and the current-control node is node 2. 3 ^ O Figure 1.2. CCII+/CCII- and their adjoint networks. The current-control node x remains unchanged while the output node z and voltage-control nodes y of CCII+/CCIIand their adjoint networks are inter-changed. The topology duality of voltage-mode and current-mode circuits is illustrated using the current-conveyor based voltage amplifier shown in Fig. 1.3(a). Replace the CCII+ and CCII- with its corresponding adjoint network and the voltage buffer with a CCII+, we arrive at the adjoint network of the voltage amplifier, as shown in Fig.1.3(b). MH (a) (b) Figure 1.3. (a) CCII-based voltage amplifier; (b) Adjoint network of CCII-based voltage amplifier.

22 6 Voltage-Mode Versus Current-Mode : A Critical Comparison 1,3 Characteristics of Current-Mode Circuits Input and Output Impedances It was pointed out earlier that a voltage-mode circuit is featured by a large input impedance and a low output impedance. On the contrary, a current-mode circuit possesses a low input impedance and a high output impedance. The loading effect arising from the finite output impedance of current-mode circuits or equivalently the non-zero input impedance can be studied using Fig. 1.4(a) where the input source is represented by its Norton equivalent. The load current is given by 1o2 1 1-f Zo^l 1 jlo (1.5) where ZQ and Zin are the output impedance of the driving stage and the input impedance of the driven stage, respectively. Note that Zin<^Zo was assumed in simplifying (1.5). To minimize the loading effect, Zir^<^Zo is required for current-mode circuits. Similarly, when the input is represented by its Thevenin equivalent, the loading effect of voltage-mode circuits can be studied using Fig. 1.4(b) with the load voltage.o2 = ^. o - ( l - ^ ). o. (1.6) To minimize the loading effect, Zin^Zo is required for voltage-mode circuits. (a) (b) Figure 1.4- Loading effect, (a) Current-mode circuits; (b) Voltage-mode circuits Bandwidth The bandwidth of voltage-mode and current-mode circuits can be best compared using the building blocks of voltage/current-mode circuits shown in Fig.1.5. Because a well-designed current-mode circuit

23 Characteristics of Current-Mode Circuits 7 has a large output impedance and a small input impedance, the load impedance z^^o holds. As a result, M2 of the basic current mirror is not subject to Miller effect. The only pole of the basic current mirror is at the gate of Mi^2 with the pole frequency given by 9ml Cgsl + Cgs2 + Cgd2 ^^^^ Due to the existence of the floating gate-drain capacitor Cgd, the commonsource configuration is subject to Miller eff'ect with Miller capacitances Cmi = Cgd{l+gmro) at the gate and Cm2 = Cgd{l + ^:^) at the drain, where VQ and gm are the output impedance and transconductance of the transistor, respectively. The pole at the input called Miller pole, is given by LUin^ 1= ; -T, (1-8) Rs [Cgs + Cgd{l + gmro)\ where Rs is the resistance of the source. The output pole is estimated from ujo^ /^ ^.^ \, where Cin is the input capacitance of the load stage. The common-gate configuration is not subject to Miller effect due to the absence of floating capacitors. The pole at the input is given by uin ^ wh" ^^^ ^^^ P^^^ ^^ ^^^ output is computed from ^o ~ roic ^-fc- ) "^^^ source follower is also free of Miller eflfect simply because its small-signal voltage gain is approximately unity. The Miller capacitances at the gate and source are given by Cmi^Cm2^0. The pole at the input is given by ujin^ji h ^^^ ^^^ P^^^ ^^ ^^^ output is given For practical applications, Cin and To are often large, the dominant pole of the common-source, common-gate, and source follower amplifiers is usually at the output node. The pole frequency of the basic current mirror is therefore smaller as compared with the pole frequency of the basic voltage-mode amplifiers Slew Rate The slew rate of voltage-mode and current-mode circuits are compared using the common-source configuration and the basic current mirror shown in Fig When a square-waveform current is appued to the basic current mirror, because Mi is in the saturation, ij:)si is independent of VDSi when the channel length modulation is neglected. The rate of the change of the output current depends upon how fast Cgsir^2

24 Voltage-Mode Versus Current-Mode : A Critical Comparison J2 G)^ ^gd fi^^ ' - ^ C ^gsl ^ ^gs2 (a) (b) Figure 1.5. Bandwidth comparison of voltage-mode and current-mode circuits, (a) Basic current mirror; (b) Common-source amplifier; (c) Common-gate amplifier; (d) Source follower. Cgsi + Cgs2 is charged or equivalently how fast the gate voltage of Mi^2 rises. Because a gsl'^2~ + l^l^nc'oa,{-j^) ^{VGS1^2 - VT? = Jl + Hn, (1.9) dt VGSi^2 increases with iin- For fixed biasing currents, the larger the amphtude of the input, the higher the slew rate of the output current. JUT Figure 1.6. Slew rate comparison of voltage-mode and current-mode circuits, (a) Basic current mirror; (b) Common-source amplifier; (c) Basic differential pair. For voltage-mode circuits, the slew rate is usually determined by the output stage because of the large width of the transistors in the output stage and the large capacitance of the load. Consider the commonsource amplifier, when a sufficiently low voltage Vmin is applied to the input, the transistor switches off and Co is charged by J only, we have \^\ 'T'' When Vin = Vmax^ CQ is discharged via the transistor L "*' Jrise,max ^^^ with the slew rate \%^\ = r> V > where Ron is the channel resisl "^^ i fall,max RonCo' ^^

25 Characteristics of Current-Mode Circuits 9 tance of the transistor in the triode. The preceding results reveal that the slew rate of common-source amplifier is set by the biasing current, the width of the transistor, and the output capacitance. It is independent of the amphtude of the input voltage. A similar conclusion can be drawn for the voltage-mode differential pair configuration Propagation Delay For digital circuits, the average propagation delay is a widely used figure-of-merit depicting the transient behavior of the circuits. It is directly related to the swing of the signal [25]. Neglect both the resistance and inductance, the average rising (falling) time of the voltage of a node, denoted by At, is determined from pat Cn{AVn) = / i{t)dt = lavgat, (1.10) where lavg is the average current charging/discharging the node, Cn is the capacitance of the node, i{t) is the net current fiowing into/out the node, and Avn is the voltage swing of the node. Eq.(l.lO) reveals that a small propagation delay can be achieved by either minimizing the swing of the voltage of the node or maximizing the current charging and discharging the capacitance of the node. For voltage-mode circuits, Avn is constrained by the signal-to-noise ratio requirements and must be kept sufficiently large, resulting in a slow transient response. Unlike voltage-mode circuits, the information carriers of current-mode circuits are branch currents. The variation of nodal voltages can be kept small as long as the current of the branches associated with the nodes is large. Consider Fig.1.7, from Bi B2 AVn = ^n( X! Aiin^i,^ - ^ Aio^b2) ^ (l-h) 6i=l 62=1 where Zn is the impedance of the node, Bi and B2 are the number of input and output branches connected to the node, respectively, we conclude that for a given Avn, a large current variation can be obtained as long as Zn is kept small. The small nodal voltage variation of currentmode circuits lowers the amount of time needed to charge/discharge C^, resulting in a faster transient response. This is one of the key advantages of current-mode circuits Supply Voltage Sensitivity The effect of VJDD and ground fluctuations on the output voltage (current) of CMOS circuits is of a critical concern in mixed-mode circuits

26 10 Voltage-Mode Versus Current-Mode : A Critical Comparison 0,1 -^^^0.1 Figure 1.7. Variation of nodal voltages and branch currents of current-mode circuits. because both analog and digital circuits often share the same supply voltage and ground. Supply voltage sensitivity, defined as [26] S'vnn dvo ^^^ = ^77^. dvdd (1-12) is a measure of the effect of the variation of the supply voltage on the response of the circuits. Assume the supply voltage is changed from VDD and VDD + AVOD, where AVDD is a random variable with zero mean. For practical circuits, AVDD<^VDD holds and the small-signal analysis approach can be employed to analyze the effect of AVDD on the response of the circuits. Consider the common-source amplifier shown in Fig. 1.8(a). M2 is biased in the saturation and behaves as a current source. The smallsignal equivalent circuit of the amplifier for supply voltage sensitivity analysis with junction capacitances neglected is shown in Fig. 1.8(b). At low frequencies where Cgs and Cgd are neglected, we have AV, +, +. ^'^ "882* <i> < go2 ^ V^ ^jsl <p < go\ \7 ^ml^*! ml gsl (a) (b) Figure 1.8. Supply voltage sensitivity analysis of voltage-mode circuits. (a) Common-source amplifier; (b) Small-signal equivalent circuit.

27 Summary 11 QVo r 9m2 9ol + 9o2 {roi\\ro2)gm2' (1.13) The above result shows that AVDD is directly amplified with a large voltage gain. It is worthy noting that Fig.1.8(a) is the common-gate amplifier with vin the biasing voltage of Mi, which behaves as a current source, and AVDD the input of the common-gate configured M2. Now let us consider the circuit shown in Fig The load is a current mirror with the source current provided by an ideal current source J. Using a small-signal analysis, it can be shown that ^VDD 9o2' (1.14) As compared with (1.13), because go<^9m^ the current-mode circuit is less sensitive to the fluctuation of the supply voltage. Also seen is that the effect of AVDD on VQ is mainly due to the finite output impedance ro2 of the load current mirror. AVDD So2 T7 < (a) (b) Figure 1.9. Supply voltage sensitivity analysis of current-mode circuits, (a) Currentmirror amplifier; (b) Small-signal equivalent circuit ESD A large number of ESD (electrostatic discharge)-induced damages of MOSFETs is due to the breakdown of the gate-oxide insulator, especially when the thickness of the gate-oxide tox is scaled down aggressively in deep sub-micron CMOS technologies. Voltage-mode circuits are particularly vulnerable to ESD strikes as the input node of these circuits is usually the gate of MOSFETS, a high-impedance node. No low-impedance paths from the input pads to the ground exist to discharge electrostatic charge accumulated at the pads, as shown in Fig On the contrary, the low-impedance characteristics of the input pads of current-mode circuits prevent the accumulation of static charge at the pads, as shown in Fig.1.10.

28 12 Voltage-Mode Versus Current-Mode : A Critical Comparison Bonding wire y- Bonding pad (jr) (a) (b) Figure ESD sensitivity, (a) Voltage-mode circuits; (b) Current-mode circuits. 1.4 Summary The intrisic differences and topological relation of ideal voltage-mode and current-mode circuits have been examined. It was followed with an in-depth investigation into the input and output impedance, bandwidth, slew rate, propagation delay, supply voltage sensitivity, and ESD of practical voltage-mode and current-mode circuits. It has been shown that current-mode circuits offer comparable bandwidth to that of highbandwidth voltage-mode circuits, such as common-gate amplifiers and source followers. Unlike voltage-mode circuits whose slew rate is set by their dc biasing currents, the slew rate of current-mode circuits is proportional to the amplitude of input currents, making them attractive for apphcations where a large slew rate is required. The low swing of the nodal voltage of current-mode circuits also makes them particularly attractive for apphcations where a small propagation delay is essential. The low input impedance of current-mode circuits makes them less sensitive to ESD stress.

29 Chapter 2 DESIGN TECHNIQUES FOR CURRENT- MODE CIRCUITS The rapid down-scale of the feature size of MOS devices, the aggressive reduction in the supply voltage, and the moderate reduction in the threshold voltage of modern CMOS technologies have greatly affected the performance of CMOS current-mode circuits, reflected by a small dynamic range, a reduced effective gate-source voltage, a low device output impedance, and an increased level of device mismatches. This chapter examines the design techniques that improve the performance of low-voltage CMOS current-mode circuits. The chapter is organized as follows : Section 2.1 examines the characteristics of basic current amplifiers. Section 2.2 investigates the techniques that boost the output impedance of current-mode circuits. Section 2.3 examines the techniques that lower the input impedance of current-mode circuits. Section 2.4 presents a balancing network approach for eliminating the mismatchinduced output offset current of current-mode circuits. In Section 2.5, an effective power reduction technique called current-branching is investigated. Section 2.6 introduces resistor series peaking, inductor series peaking, and current feedback for bandwidth improvement of currentmode circuits. Section 2.7 looks into circuit techniques for dynamic range improvement, specifically the characteristics of cla^ss AB current amplifiers. In Section 2.8, our focus is on the topologies and characteristics of CMOS active inductors. The applications of active inductors will be given in later chapters of the book. The chapter is summarized in Section ,1 Basic Current Amplifiers The schematic of basic CMOS current amplifiers is shown in Fig.2.1(a). Because a well-designed current-mode circuit possesses a small input

30 14 Design Techniques for Current-Mode Circuits impedance and a large output impedance, it is reasonable to assume that the load impedance is sufficiently small. As a result, M2 is not subject to Miller effect. Under a perfect matching condition and neglect the channel length modulation, the current transfer function is given by where A = ^r^ and gmi toh Iin{s) - + 1' Qml Cgsl + Cgs2 + Cgd2 (2.1) (2.2) The input impedance of the basic current amplifier is given by ^in\^) 1 5ml ^ + 1 ^^6 (2.3) The input impedance can be lowered by either increasing the width of Ml or increasing the biasing current. The former lowers the bandwidth whereas the latter increases the static power consumption. J AJO) (a) (b) (c) Figure 2.1. (a) Basic current amplifier; (b) Noise sources in basic current amplifier; (c) Input-referred noise-voltage and noise-current generators of basic current amplifier. The output impedance is given by Zo^ro2 approximately. It was shown in [27] that the output impedance of MOSFETs in deep sub-micron CMOS technologies is small. The finite output impedance of MOSFETs gives rise to a change of the output current IQ when the output voltage Vo varies. Because io = gm2'^gs-^9o2vo and iin = {gmi +9oi)vgs, we have rhn + go2vo 1 + ^ 9ml