SoC Interconnect Modeling Venkata Krishna N. Dhulipala

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1 SoC Inerconnec Modeling Venkaa Krishna N. Dhulipala Absrac Mos embedded sysems of oday are buil using he SOC echnology for large scale producion. As echnology advances delay of ransisors and local inerconnecs scales down and in his way he local clock frequency is projeced o increase rapidly. Scaling he ransisors makes local inerconnecs shorer and resuls in smaller delay. However, since chip area is projeced o increase, lengh of global inerconnecs increases and herefore heir delay. For insance, he key soluions for reducing delay of global inerconnecs can be hough of as increasing he wire cross-secional area and insering repeaers while reaining a good wiring densiy. Wiring densiy on he oher hand inroduces signal inegriy issues. Also, he communicaion beween he SOC and memories ouside he chip happens hrough off-chip inerconnecs, so an opimal pariion for on and off-chip inerconnecs is required. These differen radeoffs necessary for SOC inerconnec modeling are discussed in deail in his repor. I. Inroducion The wires linking ransisors ogeher are called inerconnec and play a major role in he performance of modern sysems. Fig.1 shows a pair of adjacen wires. These wires have a widh w, lengh l, hickness, and spacing of s, from heir neighbors and have a dielecric heigh h beween hem and he conducive layer below. Earlier, low densiy SoC chips had relaively slower ransisors and wider and hicker wires which had low resisance. Under hose circumsances, wires could be reaed as ideal equipoenial nodes wih lumped capaciance. Bu oday, ransisor swiching frequencies are much higher and he wires have become narrower, driving up heir resisance such ha wire RC delay exceeds gae delay. Moreover, he wires are packed very closely ogeher and hus a large fracion of heir capaciance is o heir neighbors, resuling in crossalk. Also, on-chip inducance is now becoming a facor for sysems wih fas edge raes and closely packed buses. Considering all of hese facors, circui design is now as much abou engineering he wires o exrac opimal performance and reap he benefis of reducing feaure size. This repor is organized by inroducing he inerconnec modeling blocks in secion II, hen he issues wih inerconnec are discussed in secion III followed by he mehods of improving delay in secion IV and concluded wih he curren and fuure rends and innovaions in secions V, VI. w s l h Fig. 1 II. Building Blocks of Inerconnec Modeling Resisance Resisance of a uniform slab of conducing maerial can be expressed as R = (ρ/ ). (l/w) (1) where ρ is he resisiviy of he conducor and is a fixed propery of he meal being used for he wire.

2 Capaciance An isolaed wire over he subsrae (silicon layer over which ransisors are buil and is ypically grounded) can be modeled as a conducor over a ground plane. The wire capaciance has wo major componens: he parallel plae capaciance of he boom of he wire o he ground and he fringing capaciance arising from he fringing fields along he edge of a conducor wih finie hickness. In he addiion, a wire adjacen o a second wire on he same layer can exhibi capaciance o ha neighbor. The classic parallel plae capaciance formula is C = (ε ox /h). wl (2) The fringing capaciance is more complicaed o compue and requires numerical field solver for exac resuls. We see ha capaciance ineracions beween layers is quie complex in oday s CMOS processes used o build SoC. A conservaive upper bound on capaciance can be obained assuming ha he layers above and below he conducor of ineres are solid ground planes. Similarly, a lower bound can be obained assuming here are no oher conducors in he sysem excep he subsrae. The upper bound can be used for propagaion delay and power esimaion while he lower bound can be used for conaminaion delay (minimum delay) calculaions before laying ou an SoC. A cross-secion of he model used for capaciance upper bound calculaion is shown in Fig.2. The oal capaciance of he conducor of ineres is he sum of is capaciance o he layer above, he layer below and he wo adjacen conducors. If he layers above and below are no swiching, hey can be modeled as ground planes and his componen of capaciance is called C gnd. Theoreically, wires will have some capaciance o furher neighbors, bu in pracice capaciance is infiniesimal and can be ignored because mos elecric fields erminae on he neares conducors. C gnd = C bo + C op C oal = C gnd +2 C adj (3) s w h2 Cop Cadj h1 A B C Cbo Fig. 2 Delay Inerconnec increases delay for wo reasons. Firs, he wire capaciance adds loading o each gae. Second, long wires have significan resisance ha conribues disribued RC delay or fligh ime. The disribued resisance and capaciance of a wire can be approximaed wih a number of lumped elemens. Of he many approaches he Π model is he mos popular which gives an accuracy of up o 3%, he model is shown in Fig.3, R I O C/2 C/2 Fig. 3 If he resisance of he inpu buffer I is Rin and he oupu load offered by he oupu buffer O on he righ hand side is Cou, hen Elmore Delay models says ha delay of he circui wih inerconnecs is give by,

3 τ = C/2 (Rin) + (C/2 + Cou) (Ri + R) (4) This gives us an approximae hand calculaion o esimae he delay of a circui given he lumped capaciance and resisance values. Inducance Global signal and clock wires are roued wih large widhs and hicknesses a he op levels of he meal o minimize delays. This decreases he resisance of he wires, making heir inducive impedance comparable o he resisive par. Z=R+jwL, when wl is comparable o R, inducive effecs mus be considered. As he clock frequency increases and he rise imes decrease, elecrical signals comprise more and more highfrequency componens, making he inducance effecs more significan. Example of Inducance Effecs (a) Over/under-shoo edges, (b) L di/d volage drop, (c) Long range crossalk, and (d) f-dependen R III. Issues due o increased Package Densiy and Feaure Size Reducion Signal Inegriy and Crossalk The mos imporan Signal inegriy problems are: 1) crossalk, 2) Overshoo (signal rising momenarily above he power supply volage or below ground), 3) reflecion (echoing back a porion of a signal when i reaches he end of inerconnec), 4) signal skew (he difference in arrival ime of one source signal o differen receivers). The occurrence of crossalk fauls is aribued o he fac ha a wire no only serves as a conducor of elecrons bu also includes parasiic resisor (a low frequencies), capacior (a mid-range frequencies), inducor (a high frequencies) and anenna (a very high frequencies). From Fig.2 we may see ha wires A, B and C affec each oher hrough coupling capaciance which is also called he Miller capaciance. If boh a wire and is neighbor are swiching, he direcion of he swiching affecs he amoun of charge ha mus be delivered and he delay of he swiching. The charge delivered o he coupling capacior is, Q = Cadj ΔV, where ΔV is he change in volage beween A and B. ΔV migh change depending on wheher he swiching in he same direcion or differen or idle. Aggressor and vicim models of crossalk deerminaion have been developed o deal wih he compuaion of crossalk. In essence i is imporan o remember ha he delay is improved/worsened by addiion of crossalk from neighboring wires. There are many possible design and fabricaion soluions o margin and minimize crossalk problems beween inerconnecs. These soluions include: 3-D layou modeling and parasiic exracion, accurae RLC simulaion of on-chip power grid, using decoupling capaciors o limi he maximum dv/d, insering repeaers/buffers on inerconnecs and shielding wires. IV. Improving Inerconnec Delay Repeaers We see ha due o he increase in he lengh of he delay lines he signal of ineres ge aenuaed and migh resul in an undesired ransiion/resul. To cope wih his problem an opimal number of repeaers have o be insered along he lengh of he wire o mainain signal inegriy. Repeaers if made of good buffers also help in eliminaion of crossalk effecs by driving a in a direcion ha is funcionally desired. Fig. 4 Consider he lengh of a wire l divided ino N segmens, for he enire lengh of he, we see from equaions 1 and 2, ha delay RC is proporional o l 2. From Fig.3, dividing he Π model segmen ino N equal pars we see ha he capaciance of he signal segmen is give by C.l/2N and he resisance is given by R.l/N. Hence, he delay using Elmore model can be wrien as, Τ pd = C.l/2N (Rin) + (C.l/2N + Cou) (Ri + R.l/N) (5)

4 The idea is o minimize delay by insering he opimal number of repeaers, so by parial differeniaion of he above resul wih respec o N i.e., δτ pd / δn = 0, we ge, l/n =[2RinCou/(RC)] 1/2 (6) The above resul is very imporan for quick hand compuaion of diving a given lengh of a wire segmen o ge he minimal delay. On and off-chip Inerconnecs Scaling he ransisors increases overall chip area and he lengh of global inerconnecs increases and herefore heir delay. The key soluions for reducing delay of global inerconnecs are increasing he wire cross-secional area and insering repeaers. However, using fa wires decreases he wiring densiy. Offchip inerconnecs usually have very large cross-secional area and herefore, hey have negligible loss. In his way some of he long global inerconnecs may be roued hrough he prined wiring board (PWB). However, since PWB wiring densiy is small, very few inerconnecs may be roued hrough he board. An opimal pariion beween on-chip and off-chip inerconnecs is required which resuls in highes performance. I has been heurisically deermined ha inerconnecs for of lengh l such ha, lmax < l < 2Dchip, (where lmax = Dchip, Dchip being he edge size of he chip) should be on-pwb o have he highes global clock frequency. V. Curren Tools Trends in Inerconnec Modeling Place and Roue (P&R) ools like Magma s Manle and Synopsys s Asro provide daa o he iming analyzer by back-annoaing he laid ou SoC s capaciance and resisance in lumped (delay modeling) or coupled (crossalk modeling) forma hrough IEEE Sandard Parasiic Exracion File (SPEF), Sandard Delay Forma (SDF) or he binary SPEF. Cadence s Allegro is one of he advanced ools ha is used o model chip-o-board inerconnecs. Allegro allows plaform users o race a signal as i moves from an IC's I/O buffers and hrough redisribuion layers, raversing die bump pads, package subsraes, connecors and pc boards. VI. Fuure Trends and Innovaions Parallel Repeaer-Inserion Mehodologies for SoC Inerconnecs Work ill now has been resriced o serial repeaers operaing when inerconnec inducive effecs are no significan. I is proven in ha parallel repeaers ouperform serial repeaers in erms of delay, power and silicon area when regeneraing signals in SoC inerconnecs. Inerconnec Delay Aware RTL Bus Archiecure A quorum of researches in Georgia Insiue of echnology demonsraed a mehodology o generae a cusom bus archiecure using accurae esimaions of inerconnec delay. To improve bus delay accuracy, hey alered he bus Verilog regiser ransfer level (RTL) specificaion based on inerconnec delay esimaions and used early in he design phase. VII. Conclusion Due o he limiaions posed by inerconnecs; designers oday are no able o efficienly reap he benefis of reducing feaure sizes and frequency scaling. Towards his end many advanced models are being researched and deployed concurrenly o model he higher order effecs in inerconnecs ha arise in lower device geomeries. Inerconnec delay effecs are being incorporaed and aken ino accoun in he early design and archiecure phase by inroducing delay headroom. Fuure of inerconnec modeling calls for design of noise-canceling inerconnecs which is an acive field of research wherein he wires are design o rejec (o he leas minimize) effec of neighboring high frequency nes. Mixed signal SoC call for more sringen design consrains on he way digial inerconnecs are laid over analog nes. A possible research area o increase wiring densiy would be o make high frequency resisan analog nes (wih inbuil low pass filers) o rejec digial noise of adjacen nes. Many such advanced design echniques can be researched, validaed, designed and deployed o be able o maximize he benefi and leverage on echnology progresses.

5 VIII. References [1] N. Wese, D. Harris, CMOD VLSI Design, A Circuis and Sysems Perspecive, hird ediion [2] Kyeong Keol Ryu, Alexandru Talpasanu, Vincen J. Mooney, Inerconnec Delay Aware RTL Verilog Bus Archiecure Generaion for an SoC, Cener for Research on Embedded Sysems and Technology School of Elecrical and Compuer Engineering, Georgia Insiue of Technology. [3] Shen Lin, Inerconnec Modeling and Design for Giga-Herz Circuis and Sysems, Hewle Packard Labs. [4] Falah R. Awwad, Mohamed Nekili, Venkaanarayana Ramachandran, On Modeling of Parallel Repeaer-Inserion Mehodologies for SoC Inerconnecs, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY [5] Zhang Jinlin, Chen Chaoyang, Shen Xubang, An Efficien Deec Model for Crossalk Fauls on SOC inerconnecs, Insiue of Image Recogniion and Arificial Inelligence, he key LAB of Minisry of Educaion, HuaZhong Universiy of Science and Technology. [6] Mike Sanarini, Cadence plaform models chip-o-board inerconnec, EE Times, March, 2004.

P. Bruschi: Project guidelines PSM Project guidelines.

P. Bruschi: Project guidelines PSM Project guidelines. Projec guidelines. 1. Rules for he execuion of he projecs Projecs are opional. Their aim is o improve he sudens knowledge of he basic full-cusom design flow. The final score of he exam is no affeced by