Optimizing Data Encoding Schemes to Reducing Energy Consumption in Network on Chip

Transcription

1 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) RESEARCH ARTICLE OPEN ACCESS Opimizing Daa Encoding Schemes o Reducing Energy Consumpion in Nework on Chip Jeeva anusha 1, Dr.V.Thrimurhulu 2 1 II M.Tech VLSI SD Suden, CR Engineering College, Tirupahi, Chioor (Dis) A.P, India, 2 Professor, Head of ECE Dep., CR Engineering College, Tirupahi, Chioor (Dis) A.P, India, 1 anu.jeeva4@gmail.com, 2 vmurhy.v@gmail.com Absrac The power dissipaed by he links of a nework-on-chip.he power dissipaed by he oher elemens of he communicaion subsysem, namely, he rouers and he nework inerfaces. we presen a se of daa encoding schemes o reduces he power dissipaed by he links of an Nework on chip. In proposed schemes are general and ransparen wih resc o he Nework on chip (i.e., heir applicaion does no require any modificaion of he rouers and archiecure). We shows he boh synheic and real raffic scenarios of he effeciveness of he proposed schemes, which allow o save up o 51% of power dissipaion and 14% of energy consumpion wihou any significan rformance degradaion and less han 15% area overhead in nework inerface. Keywords: Coupling swiching aciviy, daa encoding, inerconnecion on chip, low power nework-on-chip, power analysis. I. INTRODUCTION SHIFTING from a silicon echnology he resuls in faser and more power efficien gaes bu slow and more power hungry wires[1]. In his, more han 50% of he dynamic power is dissipaed hrough inerconnecs in curren processors, and his is exced o rise o 65% 80%of he nex several years [2]. Global inerconnec lengh does no suiable for smaller ransisors and local wires. Chip size remains consan because he chip funcion coninuously increase he RC delay and increases exponenially. A 32/28 nm, he RC delay in a 1-mm global wire a he minimum pich is 25 higher han he inrinsic delay of a wo-inpu NAND gae. If he raw compuaion he abiliy of insancing more and more cores in a single silicon die, i increasing he scalabiliy issues, due o he efficien and reliable communicaion beween increasing he no of cores is he real problem[3] he scalabiliy and variabiliy issues ha characerize he ulra deep submicron meer era in Nowadays, he on-chip communicaion issues as relevan as, in some cases more relevan han, he compuaion-relaed issues [4]. In fac, he communicaion subsysem increases impacs in he radiional design objecives, including cos, area, rformance, power dissipaion, energy consumpion, reliabiliy, ec. As echnology shrinks, he more significan fracion of he oal power budge is complex in sysem-on-chip. In his par, we focus on aimed o reducing he power dissipaed by he nework links. In fac, he power dissipaed by he nework links by rouers and nework inerfaces and heir conribuions o increase he echnology scale [5].we presen a se of daa encoding schemes oraed a fli level on an end-o-end basis, which allows us o minimize he boh swiching aciviy and coupling swiching aciviy of he rouing pah links and raversed by he packes. The proposed encoding schemes, which are ransparen o he rouer implemenaion, are presened a boh algorihmic level and he archiecural level, and assessed by means of simulaion and synheic and real raffic scenarios. The analysis akes ino accoun of several ascs of he design, including silicon area, power dissipaion, and energy consumpion. The resuls show ha by using he proposed encoding schemes up o 51% of power and 14% of energy can be saved wihou any significan degradaion in rformance and wih 15% area overhead in he Nework inerface. II. RELATED WORKS AND CONTRIBUTIONS In he nex several years, he availabiliy of chips wih 00cores is foreseen [6]. In hese chips, oal sysem power budge is dissipaed by inerconnecion neworks. The design of power-efficien inerconnecion neworks has been focus of many works in he lieraure dealing wih Nework on chip archiecures. These works concenrae on differen componens of he inerconnecion neworks such as rouers, NIs, and links. The daa encoding scheme is anoher mehod i is o reduce he link power dissipaion. The daa encoding echniques may be classified ino wo caegories. In he firs caegory, encoding echniques concenrae on lowering he power due o self-swiching aciviy of individual bus 8 P a g e

2 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) lines while ignoring he power dissipaion owing o heir coupling swiching aciviy. In his caegory, we proposed he bus inver (BI) and INC- XOR have daa paerns and graycode are used in encoding echniques. he power consumpion due o he coupling swiching aciviy o become a large fracion of he oal link power consumpion. The works in he second caegory concenrae on reducing power dissipaion hrough he reducion of he coupling swiching [], Among hese schemes [], he swiching aciviy is reduced using many exra conrol lines. firs he daa boh odd and even invered number hen ransmission is rformed using he kind of inversion which reduces more he swiching aciviy. up o 39%. If he number is larger han half of he link widh, he inversion will be rformed o reduce he number of 0 o 1 ransiions when he fli is ransferred via he link. This echnique is only concerned abou he self-swiching wihou worrying he coupling swiching. Ti me , 01 Normal,0 1,,0 0, I, 01 II V, 00,, 00 Odd invered s II,III,and,0 1,,0, 1, 01, 00 III, 01,, V TABLE 1 EFFECT OF ODD INVERSION ON CHANGE OF TRANSITION TYPES The basic idea of he proposed approach is encoding he flis before hey are injeced ino he nework wih is o minimizing he self-swiching aciviy and he coupling swiching aciviy raversed by he flis and self-swiching aciviy and coupling swiching aciviy are responsible for link power dissipaion. In his par, we refer he end-o-end scheme. I akes advanage of he piline naure of he wormhole swiching echnique [4].for he proposed scheme, an encoder and a decoder block are added o he nework inerface. III. OVERVIEW OF THE P ROPOSAL The basic idea of he proposed approach is encoding he flis before hey are injeced ino he nework wih he goal of minimizing he selfswiching aciviy and he coupling swiching aciviy in he links raversed by he flis. In fac, selfswiching aciviy and coupling swiching aciviy are responsible for link power dissipaion. In his par, we refer o he end-o-end scheme. This end-o-end encoding echnique akes advanage of he piline naure of he wormhole swiching echnique [4].Noe ha since he same sequence of flis passes hrough all he links of he rouing pah, he encoding decision aken a he NI may provide he same power saving for all he links.for he proposed scheme, an encoder and a decoder block are added o he NI. Excep for he header fli, he encoder encodes he ougoing flis of he packe such ha he power dissipaed by he iner-rouer poin-o-poin link is minimized.. ROPOSED ENCODING SCHEMES The proposed encoding scheme is o reduce power dissipaion by minimizing he coupling ransiion aciviies and inerconnecion nework. The dynamic power dissipaed by he inerconnecs and drivers is P =[T 0 1 (C S +C l )+T C C C ]V 2 dd F ck (1) where T 0 1 is he number of 0 ransiions in he bus in wo consecuive ransmissions, T c is he number of correlaed swiching beween physically adjacen lines, C s is he line o subsrae capaciance, C l is he load capaciance, C is he coupling capaciance, Vdd is he supply volage, and F ck is he clock frequency. A ransiion occurs when one of he lines swiches when he oher remains unchanged. In a I ransiion, one line swiches from low o high while he oher makes ransiion from high o low. A II ransiion corresponds o he case where boh lines swich simulaneously. Finally, in a V ransiion boh lines does no change. The coupling ransiion aciviy, T c, is a weighed sum of differen ys of coupling ransiion conribuions.therefore T C =K 1 T 1 +K 2 T 2 +K 3 T 3 +K 4 T 4 (2) Using (2), one may express (1) as P =[T 0 1 (C s +C l )+(T 1 +2T 2 )C c ]v 2 ddf ck (3) PαT 0 1 C s +(T 1 +2T 2 )C c (4) we calculae he occurrence probabiliy for differen ys of ransiions. Consider ha fli ( 1) and fli () refer o he previous fli which was ransferred he link in he fli rescively. We consider only wo adjacen bis of he physical channel. Sixeen differen combinaions of hese four bis could occur(table I). he firs bi is he value of he generic ih line of he link, whereas he second bi represens he value of is (i +1)h line. The number of ransiions for s I, II, III, and are 8, 2, 2, 9 P a g e

3 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) and 4, rescively. For a random se of daa, each of hese sixeen ransiions has he same probabiliy. Therefore, he occurrence probabiliy in s I, II, III, and are 1/2, 1/8, 1/8, and 1/4, rescively. A scheme1 In scheme I, we focus on reducing he numbers of ransiions and I by convering in o y1. The scheme compares he curren daa wih he previous one o decide wheher odd inversion or no inversion of he curren daa can lead o he link power reducion. P αt 0 1 +(K 1 T 1 +K 2 T 2 +K 3 T 3 +K 4 T 4 )C C (5) 1) Power Model: If he fli is odd invered dynamic power on he link in he self-ransiion aciviy, and he coupling ransiion before being ransmied, he aciviy of s I, II, III, and, rescively. Table I repors. The firs bi is he value of he generic ih line of he link, whereas he second bi represens he value of is (i + 1)h line. For each pariion, he firs line represens he values a ime 1 (). =T 2 +T 1 -T 1 (9) T y > T x () T y +T x = w-1 () > (w 1) 2 (12) Proposed Encoding Archiecure: The proposed encoding archiecure, which is based on he odd inver condiion defined by is shown in Fig. 1. We consider a link widh of w bis. If no encoding is used. The w 1 bis of he incoming (previous encoded) body fli are indicaed by X i (Y i ), i = 0,1,...,w 2. The wh bi of he previously encoded body fli is indicaed by inv which shows if i was invered (inv = 1) or lef as i was (inv= 0) B. Scheme II In he proposed encoding scheme II, we make use of boh odd and full inversion. The full inversion oraion convers I ransiions o V ransiions. The scheme compares he curren daa wih he previous one o decide wheher he odd, full, or no inversion of he curren daa of power reducion. 1)Power model: The odd inversion leads o power reducion when p < p and p < p. he power p is given by P α T 1 +2T 4 (13) T 2 +T 3 +T 4 +2T 1 <T 1 +2T 4 (14) 2(T 2 -T 4 ) <2T y -w+1 (15) Fig.1.(a) encoder archiecure scheme1 circui diagram Fig.1.(b) encoder archiecure scheme1 inernal view of he encoder block(e) (6) 1 T 4 0 1(odd)+T 1 +2T 2 > 1 T 4 0 0(odd)+T 2 +T 3 +T 4 +2T 1 (7) We can approximae he exac condiion as, T 1 +2T 2 > T 2 +T 3 +T 4 +2T 1 (8) he encoding scheme due o he error induced by he approximaion bu i simplifies he hardware implemenaion of encoder. Based on (12) and (15), he odd inversion condiion is obained as 2(T 2 -T 4 )<2T y -w+1 T y >(w-1)/2 (16) T 2 >T 4 (17) 2(T 2 -T 4 )>2T y -w+1 T 2 >T 4 (18) Proposed Encoding Archiecure: The oraing an encoder implemening he Scheme1in proposed encoding archiecure, which is based on he odd inver condiion of and he full inver condiion of is shown in Fig. 2. Here again, he wh bi of he previously and he full inver condiion of is shown in Fig. 2 In his encoder, in addiion o he T y block in he Scheme I encoder, we have he T 2 and T 4 blocks which deermine if he inversion based on he ransiion ys T 2 and T 4 should be aken place for he link power reducion. The second sage is formed by a se of 1s blocks which coun he number of 1s in heir inpus. P a g e

4 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) C. Scheme III In he proposed encoding Scheme III, we add even inversion o Scheme II. The reason is ha odd inversion convers some of (T 1) ransiions o I ransiions. As can be observed from Table II, if he fli is even invered, he ransiions indicaed as T 1/T 1 in he able are convered o V/II ransiions. Fig.2.encoder archiecure scheme The oupu of hese blocks has he widh of log 2 w. Finally, he boom 1s block scifies he number of ransiions whose full invering of pair bis leads o he increased link power. Based on he number of 1s for each ransiion y, Module A decides if an odd inver or full inver acion should be rformed for he power reducion. Fig.3.(a) decoder archiecure scheme2 circui diagram Fig.3. 1)Power model: similar o he analysis given for scheme1,we approximae he condiion p < p as T 1 +2T 2 >T 2 +T 3 +T 4 +2T 1 (19) Defining Te = T 2 +T 1 -T 1 (20) Ti Normal Even invered me s II,III,and ,0 1,,1 1,00 I, 01 II V, 00,, 01 II,0 1,,0 1, 01,,,00, 00 III 2) Proposed Encoding Archiecure: The oraing principles of his encoder are similar o hose of he encoders implemening Schemes I and II. The proposed encoding archiecure, which is based on he even inver condiion. Fig.3.(b) decoder archiecure scheme2 inernal view of decoder block(d). For his module, if is saisfied, he corresponding oupu signal will become 1. In case no inver acion should be aken place, none of he oupu is se o 1. Module A can be implemened using fulladder and comparaor blocks. The circui diagram of he decoder is shown in Fig. 3. Fig.4 Encoder archiecure scheme III. P a g e

5 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) In Fig.4 he firs sage, we have added he T e blocks which deermine if any of he ransiion ys of T2,T 1, and T 1 is deeced for each pair bis of heir inpus. For hese ransiion ys, he even inver acion yields link power reducion. Again, we have four Ones blocks o deermine he number deeced ransiions for each. The oupu of he Ones blocks are inpus for Module C. Fig. 6. Percenage of decrease s I, II, and coupling swiching aciviy obained wih differen daa encoding. Fig.5. Percenage impac on silicon area and power dissipaion of he nework inerface due o he daa encoding/decoding logic V. RESULTS AND DISCUSSION The proposed daa encoding schemes have been assessed by means of a cycle-accurae NOC simulaor based on Noxim.The power esimaion models of Noxim include NIs, rouers and links. The NOC was clocked a 700 MHz while he baseline NI wih minimum buffering and supporing on core proocol 2 and advanced high-rformance bus proocol dissipaed 5.3mW. The average power dissipaed by he worm hole-based rouer was 5.7 mw. Based on a 65-nm UMC echnology, a oal capaciance of 592 ff/mm was assumed for an inerrouer wire We assumed 2-mm 32-bi links and a packe size of 16 byes (eigh flis). We calculae he coupling capaciance of and nf, and we calculae he power (vdd = 0.9 V and F ck = 700 MHz). The encoder and he decoder were designed in Verilog HDL described a he RTL level, synhesized wih synopsys design compiler and mapd ono an UMC 65-nm echnology library. he proposed encoding scheme I (H), scheme II (HF), and scheme III (OEF) are compared agains SC and SCS [23], he BI coding he coupling driven BI (CDBI) coding and he forbidden paern condiion (FPC) codes. B. Energy Analysis: The proposed daa encoding schemes in reducing he energy consumpion,we consider an 8x8 mesh based nework on chip. We assumed a minimum of wo-fli and maximum eigh-fli packes, deerminisic XY rouing, and inpu FIFO buffers of four flis. Noe ha he coupling Fig. 7. Toal power/energy saving using differen daa encoding schemes. ransiion aciviy reducion is a weighed sum of he s I and II ransiions. To obain he resuls for oal power and energy saving shown in Fig. 7, we have considered all he inerconnec Nework on chip componens including link, rouer, encoder, decoder, and NI. This par of Nework on chip power/energy consumpion consiues an imporan fracion of he overall power/energy budge of he enire sysem. The resuls indicae ha for a given pariioning of he link (4, 8, 16, or 32 bis), excep for BI32 and CDBI32, all of he schemes provide us wih some power savings. Among hem, OEF4 and FPC shows he highes power savings. Fig. 8. Toal power saving using differen daa encoding schemes for several daa sreams. Fig. 9. Toal energy saving using differen daa encoding schemes for several daa sreams. I shows he highes power savings. This shows ha our proposed schemes provide more power reducions when compared wih oher schemes. The power savings obained when differen daa ses including PDF, video, music, ex, and picure are used as he workloads are given in Fig. 8 (Fig. 9)i shows he energy savings for all he daa sreams considered in his par. Also, in he case of OEF4, he saving is he larges among all he encoding schemes. For his encoding scheme, he maximum of 12 P a g e

6 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) energy and power more han 20% and 60%, rescively, was achieved for he picure workload. Higher (lower) aciviies provide more (fewer) opporuniies for he power saving by he proposed encoding schemes. For hese applicaions, he proposed encoding schemes may provide lower power/energy savings. In hese cases, one may apply he coding echnique only o he bis wih higher swiching aciviies as has been rformed for lowpower memory addressing schemes. Fig.. Increase of he compleion ime versus increase of power dissipaion. C. Power Versus Performance The radeoff beween he reducion of he average power dissipaion of he communicaion sysem wih he compleion ime is an imporan characerisic of he sysem. The rcenage increase of compleion ime is defined as he rcenage increase of he ime needed o drain a given amoun of raffic. In Fig., his characerisic for each encoding scheme has been ploed. The poins belonging o he lower (upr) region are characerized by a rcenage of compleion ime increase which is greaer (smaller) han he rcenage of power dissipaion reducion. From his graph, he OEF, HF, and H are he Pareo-opimal encoding schemes. We assume 32-bi links and packes of four flis (fli size is 32 bis). The schemes H, HF, OEF, SC, SCS, and BI require one, wo, four, and eigh addiional bis (inv bis) when he link is divided ino one, wo, four, and eigh pariions, rescively. implemenaion ourforms H, HF, OEF, SC, SCS, and BI implemenaions by 13%. For boh he average delay and he. Fig.. (a) Average delay. (b) Throughpu using differen daa coding. Fig.12.Toal power/energy saving using differen daa encoding schemes. D Mulimedia Sysem on Chip Case Sudy: We analyze he efficacy of he proposed daa encoding schemes on wo complex heerogeneous sysems. The firs one, which is mapd o an 8 8 mesh, consised of a riple video objec plane decoder which has 38 core and mulimedia and wireless communicaion which has 26 cores. We assumed a minimum of wo-fli and maximum eigh-fli packes, deerminisic XY rouing, and inpu FIFO buffers of four flis. The resuls of power and energy saving when differen daa encoding schemes have been presened in Fig.12. For hese resuls, we assumed ha he packe size was eigh flis. Fig. 13. Toal power/energy saving using differen daa encoding schemes. As can be observed from he resuls, he amoun of power and energy reducions are similar o hem resuls presened in Fig. 7. The second heerogeneous sysem consiss of an MPEG-4 decoder, a picure-inpicure, a muli window display, a 263 encoder and mp3 decoder, and a 263 decoder and an mp3 decoder, which have a oal of 58 cores. The sysem is mapd o an 8 8 mesh using he mapping echnique described. As he resuls presened in Fig. 13 show, all of he schemes provide some power savings. Among hem, FPC and OEF4 have he highes power savings. For he oal energy consumpion resul, he highes reducion is % is achieved for OEF4. The amoun of power and energy reducions for almos all he schemes are less han he corresponding resuls presened in Fig.12. This lowers he effeciveness of he daa encoding echniques. VI. CONCLUSION We have presened a se of daa encoding schemes aimed a reducing he power dissipaed by he links of an NOC. In fac, he overall power dissipaed by he communicaion sysem. As compared o he previous encoding schemes 13 P a g e

7 Inernaional Journal of Engineering Research and Applicaions (IJERA) ISSN: Naional Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13 h & 14 h March 2015) proposed in he lieraure, he proposed schemes is o minimize no only he swiching aciviy, bu also he coupling swiching aciviy which is mainly responsible for link power dissipaion in he deep sub micro meer echnology.the proposed encoding schemes are agnosic o NOC archiecure in he sense ha heir applicaion does no require any modificaion neiher in he rouers nor in he links. An exensive evaluaion has been carried ou o assess he impac of he encoder and decoder logic in he Nework Inerface. I impacs he rformance, power, and energy. The applicaion of he proposed encoding schemes allows savings up o 51% of power dissipaion and 14% of energy consumpion wihou any significan rformance degradaion and less han 15% area overhead in he Nework Inerface. ACKNOWLEDEMENT I express my sincere hanks o my guide Mr. Dr. V. Thrimurhulu and Projec Coordinaor Mr. S.ALI ASGAR, M.Tech, Assisan Professor of ECE Dep, and o my HEAD OF DEPARTMENT Dr. V. Thrimurhulu M.E., Ph.D., MIETE., MISTE. Professor & Head of ECE Dep. CREC, TIRUPATHI, for heir valuable guidance and useful suggesions, which held me in he projec work. REFERENCE: [1] Inernaional Technology Roadmap for Semiconducors. (20) [Online].Available: hp:// [2] M. S. Rahaman and M. H. Chowdhury, Crossalk avoidance and errorcorrecion coding for coupled RLC inerconnecs, in Proc. IEEE In Symp. Circuis Sys., May 2009, pp [3] W. Wolf, A. A. Jerraya, and G. Marin, Muliprocessor sysem-on-chipn MPSoC echnology, IEEE Trans. Compu.-Aided Design Inegr. Circuis Sys., vol. 27, no., pp , Oc [4] L. Benini and G. De Micheli, Neworks on chips: A new SoC paradigm, Compuer, vol. 35, no. 1, pp , Jan [5] S. E. Lee and N. Bagherzadeh, A variable frequency link for a power aware neworkon-chip (NoC), Inegr. VLSI J., vol. 42, no. 4,pp , Sep [6] D. Yeh, L. S. Peh, S. Borkar, J. Darringer, A. Agarwal, and W. M. Hwu, Thousandcore chips roundable, IEEE Design Tes Compu., vol. 25, no. 3, pp , May Jun [7] A. Vial and M. Marek-Sadowska, Crossalk reducion for VLSI, IEEE Trans. Compu.-Aided Design Inegr. Circuis Sys., vol. 16, no. 3, pp , Mar [8] M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and V. De, Formal derivaion of opimal acive shielding for low-power on-chip buses, IEEE Trans. Compuer Aided Design Inegr. Circuis Sys., vol. 25, no. 5, pp , May [9] L.Macchiarulo, E. Macii, and M. Poncino, Wire placemen for crossalk energy minimizaion in address buses, in Proc. Design Auom. Tes Eur. Conf. Exhibi., Mar. 2002, pp [] R. Ayoub and A. Orailoglu, A unified ransformaional approach for reducions in faul vulnerabiliy, power, and crossalk noise and delay on processor buses, in Proc. Design Auom. Conf. Asia Souh Pacific, vol.2. Jan. 2005, pp AUTHORS: JEEVA ANUSHA received her B.Tech degree in Elecronics & Communicaion Engineering from SV engineering college for women, irupahi (A.P), India, in he year Currenly pursuing her M.Tech degree in VLSI Sysem Design a Chadalawada Ramanamma Engineering College, Tirupai(A.P), India.. His area of research Includes low power VLSI design. Dr.V.Thrimurhulu M.E., Ph.D., MIETE., MISTE Professor & Head of ECE Dep. He received his Graduaion in Elecronics & Communicaion Engineering AMIETE in 1994 from Insiue of Elecronics & Telecommunicaion Engineering, New Delhi, Pos Graduaion in Engineering M.E scializaion in Microwaves and Radar Engineering in he year Feb, 2003, from Universiy College of Engineering, Osmania Universiy, Hyderabad., and his Docorae in philosophy Ph.D from cenral Universiy, in he year He has done his research work on Ad-Hoc Neworks. 14 P a g e