Efficient Data Encoding and Decoding for Network-On-Chip Application

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1 Inernaional Journal of Curren Engineering and Technology E-ISSN , P-ISSN INPRESSCO, All Righs Reserved Available a hp://inpressco.com/caegory/ijce Research Aricle Efficien Daa Encoding and Decoding for Nework-On-Chip Applicaion Palagani Yellappa, S K. Mahaboob Basha and K. Neelima Deparmen of Elecronics and Communicaion Engineering, Sree Vidyanikehan Engineering College (Auonomous), Tirupahi, India Acceped 10 Aug 2015, Available online 18 Aug 2015, Vol.5, No.4 (Aug 2015) Absrac Nework-on-Chip (NoC) is composed of hree main building blocks links, rouers and nework inerfaces (NIs). In NoC links are he major power dissipaion sources and self-swiching, coupling-swiching aciviies are responsible for link power dissipaion. This paper inroduces se of efficien daa encoding and decoding schemes for reducion of link power dissipaion, delay. Firs self swiching is reduced by checking he swiching ransiion and hen he coupling beween he links is checked and ensured ha he power consumpion is reduced. In his paper, we refer o he endo-end encoding echnique, his echnique akes advanage of he pipeline naure of he wormhole swiching echnique. Especially he decoding schemes are focused on reducing hardware and delay. This paper proposing he concep of on-chip neworks, skeches a daa encoding & decoding inernal views and analyzes he power and delay reducion of boh encoding & decoding schemes in Xilinx Sparan3E family (XC3S500E-5FG320). Keywords: Coupling swiching aciviy, Daa encoding, Daa decoding, NoC, Power reducion and verilog HDL. 1. Inroducion 1 Every echnology has facing some problems like power dissipaion, energy consumpion problems ec. In VLSI echnology in order o esimae and opimize he power consumpion of a digial circui, i is necessary o know how energy is dissipaed. Generally he inerconnecion archiecure is based on dedicaed wires or shared busses. If sysem has a limied number of cores hen dedicaed wire archiecure is effecive, oherwise increases he sysem complexiy. A shared bus is a se of wires which is common o muliple cores, so his approach is more flexible and is oally reusable. Bu i allows only one communicaion ransacion a a ime, all cores share he same communicaion bandwidh in he sysem and is scalabiliy is limied o few dozen IP cores [ITRS online]. Pleny of radiional iner-connec schemes like poin-o-poin, crossbars and buses are available o inerconnec small number of cores. While achieving fas and efficien communicaion wih poin-o-poin communicaion schemes, wire densiy is a barrier for adaping hem o many core archiecures. Moreover, buses are simpler in design, hey suffer from he scalabiliy and arbiraion issues along wih bandwidh boleneck as he number of cores increases [D. Yeh and L. S. Peh e al. 2008]. Similarly he area and *Corresponding auhor Palagani Yellappa is a M.Tech Suden, VLSI; S K. Mahaboob Basha and K. Neelima are working as Assisan Professors power requiremens of a crossbarlimi is applicabiliy. Hence, in many core archiecures like Chip Muliprocessors (CMP) and Muli processor Sysem-on-Chip (MPSoC), emerge he need of an efficien communicaion infrasrucure as radiional soluions fails o handle he communicaion challenges. Nework-on-Chip (NoC) is a scalable and modular design approach, i is a aracive alernaive for he radiional shared buses or dedicaed wires due o many reasons. Firs, NoCs represen a scalable soluion o on-chip communicaion paradigm, because hey provide scalable bandwidh a low power and area overheads. Second, NoCs are very efficien in erms of use of wiring and muliplexing many raffic flows on he same channels providing qualiy of service (QoS) and higher bandwidh. Finally, on-chip neworks wih regular opologies have shor inerconnecs ha can be opimized and reused using regular ieraive blocks, hus making he verificaion process easy. In NoC archiecure nework inerface (NI), swiches and links are he main componens. The nework inerface or nework adaper makes he logical connecion beween he IP core and he nework, since each IP may have a disinc inerface proocol wih respec o he nework. Swiches carry ou he ask of dispaching packes inside he nework, depending on he paricular rouing scheme choosen. The number of pors depends on he opology of he nework. Links are used o ransmi packe beween rouers Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

2 Fig.1 Nework-on-Chip power dissipaion sources (links) The res of his paper is organized as follows. We briefly discuss exising mehods (Bus-Inver and Graycode) in Secion II, while Secion III presens an overview of he proposed daa encoding schemes. The proposed daa encoding and decoding schemes along wih possible hardware implemenaions and heir analysis are described in Secion IV. In Secion V, he resuls for he hardware overhead, power and energy savings and performance reducion of he proposed daa encoding schemes are compared wih hose of oher approaches. Finally, his paper is concluded in Secion VI. 2. Exising Mehods herefore power could be saved by minimizing he number of ransiions occurring on hese bus lines. The major ypes of swiching ransiions are self-swiching and coupling-swiching [A. Sahish e al. 2011]. Selfswiching ransiion is defined as ransiion on he capaciance beween a daa bus line and subsrae (ground). Coupling-swiching ransiion on daa bus is defined as ransiion on capaciance beween adjacen bus lines. Le s consider daa value (piece of informaion) and bus value (acual value on he bus). The Bus-Inver mehod uses one exra conrol bi called inver-bi. In his mehod he peak power dissipaion can be decreased by half by coding as follows [Mircea R e al. 1995]. 1) Compue he Hamming disance beween he presen bus value and he nex daa value. 2) If he Hamming disance is larger han n/2 ( n is number of bis), se inver =1 and make he nex bus value equal o he invered nex daa value. 3) Oherwise le inver = 0 and le he nex bus value equal o he nex daa value. 4) A he receiver side he conens of he bus mus be condiionally invered according o he inver-line, unless he daa is no sored encoded as i is (e.x., in a RAM). In any case he value of inver mus be ransmied over he bus (he mehod increases he number of bus lines from n o n+1 ). The Bus-Inver mehod generaes a code ha has he propery ha he maximum number of ransiions per ime-slo is reduced from n o n/2 and hus he peak power dissipaion is reduced by half. Using he Bus-Inver coding in order o decrease he number of ransiions. The daa encoding echniques may be classified ino wo caegories. In he firs caegory, encoding echniques are concenraes on lowering he power due o self-swiching aciviy of each bus lines. In his caegory Bus-Inver and INC-XOR were proposed for he case of random daa paerns are ransmied via hese lines. Among hese mehods, Bus-Inver encoding is a more popular echnique for reduce dynamic swiching power and he number of ransiions on he bus. In he second caegory Gray-code encoding, working-zone encoding, T0 and T0-XOR were suggesed for he case of correlaed daa paerns. Among hese mehods, Gray-code encoding is widely used echnique for reducing he errors and power dissipaion by he links of an NoC. Applicaion specific approaches (ASP) have also been proposed, bu his caegory is no suiable o be applied in he deep sub-micron meer echnology nodes where he coupling capaciance consiues a major par of he oal iner-connec capaciance. 2.1 Bus-Inver (BI) encoding mehod The Major idea behind Bus-Inver encoding originaed by noing ha more power is wased during daa ransmission in off-chip bus lines. This is due o he he high capaciance lines and high swiching aciviies Fig.2 Bus-Inver encoding 2.2 Gray-Code encoding mehod The power dissipaed by he links of a NoC due o noise increases he risk of errors in he communicaion subsysem. Using he daa encoding wih Gray inpu is mainly reducing he errors and power dissipaion by he links of an NoC. This mehod consiss of a Binary o Gray converer, Encoder, Decoder and Gray o Binary converer and uses he Binary o Gray conversion a he ransmier secion and Gray o Binary conversion a he receiver secion [S. Kaviha e al. 2014]. The Binary o Gray converer is used o conver he binary daa o gray daa. The refleced binary code also known as Gray code. Gray codes are widely used o faciliae error correcion in digial communicaions such as digial erresrial elevision (DTT) and some cable TV sysems Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

3 Fig.3 Binary o Gray code conversion Encoder and Decoder are he basic elemens of any digial communicaion sysem. An Encoder is a device ha convers informaion from one forma o anoher forma, for he purposes of sandardizaion, speed and compressions. A simple Encoder circui can receive a single acive inpu ou of 2n inpu lines generae a binary code on n parallel oupu lines. A Decoder is a device which does he reverse operaion of an Encoder, so ha he original informaion (inpu daa) can be rerieved. A decoder convers binary informaion from n inpu lines o a maximum of 2n unique oupu lines. The Encoder and Decoder are responsible for implemening he olerance agains ransien fauls. Finally Gray o Binary converer is used o conver he gray daa o binary daa. Fig.4 Gray o Binary code conversion 3. Overview of he Proposal Energy consumpion and power dissipaion are oday recognized as he mos imporan design opimizaion objecives. The basic idea of he proposed approach is encoding he flis before hey are injeced ino he nework wih he goal of minimizing he self-swiching and coupling-swiching aciviies. In fac, self-swiching and coupling-swiching aciviies are responsible for link power dissipaion. In his paper we prefer End-o- End echnique, his echnique akes advanage of he pipeline naure of he wormhole swiching echnique [Ioannis Nousias and Tughrul Arslan, 2006] and make he inversion which leads o he higher power saving. Our aim is o cover and I o II and V bi combinaions as far as possible. This is because, II and V combinaions resul in less coupling-swiching and normal-swiching aciviies. 4. Proposed Encoding and Decoding schemes The main goal of he proposed encoding scheme is o reduce he power dissipaion by minimizing he coupling ransiion aciviies on he links of he inerconnecion nework. Coupling ransiions are classified ino four ypes, I, II and V are shown in he below Table 1. Table 1 Effec of odd inversion on change of ransiion ypes Time Normal Odd Invered , T1* T1** T1*** I II V III s II,III and IV IV, I A ransiion occurs when one of he lines swiches when he oher remains unchanged (ex., 00,01 or 00,10 ec.). Fig.5 General Scheme of Proposed Approach In a I ransiion, one line swiches from low o high while he oher makes ransiion from high o low (ex., or ec.). This paper inroduces hree encoding and decoding schemes. In Scheme I, we focus on reducing ransiions and in Scheme II, boh s I and I ransiions are aken ino accoun for deciding beween halfinver and fullinver, which is depending up on he amoun of swiching reducion. Finally, in Scheme III, we consider he fac ha ransiions show differen behaviors in he case of odd and even invers A II ransiion corresponds o he case where boh lines swich simulaneously (ex., or ec.) Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

4 Now, defining [Nima Jafarzadeh e al. 2014] Ty = T 2 + T 1 T 1*** (2) Finally, in a V ransiion boh lines do no change (ex., 00,00 or 10,10 ec.). The effecive swiched capaciance varies from ype o ype (I o IV) and hence, he coupling ransiion aciviy (Tc) is a weighed sum of differen ypes of coupling ransiion conribuions. Therefore [Nima Jafarzadeh e al. 2014] T C=K 1T 1+K 2T 2+K 3T 3+K 4T 4 (1) Where Ti is he average number of i ransiion and Ki is he corresponding weigh. The number of ransiions for s I, II, III and IV are 8, 2, 2 and 4 respecively. For a random se of daa, each of hese sixeen ransiions has he same probabiliy. Therefore, he occurrence probabiliy for s I, II, III and IV are 1/2, 1/8, 1/8 and 1/4 respecively [K. W. Ki and B. Kwang Hyun e al. 2000]. 4.1 Scheme I In scheme 1, our main goal is o reducing he number of and I ransiions. ransiions is convered ino II and V. I ransiions is convered ino ransiions. This scheme compares he wo daa s based on o reducing he link power reducion by doing odd inversion or no inversion operaion. The majoriy voer block, deermines if he below condiion (3) is saisfied Ty > 0.5 (w-1) (3) The general block diagram in Fig 6(a) is same for scheme I, scheme II and scheme III. The w-1 ( w is oal number of bis) bis are given o he encoder block (E) and anoher inpu of he encoder block is he previously encoded oupu. Block E compares hese wo inpus and performing he any one of he inversion based on he ransiion ypes. Comparing he curren daa and previous encoded daa o decide which inversion is performed for link power reducion. Here he Ty block akes wo adjacen bis (eqn. 2) from he given inpus checks wha ype of ransiions occurs, wheher more number of ype I and ype II ransiions is occurring means i se he oupu sae o 1, oherwise i se he oupu o 0. The odd inversion is performed for hese ypes of ransiions. Then he nex block is he Majoriy voer (eqn. 3) i checks he sae, if he number of 1 s is greaer han 0 s or no. The las sage using he XOR circuis, hese circuis is used o perform he inversion on odd bis. The decoding is performed by simply invers he encoder circui when he inver bi is high. 4.2 Scheme II In scheme II, our main goal is o reducing he number of I ransiions, so I ransiions are convered ino V ransiions. This scheme compares he wo daa s based on o reducing he link power reducion by doing full inversion or odd inversion or no inversion operaion. Full and odd inversion based his advanced encoding archiecure consis of w-1 link widh and one bi for inversion bi which indicae if he bi ravel hrough he link is invered or no. W bis link widh is considered when here is no encoding is applied for he inpu bis. Here he Ty block (eqn. 2) from scheme I is added in scheme II. (a) (b) Fig.6 Encoder archiecure scheme I(a) Circui diagram (b) Inernal view of he encoder block (E) Fig.7 Encoder archiecure Scheme II 2827 Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

5 The odd inversion condiion is obained as 2(T 2 -T 4**) < 2Ty-w + 1 Ty > (w-1)/2 (4) The full inversion condiion is obained as 2(T2 - T4**) > 2Ty -w + 1 T2 > T4** (5) The operaing principles of scheme II encoder is similar o Scheme I encoder. The proposed encoding archiecure, which is based on he odd inver condiion of (4) and he full inver condiion of (5), is shown in Fig. 7. Here again, he wh bi of he previously encoded body fli is indicaed wih inv which defines if i was odd or full invered (inv = 1) or lef as i was (inv = 0). In his encoder, in addiion o he Ty block in he Scheme I encoder, we have he T2 and T4** blocks which deermine if he inversion based on he ransiion ypes T2 and T4** should be aken place for he link power reducion. The second sage is formed by a se of 1 s blocks which coun he number of 1 s in heir inpus. The oupu of he op 1 s block deermines he number of ransiions ha odd invering of pair bis leads o he link power reducion. The middle 1 s block idenifies he number of ransiions whose full invering of pair bis leads o he link power reducion. Finally, he boom 1s block specifies he number of ransiions whose full invering of pair bis leads o he increased link power. Based on he number of 1 s for each ransiion ype, Module A decides if an odd or full inver acion should be performed for he power reducion. inpu of he decoder is previous decoded oupu. The decoder block compares he wo inpu daa s and inversion operaion is performed and w-1 bis oupu is produced. The remaining one bi is used o indicae he inversion is performed or no. In decoder circui diagram (Fig. 8) consis of Ty block and Majoriy vecor and XOR circuis. Based on he encoder acion he Ty block is deermined he ransiions. Based on he ransiions ypes he majoriy blocks checks he validiy of he inequaliy given by (eqn. 3). The oupu of he majoriy voer is given o he XOR circui. Half inversion, full inversion and no inversion is performed based on he logic gaes. 4.3 Scheme III Table 2 Effec of even inversion on change of ransiion ypes Time Normal Odd Invered , T1* T1** T1*** I II V II s II,III and IV IV, III (a) In scheme III, we are add he even inversion ino scheme II. Because he odd inversion convers (T 1***) ransiions ino I ransiions. From able II, T1**/T1*** are convered ino V/II ransiions by he flis is even invered. The link power reducion in even inversion is larger han he Odd inversion [Z. Yan and J. Lach e al. 2002]. Defining Te = T 2 + T 1 T 1* (6) The even inversion leads o power reducion [Nima Jafarzadeh e al. 2014] (b) Fig.8 Decoder archiecure Scheme II (a) Circui diagram (b) Inernal view of he decoder block (D) Te>(w 1)/2, Te>Ty, 2(T 2 T 4**)< 2Te w+1 (7) The full inversion leads o power reducion The circui diagram of he decoder is shown in Fig. 8. The w-1 bis are given o decoder circui and anoher 2(T 2 T 4**) > 2Ty w+1, (T 2 > T 4**) 2(T 2 T 4**) > 2Te w+1 (8) 2828 Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

6 2(T 2 T 4**) < 2Ty w+1, Ty > (w 1)/2 Te < Ty (9) 5.1 Power comparison Exising Mehods Table 3 Power dissipaion and delay in Bus-Inver Encoding mehod Table 4 Power dissipaion in Gray-code Encoding mehod Fig.9 Encoder archiecure Scheme III The encoding archiecure (Fig. 9) in scheme III is same of encoder archiecure in scheme I and II. Here we are adding Te block o he scheme II. This is based on even inver, full inver and odd inver condiions. I consiss of w-1 link widh inpu and he w bi is used for he inversion bi. The full, half and even inversion is performed means he inversion bi is se 1, oherwise i se as 0. The Te block is deermined if any of he deeced ransiion of ypes T2, T1** and T1***. For hese ransiion ypes, he even inver acion yields link power reducion. The one s block deermines he number of ones in he corresponding ransmissions of Ty, T2, Te and T4**. This number of one s is given o he Module C block. This block check if odd, even, full or no inver acion corresponding o he oupus 10, 01, 11 or 00 respecively, should be performed. The decoder archiecure of scheme II and scheme III are same is shown in he belo Fig Proposed schemes discussion and comparison A. Scheme I The scheme I main goal is reducing he number of I ransiions and I ransiions. In he encoding logic, each Ty block akes he wo adjacen bis of he inpu flis (X 1X 2Y 1Y 2, X 2X 3Y 2Y 3, ec.). Fig.11 Simulae oupu of Ty block The Majoriy voer checks he sae, if he number of one s is greaer han zeros or no. Fig.10 Decoder inernal view of scheme III 5. Resuls and Discussion The proposed daa encoding and decoding schemes are simulaed and verified using Verilog HDL in Xlinix ISE 10.1i for he arge device xc3s500e-5fg320. Fig. 12 Simulae oupu of Majoriy voer The oupu of he scheme I reducing he number of and I ransiions by using he odd inver condiion. This means ha he odd invering for his pair of bis leads o he reducion of he link power dissipaion Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

7 Module C check if odd, even, full or no inver acion corresponding o he oupus 10 01, 11 or 00 respecively, should be performed. Fig.13 Simulae oupu of Scheme I Encoding (4-bi) Fig.14 Simulae oupu of Scheme I Encoding (18-bi) B. Scheme II In scheme II he ype II ransiion is convered ino V ransiions by using he odd and full inversion condiion. Based on he one s block he Module A akes he decision of which inversion (odd or full) should be performed for he link power reducion. For his module (eqn. 4 & 5) is saisfied, he corresponding oupu is se o 1 oherwise oupu is se o 0 (no inversion is akes place). Fig.18 Simulae oupu of Module C Fig.19 Simulae oupu of Scheme III Encoding and Decoding (18-bi) Power comparison Proposed Mehods: Table 5 Power dissipaion in scheme I Fig.15 Simulae oupu of Module A Table 6 Power dissipaion and delay in scheme II Fig.16 Simulae oupu of Scheme II Encoding and Decoding (18-bi) C. Scheme III Adding he Te block o he scheme II, his is based on even inver and Odd inver condiions. Table 7 Power dissipaion and delay in scheme III Fig.17 Simulae oupu of Te block 2830 Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

8 Fuure Enhacemen 3-bi Coupling Transiions Fig.20 RTL schemaic of 3-bi Coupling ransiion A ransiion occurs when one of he lines swiches when he oher remains unchanged (ex., 000,001 or 000,010 ec.). Fig.21 Simulae oupu of Coupling ransiion In a I ransiion, one line swiches from low o high while he oher makes ransiion from high o low (ex., 001,110 or 010,10 ec.). Fig.22 Simulae oupu of I Coupling ransiion A II ransiion corresponds o he case where hree lines swich simulaneously (ex., 01 or 10 ec.). Fig.23 Simulae oupu of II Coupling ransiion Finally, in a V ransiion hree lines do no change (ex., 000,000 or 110,110 ec.). Fig.24 Simulae oupu of V Coupling ransiion Conclusion In his paper hree encoding and decoding schemes are proposed (namely scheme I, scheme II and scheme III) for reducing coupling and normal swiching aciviies in links of NoC. As he consecuive bis are aken care, no o have opposie values so ha coupling-swiching aciviy is reduced. Similarly, he bis passed hrough paricular links are encoded in such a way ha oggling (opposie previous and presen values) of he bi values in ha paricular links are prevened, o reduce normal swiching aciviy. The main aim of his paper is o cover and II o II and V bi combinaions in he bes possible way, as II and V combinaions resul in less coupling swiching and normal swiching aciviies. From resuls i is clear ha scheme III has even lesser coupling swiching and normal swiching aciviy when compared o scheme II which is achieved by he inclusion of even inversion module e module in he Scheme-III. So ha and I bi combinaions are convered ino II and V bi combinaions. Also Scheme II convers some bi combinaions o I bi combinaions. Hence, Scheme III proves o be more opimized han Scheme II. References Inernaional Technology Roadmap for Semiconducors. (2011) [Online]. Available: hp:// D. Yeh, L. S. Peh, S. Borkar, J. Darringer, A. Agarwal, andw. M. Hwu, (2008), Thousand-core chips roundable, IEEE, vol. 25, A. Sahish, M.Madhavi Laha and K. Lalkishor, (2011), An Efficien Swiching Aciviy Reducion Technique for On- Chip Daa Bus, IJCSI, Vol. 8, Mircea R. San and Wayne P. Burleson, (1995), Bus-Inver Coding for Low-Power I/O, IEEE, Vol. 3, S. Kaviha (2014), Daa Encoding Technique Using Gray Code in Nework-on-Chip, IJST, Vol. 2, S. Anusuyahdevi and Dr.S.Jayashri, (2014), Performance Analysis of an Efficien Low Power NOC Rouer Sysem Using Gray Encoding Techniques, IJIRCCE, Vol. 2, Ioannis Nousias, Tughrul Arslan, (2006), Wormhole Rouing wih Virual Channels using Adapive Rae Conrol for Nework-on-Chip (NoC), NASA/ESA Conference on Adapive Hardware and Sysems. Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh and Ali Afzali-Kusha, (2014), Daa Encoding Techniques for Reducing Energy Consumpion in Nework-on-Chip, IEEE, Vol. 22, K. W. Ki, B. Kwang Hyun, N. Shanbhag, C. L. Liu, and K. M. Sung, (2000), Coupling-driven signal encoding scheme for low-power inerface design, IEEE, Vol. 2, Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino and Vincenzo Caania, (2011), Daa Encoding Schemes in Neworks on Chip, IEEE, Vol. 30, Z. Yan, J. Lach, K. Skadron, and M. R. San, (2002), Odd/even bus inver wih wo-phase ransfer for buses wih coupling, Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)

9 Palagani Yellappa, is currenly pursuing his M.Tech in he specializaion of VLSI in ECE Deparmen of Sree Vidyanikehan Engineering college (Auonomous), Tirupahi. He has compleed B.Tech from Sree Rama Engineering College, Tirupahi. His curren research ineress include nework-on-chips, lowpower inerconnecion and VLSI Signal Processing. Sk. Basha, is currenly working as an Assisan Professor in he ECE Deparmen of Sree VidyanikehanEngineering College (Auonomous), Tirupahi. He has compleed his M.Tech in VLSI Design, in Sayabhama Universiy. His research area of ineres includes Digial Sysem Design and VLSI Signal Processing.. K. Neelima, is currenly working as an Assisan Professor in he ECE Deparmen of Sree VidyanikehanEngineering College (Auonomous), Tirupahi. She has compleed her M.Tech in VLSI Design, in Sayabhama Universiy. Her research area of ineres includes Digial Sysem Design and VLSI Signal Processing Inernaional Journal of Curren Engineering and Technology, Vol.5, No.4 (Aug 2015)