Demodulation Based Testing of Off Chip Driver Performance

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1 Demodulaion Based Tesing of Off Driver Performance Wilfried Daehn Hochschule Magdeburg-Sendahl Fachbereich Elekroechnik Posfach Magdeburg Phone: Fa: Absrac unesed pors This paper presens a new echnique for esing he performance of off chip drivers (s). I is based on he use of periodic signals and a demodulaion based analysis in he frequency domain The echnique is paricular useful for replacing epensive ime domain ess of performance by simpler and less epensive phase shif measuremens in he frequency domain. Such ess can easily be performed by low cos eernal es circuiry or low cos ATE. ATE (off chip es conroller) # #5 #2 #6 #3 #7 #4 #8 Inroducion 27 years afer is invenion BILBO like self es mehods /KMZ79/ have become a sandard approach for esing he core of high performance inegraed circuis like microprocessors / PAG99,/ and high end RAMs /REA99, NHK99, BHA99 CGB99/. The ask of he ATE is reduced o conrolling he operaion of he self es uni and evaluaing he go/nogo signal. Proprieary and sandard es inerfaces /HK9/ connec he on chip self es uni and he off chip ATE by a small number of inerconnec lines. This allows o conrol he simulaneous self es of more han 6 chips using a single eernal eser. A shorcoming of he approach is is inabiliy o es he performance of he I/O-circuiry of a packaged chip. As only one line is used for ransferring he go/nogo informaion o he off chip ATE mos oupu lines of he chip canno be esed wih respec o iming (Fig. ). unesed pors Fig. : Inadequacy of parallel self ess for I/O performance analysis Consequenly wo sep es schemes have come up for high end DRAMs. During he firs sep he chip core is es. This sep is more ore less suppored by onchip self es circuiry. A single eernal chip eser may conrol he simulaneous self es of more han 6 inegraed circuis. The second sep is performed afer packaging of he chips. The emphasis is on esing he iming performance of he. Whereas he iming es of he chip core is a poenial candidae for being handed over o he self es uni he chip I/Os can only be esed by an eernal eser ha has access o he pins of he chip. As all I/O-pins of he are conneced o he ATE, he number of s ha can be esed in parallel by a single eser is significanly from abou 6 o 4 or less. Wih high speed devices like RAMBUS DRAMs he

2 reducion is even larger. Usually only 2 chips are esed in parallel. The reducion of parallelism is due o he limied number (<24) of measuremen channels of he ATE. Whereas several inpu buffers of a chip could be esed using only one signal source of a eser and on chip evaluaion circuiry esing he off chip drivers of an inegraed circui requires separae eser channels for each chip oupu. High Speed ATE # #2 Fig. 2: Reduced paralleliy of I/O-ess due o eser channel limiaions Speed sor ess ha differ 7 MHz devices from 8 MHz devices impose high requiremens on he accuracy of he iming measuremen unis of an eser. In his paper a new low cos echnique for measuring he performance of off chip drivers of an is presened. I is based on using periodic signals and a demodulaion based analysis in he frequency domain. The ne secion oulines he echnique for measuring he ime of a single oupu. The hird secion oulines simplificaions and eensions o es muli oupu circuis. The physical defecs ha cause an increase of he ime will no be analysed here. generaion is done by a simple auomaon ha is driven by an eernal clock signal. The periodic signal is disribued o all off chip drivers. This can be accomplished using a single line from he auomaon o all s or by using a shif regiser ha connecs he s. The las approach will be preferred for chips wih boundary scan. parallel signal disribuion serial signal disribuion Fig. 3: Parallel and serial es signal disribuion Delay Time Measuremen Delay ime measuremen is based on measuring he phase angle beween an on chip generaed periodic signal and an off chip reference signal. On chip signal The simples auomaon for es signal generaion is a oggle flip flop. Figure 4 shows an implemenaion using CMOS comple gaes.

3 /RST CL INV X Xref Fig. 4: Tes I generaes a signal () of alernaing ones and zeros. The period T of () is wice he period of he clock signal. The same kind of circui may be used for generaing a reference signal ref (). () ref idenical o () ecep for a of T/4 or a respecive phase of π/2 (Fig. 5). is They can easily be obained by filering of he original signals. If he digial signal swiches beween and heir ampliudes are A A, ref. (2) π The respecive ground waves are; and ( 2π ) cos π T ( ), e i (3) 2π, sin (4) π T i ref The ime is now deermined by synchronous demodulaion (OPP98), i.e. by muliplicaion and subsequen filering. Figure 6 illusraes he mehod. T 2T 3T T 2T 3T () T 2T 3T Fig. 5: Timing of es signals ref() The phase shifed reference signal ref () can easily be generaed by eiher driving an off chip generaor wih he inverse clock signal or by probing he las sage of he same generaor. A defec produces an oupu signal e () which differs from he epeced signal hrough a ime. e ( ) ( ) () For measuring he only he ground waves ( ) and ( ) of hese signals are used., ref e(),e() w(),ref() ref() z() Fig. 6: Demodulaion based ime measuremen

4 The inermediae signal w() is w( ) (5), e, ref cos π T 2π sin 2 π T ( ) 2π sin π T 4π + sin ( + ) T Afer filering he ampliude of z() gives he ime. z 2 π 2π sin T and for < T 6 (6) 2 z (7) π T The mean value z of z() is direcly proporional o he value of he ime. w( ) π 2π Ai cos T i sin π T 2π ( i ) sin i T Ai ( i + ) + sin i T (9) Afer filering we obain again 2 z A sinϕ i. () π π T This is he same resul as before. Therefor e () need no be filered before demodulaion. An eension for simulaneous characerisaion of several s is skeched in figure 7. () w() z()... Simplificaion and eension o muli oupu circuis I will now be shown ha e () need no be filered before demodulaion. This keeps he hardware requiremens for he measuremen uni low. e () is represened by a Fourier series. e Ai cos T wih A /2, A /π and ϕ w() now evaluaes o i 2 π T. (8) ref() Fig. 7 : Parallel measuremen of imes The on chip es hardware can be reduced if he off chip signal generaor is used o generae boh he es signal and he reference signal. An inpu buffer of he mus be used o supply he simulus o he s (Fig. 8).

5 ref() B () e() w() z(),ref() ref() e() w(),ref() z() Fig. 8: Delay ime measuremen wih an eernal generaion Fig. 9 : Skew measuremen using an on chip generaor The ime measured using a single eernal generaor for he es signal and he reference signal is he combined ime of he inpu buffer and he. If he nominal ime of he inpu buffer is known from simulaion he ime can be compued. If he signal generaor is inegraed on he he reference signal ref () mus be supplied o he off chip measuremen uni via an (Fig. 9). The eernal measuremen uni is used o measure he skew beween he ed es signal and he ed reference signal. Under he assumpion of a single failure boh configuraion of he measuremen uni are able o deec a parameer faul of he failing. Measuremen Errors As he echnique is based on he use of a harmonic reference signal ref ( ) he qualiy of he, deermines he accuracy of he measuremens. The suppresses he higher order harmonics of ref (). We assume a Fourier Series represenaion of he error signal and he reference signal cos ( + e π T ref sin π T ) () (2) Assuming an N h order he filered reference signal ( ) is ref, filered

6 ref π N sin (3) T Wih N>>4 he ampliudes of he higher order harmonics are rapidly decreasing. As a firs approach only he second order harmonics are aken ino accoun. The ampliude of z() becomes 2 z( ) π T + N. Wih N>6 he 2 measuremen error is smaller han one percen. Conclusions Timing ess of inegraed circuis are separaed ino ess of he core and ess of he periphery. The necessiy of esing he periphery wih off chip mehods is oulined. I is shown ha iming ess of off chip drivers (s) can be simplified significanly by he use of periodic es signals. A demodulaion based mehod allows o measure he ime of off chip drivers using low cos hardware insead of epensive high accuracy iming measuremen unis of a universal es sysem. [REA99] J. Rearick, Pracical Scan Tes Generaion and Applicaion for Embedded FIFOs, Proc. ITC99, pp [NHK99] S. Nakahara*, K. Higea, M. Kohno, T. Kawamura, K. Kakiani, Buil-in Self-Tes for GHz Embedded SRAMs Using Fleible Paern and New Repair Algorihm, Proc. ITC99, pp.3-3,999. [BHA99] D. K. Bhavsar, An Algorihm for Row- Column Self-Repair of RAMs and Is Implemenaion in he Alpha 2264, Proc. ITC99, pp.3-38, 999. [CGB99] K. Chakrabory, A. Gupa, M. Bhaacharya, S. Kulkarni, P. Mazumder, A Physical Design Tool for Buil-in Self-Repairable Saic RAMs, DATE99, pp , 999. [HK94] O. F. Haberl and T. Kropf, Self Tesable Boards wih Sandard IEEE 49.5 Module Tes and Mainenance (MTM) Bus Inerface, Proc. EDTC94, 994. [OPP98] A.V. Oppenheim, A.S. Willsky, J.T. Young, s and Sysems, pp. 385, Prenice Hall. References [KMZ79] B. Koenemann, J. Mucha, G. Zwiehoff: Buil-in Logic Block Observaion Techniques, Proc. IEEE In. Tes Conf., Cherry Hill, N. J., 979, pp [PAG99] C. Pyron*, M. Aleander, J. Golab, G. Joos, B. Long, R. Molyneau, R. Raina, N. Tendolkar, 6.2 DFT Advances in he Moorola s MPC74, a PowerPC G4 Microprocessor,Proc. ITC99, pp 37-47, 999.

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