1-/2-/4-Channel Digital Potentiometers AD8400/AD8402/AD8403

Transcription

1 -/2-/4-Channel Digital Potentiometers AD84/AD842/AD843 FEATURES 256-position variable resistance device Replaces, 2, or 4 potentiometers kω, kω, 5 kω, kω Power shutdown less than 5 µa 3-wire,SPI-compatible serial data input MHz update data loading rate 2.7 V to 5.5 V single-supply operation APPLICATIONS Mechanical potentiometer replacement Programmable filters, delays, time constants Volume control, panning Line impedance matching Power supply adjustment GENERAL DESCRIPTION The AD84/AD842/AD843 provide a single-, dual-, or quad-channel, 256-position, digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a mechanical potentiometer or variable resistor. The AD84 contains a single variable resistor in the compact SOIC-8 package. The AD842 contains two independent variable resistors in space-saving SOIC-4 surface-mount packages. The AD843 contains four independent variable resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by the digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of kω, kω, 5 kω, or kω has a ±% channel-to-channel matching tolerance with a nominal temperature coefficient of 5 ppm/ C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs, avoiding any make-before-break or break-before-make operation. (continued on Page 3) V DD DGND R WA (D), R WB (D) (% of Nominal R AB ) SDI CLK CS FUNCTIONAL BLOCK DIAGRAM AD843 DAC SELECT 2 A, A -BIT SERIAL LATCH D R WA 2 CK Q RS SDO Figure. 8-BIT LATCH CK RS 8-BIT LATCH CK RS 8-BIT LATCH CK RS 8-BIT LATCH CK RS CODE (Decimal) RS RDAC SHDN RDAC2 SHDN RDAC3 SHDN RDAC4 SHDN SHDN R WB A W B AGND A2 W2 B2 AGND2 A3 W3 B3 AGND3 A4 W4 B4 AGND Figure 2. RWA and RWB vs. Code The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD84/AD842/AD843 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 4 Electrical Characteristics kω Version... 4 Electrical Characteristics 5 kω and kω Versions... 6 Electrical Characteristics kω Version... 8 Electrical Characteristics All Versions... Timing Diagrams... Absolute Maximum Ratings... ESD Caution... Pin Configurations and Function Descriptions... 2 Typical Performance Characteristics... 4 Test Circuits... 9 Theory of Operation... 2 Programming the Variable Resistor... 2 Programming the Potentiometer Divider... 2 Digital Interfacing... 2 Applications Active Filter Outline Dimensions Ordering Guide Serial Data-Word Format... REVISION HISTORY /5 Rev. C to Rev. D Updated Format... Universal Changes to Features... Changes to Table...4 Changes to Table Changes to Table Changes to Table 5... Added Figure Replaced Figure Changes to Theory of Operation Section...2 Changes to Applications Section...24 Updated Outline Dimensions...26 Changes to Ordering Guide...28 / Rev. B to Rev. C Addition of new Figure... Edits to Specifications...2 Edits to Absolute Maximum Ratings...6 Edits to TPCs, 8, 2, 6, 2, 24, Edits to the Programming the Variable Resistor Section...3 Rev. D Page 2 of 32

3 AD84/AD842/AD843 GENERAL DESCRIPTION (continued from Page ) Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPIcompatible, serial-to-parallel shift register that is loaded from a standard 3-wire, serial-input digital interface. Ten data bits make up the data-word clocked into the serial input register. The data-word is decoded where the first two bits determine the address of the VR latch to be loaded, and the last eight bits are the data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. The AD84 is available in the SOIC-8 surface mount. The AD842 is available in both surface-mount (SOIC-4) and 4-lead PDIP packages, while the AD843 is available in a narrow-body, 24-lead PDIP and a 24-lead, surface-mount package. The AD842/AD843 are also offered in the. mm thin TSSOP-4/TSSOP-24 packages for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of 4 C to +25 C. The reset (RS) pin forces the wiper to midscale by loading 8H into the VR latch. The SHDN pin forces the resistor to an endto-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. Rev. D Page 3 of 32

4 AD84/AD842/AD843 SPECIFICATIONS ELECTRICAL CHARACTERISTICS KΩ VERSION VDD = 3 V ± % or 5 V ± %, VA = VDD, VB = V, 4 C TA +25 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL 2 R-DNL RWB, VA = no connect ±/4 + LSB Resistor Nonlinearity 2 R-INL RWB, VA = no connect 2 ±/2 +2 LSB Nominal Resistance 3 RAB TA = 25 C, model: AD84XYY 8 2 kω Resistance Tempco RAB/ T VAB = VDD, wiper = no connect 5 ppm/ C Wiper Resistance RW VDD = 5V, IW = VDD/RAB 5 Ω RW VDD = 3V, IW = VDD/RAB 2 Ω Nominal Resistance Match R/RAB CH to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25 C.2 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity 4 INL 2 ±/2 +2 LSB Differential Nonlinearity 4 DNL VDD = 5 V ±/4 + LSB DNL VDD = 3 V, TA = 25 C ±/4 + LSB DNL VDD = 3 V, TA = 4 C to +85 C.5 ±/2 +.5 LSB Voltage Divider Tempco VW/ T Code = 8H 5 ppm/ C Full-Scale Error VWFSE Code = FFH LSB Zero-Scale Error VWZSE Code = H.3 2 LSB RESISTOR TERMINALS Voltage Range 5 VA, B, W VDD V Capacitance 6 Ax, Capacitance Bx CA, B f = MHz, measured to GND, code = 8H 75 pf Capacitance 6 Wx CW f = MHz, measured to GND, code = 8H 2 pf Shutdown Current 7 IA_SD VA = VDD, VB = V, SHDN =. 5 µa Shutdown Wiper Resistance RW_SD VA = VDD, VB = V, SHDN =, VDD = 5 V 2 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V.8 V Input Logic High VIH VDD = 3 V 2. V Input Logic Low VIL VDD = 3 V.6 V Output Logic High VOH RL = 2.2 kω to VDD VDD. V Output Logic Low VOL IOL =.6 ma, VDD = 5 V.4 V Input Current IIL VIN = V or 5 V, VDD = 5 V ± µa Input Capacitance 6 CIL 5 pf POWER SUPPLIES Power Supply Range VDD range V Supply Current (CMOS) IDD VIH = VDD or VIL = V. 5 µa Supply Current (TTL) 8 IDD VIH = 2.4 V or.8 V, VDD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = V, VDD = 5.5 V 27.5 µw Power Supply Sensitivity PSS VDD = 5 V ± %.2. %/% PSS VDD = 3 V ± %.6.3 %/% Rev. D Page 4 of 32

5 AD84/AD842/AD843 Parameter Symbol Conditions Min Typ Max Unit 6, DYNAMIC CHARACTERISTICS Bandwidth 3 db BW_ K R = kω 6 khz Total Harmonic Distortion THDW VA = V rms + 2 V dc, VB = 2 V dc, f = khz.3 % VW Settling Time ts VA = VDD, VB = V, ±% error band 2 µs Resistor Noise Voltage enwb RWB = 5 kω, f = khz, RS = 9 nv/ Hz Crosstalk CT VA = VDD, VB = V 65 db Typical represents average readings at 25 C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = 5 µa for VDD = 3 V and IW = 4 µa for VDD = 5 V for the kω versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = V. DNL specification limits of ± LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I DD vs. logic voltage. 9 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. Rev. D Page 5 of 32

6 AD84/AD842/AD843 ELECTRICAL CHARACTERISTICS 5 KΩ AND KΩ VERSIONS VDD = 3 V ± % or 5 V ± %, VA = VDD, VB = V, 4 C TA +25 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL 2 R-DNL RWB, VA = No Connect ±/4 + LSB Resistor Nonlinearity 2 R-INL RWB, VA = No Connect 2 ±/2 +2 LSB Nominal Resistance 3 RAB TA = 25 C, Model: AD84XYY kω RAB TA = 25 C, Model: AD84XYY 7 3 kω Resistance Tempco RAB/ T VAB = VDD, Wiper = No Connect 5 ppm/ C Wiper Resistance RW VDD = 5V, IW = VDD/RAB 5 Ω RW VDD = 3V, IW = VDD/RAB 2 Ω Nominal Resistance Match R/RAB CH to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25 C.2 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity 4 INL 4 ± +4 LSB Differential Nonlinearity 4 DNL VDD = 5 V ±/4 + LSB DNL VDD = 3 V, TA = 25 C ±/4 + LSB DNL VDD = 3 V, TA = 4 C to +85 C.5 ±/2 +.5 LSB Voltage Divider Tempco VW/ T Code = 8H 5 ppm/ C Full-Scale Error VWFSE Code = FFH.25 LSB Zero-Scale Error VWZSE Code = H +. + LSB RESISTOR TERMINALS Voltage Range 5 VA, VB, VW VDD V Capacitance 6 Ax, Bx CA, CB f = MHz, measured to GND, code = 8H 5 pf Capacitance 6 Wx CW f = MHz, measured to GND, code = 8H 8 pf Shutdown Current 7 IA_SD VA = VDD, VB = V, SHDN =. 5 µa Shutdown Wiper Resistance RW_SD VA = VDD, VB = V, SHDN =, VDD = 5 V 2 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V.8 V Input Logic High VIH VDD = 3 V 2. V Input Logic Low VIL VDD = 3 V.6 V Output Logic High VOH RL = 2.2 kω to VDD VDD. V Output Logic Low VOL IOL =.6 ma, VDD = 5 V.4 V Input Current IIL VIN = V or 5 V, VDD = 5 V ± µa Input Capacitance 6 CIL 5 pf POWER SUPPLIES Power Supply Range VDD range V Supply Current (CMOS) IDD VIH = VDD or VIL = V. 5 µa Supply Current (TTL) 8 IDD VIH = 2.4 V or.8 V, VDD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = V, VDD = 5.5 V 27.5 µw Power Supply Sensitivity PSS VDD = 5 V ± %.2. %/% PSS VDD = 3 V ± %.6.3 %/% Rev. D Page 6 of 32

7 AD84/AD842/AD843 Parameter Symbol Conditions Min Typ Max Unit 6, DYNAMIC CHARACTERISTICS Bandwidth 3 db BW_5 K R = 5 kω 25 khz BW_ K R = kω 7 khz Total Harmonic Distortion THDW VA = V rms + 2 V dc, VB = 2 V dc, f = khz.3 % VW Settling Time ts_5 K VA = VDD, VB = V, ±% error band 9 µs ts_ K VA = VDD, VB = V, ±% error band 8 µs Resistor Noise Voltage enwb_5 K RWB = 25 kω, f = khz, RS = 2 nv/ Hz enwb_ K RWB = 5 kω, f = khz, RS = 29 nv/ Hz Crosstalk CT VA = VDD, VB = V 65 db Typicals represent average readings at 25 C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = VDD/R for VDD = 3 V or 5 V for the 5 kω and kω versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = V. DNL specification limits of ± LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of I DD vs. logic voltage. 9 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. Rev. D Page 7 of 32

8 AD84/AD842/AD843 ELECTRICAL CHARACTERISTICS KΩ VERSION VDD = 3 V ± % or 5 V ± %, VA = VDD, VB = V, 4 C TA +25 C, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL 2 R-DNL RWB, VA = no connect 5 +3 LSB Resistor Nonlinearity 2 R-INL RWB, VA = no connect 4 ±.5 +4 LSB Nominal Resistance 3 RAB TA = 25 C, model: AD84XYY kω Resistance Tempco RAB/ T VAB = VDD, wiper = no connect 7 ppm/ C Wiper Resistance RW VDD = 5V, IW = VDD/RAB 53 Ω RW VDD = 3V, IW = VDD/RAB 2 Ω Nominal Resistance Match R/RAB CH to CH 2, VAB = VDD, TA = 25 C.75 2 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity 4 INL 6 ±2 +6 LSB Differential Nonlinearity 4 DNL VDD = 5 V LSB DNL VDD = 3 V, TA = 25 C LSB Voltage Divider Temperature Coefficient VW/ T Code = 8H 25 ppm/ C Full-Scale Error VWFSE Code = FFH 2 2 LSB Zero-Scale Error VWZSE Code = H 6 LSB RESISTOR TERMINALS Voltage Range 5 VA, VB, VW VDD V Capacitance 6 Ax, Bx CA, CB f = MHz, measured to GND, code = 8H 75 pf Capacitance 6 Wx CW f = MHz, measured to GND, code = 8H 2 pf Shutdown Supply Current 7 IA_SD VA = VDD, VB = V, SHDN =. 5 µa Shutdown Wiper Resistance RW_SD VA = VDD, VB = V, SHDN =, VDD = 5 V 5 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V.8 V Input Logic High VIH VDD = 3 V 2. V Input Logic Low VIL VDD = 3 V.6 V Output Logic High VOH RL = 2.2 kω to VDD VDD. V Output Logic Low VOL IOL =.6 ma, VDD = 5 V.4 V Input Current IIL VIN = V or 5 V, VDD = 5 V ± µa Input Capacitance 6 CIL 5 pf POWER SUPPLIES Power Supply Range VDD range V Supply Current (CMOS) IDD VIH = VDD or VIL = V. 5 µa Supply Current (TTL) 8 IDD VIH = 2.4 V or.8 V, VDD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = V, VDD = 5.5 V 27.5 µw Power Supply Sensitivity PSS VDD = 5 V ± %.35.8 %/% PSS VDD = 3 V ± %.5.3 %/% Rev. D Page 8 of 32

9 AD84/AD842/AD843 Parameter Symbol Conditions Min Typ Max Unit 6, DYNAMIC CHARACTERISTICS Bandwidth 3 db BW_ K R = kω 5, khz Total Harmonic Distortion THDW VA = V rms + 2 V dc, VB = 2 V dc, f = khz.5 % VW Settling Time ts VA = VDD, VB = V, ±% error band.5 µs Resistor Noise Voltage enwb RWB = 5 Ω, f = khz, RS = 3 nv/ Hz Crosstalk CT VA = VDD, VB = V 65 db Typicals represent average readings at 25 C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 5 µa for VDD = 3 V and IW = 2.5 ma for VDD = 5 V for kω version. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = V. DNL specification limits of ± LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I 9 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. DD vs. logic voltage. Rev. D Page 9 of 32

10 AD84/AD842/AD843 ELECTRICAL CHARACTERISTICS ALL VERSIONS VDD = 3 V ± % or 5 V ± %, VA = VDD, VB = V, 4 C TA +25 C, unless otherwise noted. Table 4. Parameter Symbol Conditions Min Typ Max Unit SWITCHING CHARACTERISTICS 2, 3 Input Clock Pulse Width tch, tcl Clock level high or low ns Data Setup Time tds 5 ns Data Hold Time tdh 5 ns CLK to SDO Propagation Delay 4 tpd RL = kω to 5 V, CL 2 pf 25 ns CS Setup Time tcss ns CS High Pulse Width tcsw ns Reset Pulse Width trs 5 ns CLK Fall to CS Rise Hold Time tcsh ns CS Rise to Clock Rise Setup tcs ns Typicals represent average readings at 25 C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tr = tf = ns (% to 9% of VDD) and timed from a voltage level of.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of V/µs should be maintained. 4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section). TIMING DIAGRAMS SDI A A D7 D6 D5 D4 D3 D2 D D CLK CS V DD V OUT V DAC REGISTER LOAD 92-3 RS V DD V OUT V DD /2 t RS t S ±% ERROR BAND ±% 92-5 Figure 3. Timing Diagram Figure 5. Reset Timing Diagram SDI (DATA IN) SDO (DATA OUT) Ax OR Dx A'x OR D'x Ax OR Dx t DS t DH A'x OR D'x t PD_MIN t PD_MAX CLK CS t CSS t CH t CL t CSH tcs t CSW t S V DD V OUT V ±% ERROR BAND ±% 92-4 Figure 4. Detailed Timing Diagram Rev. D Page of 32

11 AD84/AD842/AD843 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. ±5 ma/±5 μa/ Table 5. Parameter Rating VDD to GND.3 V, +8 V VA, VB, VW to GND V, VDD Maximum Current IWB, IWA Pulsed ±2 ma IWB Continuous (RWB kω, A Open) ±5 ma IWA Continuous (RWA kω, B Open) ±5 ma IAB Continuous (RAB = kω/ kω/ 5 kω/ kω) ± μa/±5 μa Digital Input and Output Voltage V, 7 V to GND Operating Temperature Range 4 C to +25 C Maximum Junction Temperature 5 C (TJ Maximum) Storage Temperature 65 C to +5 C Lead Temperature (Soldering, sec) 3 C Package Power Dissipation (TJ max TA)/θJA Thermal Resistance (θja) SOIC (R-8) 58 C/W PDIP (N-4) 83 C/W PDIP (N-24) 63 C/W SOIC (R-4) 2 C/W SOIC (R-24) 7 C/W TSSOP-4 (RU-4) 8 C/W TSSOP-24 (RU-24) 43 C/W Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package; VDD = 5 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SERIAL DATA-WORD FORMAT Table 6. ADDR DATA B9 B8 B7 B6 B5 B4 B3 B2 B B A A D7 D6 D5 D4 D3 D2 D D MSB LSB MSB LSB ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D Page of 32

12 AD84/AD842/AD843 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS B GND 2 CS 3 SDI 4 AD84 TOP VIEW (Not to Scale) A W V DD CLK Figure 6. AD84 Pin Configuration 92-6 AGND 4 B2 A2 W2 DGND SHDN CS AD842 TOP VIEW (Not to Scale) B A W V DD RS CLK SDI 92-7 AGND2 B2 2 A2 3 W2 4 AGND4 5 B4 6 A4 7 AD843 TOP VIEW (Not to Scale) B A W AGND B3 A3 W3 W4 8 7 AGND3 Figure 7. AD842 Pin Configuration DGND 9 6 V DD SHDN 5 RS CS 4 CLK SDI 2 3 SDO Figure 8. AD843 Pin Configuration 92-8 Table 7. AD84 Pin Function Descriptions Pin No. Mnemonic Description B Terminal B RDAC. 2 GND Ground. 3 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 4 SDI Serial Data Input. 5 CLK Serial Clock Input, Positive Edge Triggered. 6 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V. 7 W Wiper RDAC, Addr = 2. 8 A Terminal A RDAC. Table 8. AD842 Pin Function Descriptions Pin No. Mnemonic Description AGND Analog Ground. 2 B2 Terminal B RDAC 2. 3 A2 Terminal A RDAC 2. 4 W2 Wiper RDAC 2, Addr = 2. 5 DGND Digital Ground. 6 SHDN Terminal A Open Circuit. Shutdown controls Variable Resistor and Variable Resistor 2. 7 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 8 SDI Serial Data Input. 9 CLK Serial Clock Input, Positive Edge Triggered. RS Active Low Reset to Midscale. Sets RDAC registers to 8H. VDD Positive Power Supply. Specified for operation at both 3 V and 5 V 2 W Wiper RDAC, Addr = 2. 3 A Terminal A RDAC. 4 B Terminal B RDAC. All AGND pins must be connected to DGND. Rev. D Page 2 of 32

13 AD84/AD842/AD843 Table 9. AD843 Pin Function Descriptions Pin No. Mnemonic Description AGND2 Analog Ground 2. 2 B2 Terminal B RDAC 2. 3 A2 Terminal A RDAC 2. 4 W2 Wiper RDAC 2, Addr = 2. 5 AGND4 Analog Ground 4. 6 B4 Terminal B RDAC 4. 7 A4 Terminal A RDAC 4. 8 W4 Wiper RDAC 4, Addr = 2. 9 DGND Digital Ground. SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor through Variable Resistor 4. CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 2 SDI Serial Data Input. 3 SDO Serial Data Output. Open drain transistor requires a pull-up resistor. 4 CLK Serial Clock Input, Positive Edge Triggered. 5 RS Active Low Reset to Midscale. Sets RDAC registers to 8H. 6 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V. 7 AGND3 Analog Ground 3. 8 W3 Wiper RDAC 3, Addr = 2. 9 A3 Terminal A RDAC 3. 2 B3 Terminal B RDAC 3. 2 AGND Analog Ground. 22 W Wiper RDAC, Addr = A Terminal A RDAC. 24 B Terminal B RDAC. All AGND pins must be connected to DGND. Rev. D Page 3 of 32

14 AD84/AD842/AD843 TYPICAL PERFORMANCE CHARACTERISTICS 8 V DD =3V OR5V R AB = kω 6 48 SS = 25 UNITS V DD =4.5V T A =25 C RESISTANCE (kω) 6 4 FREQUENCY R WB R WA CODE (Decimal) Figure 9. Wiper to End Terminal Resistance vs. Code WIPER RESISTANCE (Ω) Figure 2. kω Wiper-Contact-Resistance Histogram H FF H. V DD =5V V WB VOLTAGE (V) H 2 H 5 H CODE = H T A =25 C V DD =5V INL NONLINEARITY ERROR (LSB).5.5 T A =+25 C T A = 4 C T A =+85 C I WB CURRENT (ma) DIGITAL INPUT CODE (Decimal) 92-3 Figure. Resistance Linearity vs. Conduction Current Figure 3. Potentiometer Divider Nonlinearity Error vs. Code R-INL ERROR (LSB)..5 T A = 4 C T A =+85 C T A =+25 C V DD =5V FREQUENCY SS = 84 UNITS V DD =4.5V T A =25 C DIGITAL INPUT CODE (Decimal) WIPER RESISTANCE (Ω) 92-4 Figure. Resistance Step Position Nonlinearity Error vs. Code Figure 4. 5 kω Wiper-Contact-Resistance Histogram Rev. D Page 4 of 32

15 AD84/AD842/AD843 FREQUENCY SS = 84 UNITS V DD =4.5V T A =25 C RHEOSTAT MODE TEMPCO (ppm/ C) V DD =5V T A = 4 C/+85 C V A = NO CONNECT R WB MEASURED WIPER RESISTANCE (Ω) CODE (Decimal) Figure 5. kω Wiper-Contact-Resistance Histogram Figure 8. RWB/ T Rheostat Mode Tempco R AB (END-TO-END) 2mV NOMINAL RESISTANCE (kω) R WB (WIPER-TO-END) CODE = 8 H R W (2mV/DIV) CS (5V/DIV) R AB =kω TEMPERATURE ( C) Figure 6. Nominal Resistance vs. Temperature V 5ns TIME 5ns/DIV Figure 9. One Position Step Change at Half-Scale (Code 7FH to 8H) 92-9 POTENTIOMETER MODE TEMPCO (ppm/ C) V DD =5V T A = 4 C/+85 C V A =2V V B =V GAIN (db) T A =25 C CODE = FF CODE (Decimal) Figure 7. VWB/ T Potentiometer Mode Tempco k k k M FREQUENCY (Hz) Figure 2. kω Gain vs. Frequency vs. Code (See Figure 43) 92-2 Rev. D Page 5 of 32

16 AD84/AD842/AD CODE = 8 H V DD =5V SS = 58 UNITS FILTER = 22kHz V DD =5V T A =25 C R WB RESISTANCE (%) AVERAGE + 2 SIGMA AVERAGE 2 SIGMA AVERAGE THD + NOISE (%) HOURS OF OPERATION AT 5 C Figure 2. Long-Term Drift Accelerated by Burn-In k k k FREQUENCY (Hz) Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency (See Figure 4 and Figure 42) V 45.25µs OUTPUT V OUT (5mV/DIV) INPUT 5V TIME 5µs/DIV 5µs mV TIME 2ns/DIV 2ns Figure 22. Large Signal Settling Time Figure 25. Digital Feedthrough vs. Time H CODE = FF H H 4 H CODE = FF H GAIN (db) H 2 H H GAIN (db) H H 8 H H 4 H H 2 H 2 H 48 H 54 k k k M FREQUENCY (Hz) H k k k M FREQUENCY (Hz) Figure kω Gain vs. Frequency vs. Code Figure 26. kω Gain vs. Frequency vs. Code Rev. D Page 6 of 32

17 AD84/AD842/AD843 X NORMALIZED GAIN FLATNESS (.db/div) CODE = 8 H V DD =5V T A =25 C R=5kΩ R = kω k k k M FREQUENCY (Hz) R=kΩ GAIN (db) f 3dB = 7kHz, R = kω FREQUENCY (Hz) f 3dB = 7kHz, R = kω f 3dB = 25kHz, R = 5kΩ V IN = mv rms 36 V DD =5V R L =MΩ 42 k k k M 92-3 Figure 27. Normalized Gain Flatness vs. Frequency (See Figure 43) Figure 3. 3 db Bandwidths I DD SUPPLY CURRENT (ma). T A =25 C V DD =5V I DD SUPPLY CURRENT (µa) A: V DD =5.5V CODE = 55 H B: V DD =3.3V CODE = 55 H C: V DD =5.5V CODE = FF H D: V DD =3.3V CODE = FF H A T A =25 C B V DD =3V 2 C DIGITAL INPUT VOLTAGE (V) Figure 28. Supply Current vs. Digital Input Voltage k k k M M FREQUENCY (Hz) Figure 3. Supply Current vs. Clock Frequency D V DD =+5VDC±V p-p AC T A =25 C CODE = 8 H C L = pf V A =4V,V B =V V DD =2.7V T A =25 C PSRR (db) 4 R ON (Ω) 8 6 V DD =5.5V k k k M FREQUENCY (Hz) Figure 29. Power Supply Rejection Ratio vs. Frequency (See Figure 4) V BIAS (V) Figure 32. AD843 Incremental Wiper On Resistance vs. VDD (See Figure 39) Rev. D Page 7 of 32

18 AD84/AD842/AD843 GAIN (db) PHASE (Degrees) V DD =5V T A =25 C I DD SUPPLY CURRENT (µa).. LOGIC INPUT VOLTAGE =, V DD V DD =5.5V k WIPER SET AT HALF-SCALE 8 H 2k 4k M 2M 4M 6M M FREQUENCY (Hz) Figure 33. kω Gain and Phase vs. Frequency TEMPERATURE ( C) V DD =3.3V Figure 35. Supply Current vs. Temperature V DD =5V 6 5 R AB = kω I A SHUTDOWN CURRENT (na) THEORETICAL I WB_MAX (ma) R AB = kω R AB = 5kΩ V A = V B = OPEN T A =25 C TEMPERATURE ( C) R AB = kω CODE (Decimal) Figure 34. Shutdown Current vs. Temperature Figure 36. IWB_MAX vs. Code Rev. D Page 8 of 32

19 AD84/AD842/AD843 TEST CIRCUITS A DUT B V+ DUT A W B V+ = V DD LSB = V+/256 V MS OFFSET GND ~ W V IN 2.5V DC OP279 5V V OUT 92-4 Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 4. Inverting Programmable Gain NO CONNECT 5V DUT A W I W V IN ~ W OP279 V OUT B V MS OFFSET GND A B DUT 2.5V 92-4 Figure 38. Resistor Position Nonlinearity Error (Rheostat Operations; R-INL, R-DNL) Figure 42. Noninverting Programmable Gain DUT A +5V V MS2 A B W I V W =V DD /R NOMINAL W V MS R W =[V MS V MS2 ]/I W OFFSET GND V IN ~ W DUT B 2.5V OP42 5V V OUT Figure 39. Wiper Resistance Figure 43. Gain vs. Frequency V+ ~ V A V DD A V+ = VDD ± % W B V MS PSRR (db) = 2LOG PSS (%/%) = V MS % V DD % V MS ( ) V DD DUT B W I SW R SW =.V I SW CODE = V BIAS H +.V A=NC Figure 4. Power Supply Sensitivity (PSS, PSRR) Figure 44. Incremental On Resistance Rev. D Page 9 of 32

20 AD84/AD842/AD843 THEORY OF OPERATION The AD84/AD842/AD843 provide a single, dual, and quad channel, 256-position, digitally controlled variable resistor (VR) device. Changing the programmed VR setting is accomplished by clocking in a -bit serial data-word into the SDI (Serial Data Input) pin. The format of this data-word is two address bits, MSB first, followed by eight data bits, also MSB first. Table 6 provides the serial register data-word format. The AD84/AD842/AD843 have the following address assignments for the ADDR decoder, which determines the location of the VR latch receiving the serial register data in Bit B7 to Bit B: VR# = A 2 + A + () The single-channel AD84 requires A = A =. The dualchannel AD842 requires A =. VR settings can be changed one at a time in random sequence. A serial clock running at MHz makes it possible to load all four VRs under 4 µs ( 4 ns) for AD843. The exact timing requirements are shown in Figure 3, Figure 4, and Figure 5. The AD84/AD842/AD843 do not have power-on midscale preset, so the wiper can be at any random position at power-up. However, the AD842/AD843 can be reset to midscale by asserting the RS pin, simplifying initial conditions at power-up. Both parts have a power shutdown SHDN pin that places the VR in a zero-power-consumption state where Terminal Ax is open-circuited and the Wiper Wx is connected to Terminal Bx, resulting in the consumption of only the leakage current in the VR. In shutdown mode, the VR latch settings are maintained so that upon returning to the operational mode, the VR settings return to the previous resistance values. The digital interface is still active in shutdown, except that SDO is deactivated. Code changes in the registers can be made during shutdown that will produce new wiper positions when the device is taken out of shutdown. SHDN D7 D6 D5 D4 D3 D2 D D R S R S R S Ax Wx PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the VR (RDAC) between Terminal A and Terminal B is available with values of kω, kω, 5 kω, and kω. The final digits of the part number determine the nominal resistance value; that is, kω = ; kω =. The nominal resistance (RAB) of the VR has 256 contact points accessible by the wiper terminal, and the resulting resistance can be measured either across the wiper and B terminals (RWB) or across the wiper and A terminals (RWA). The 8-bit data-word loaded into the RDAC latch is decoded to select one of the 256 possible settings. The wiper s first connection starts at the B terminal for data H. This B terminal connection has a wiper contact resistance of 5 Ω. The second connection (for the kω part) is the first tap point located at 89 Ω = [RAB (nominal resistance) + RW = 39 Ω + 5 Ω] for data H. The third connection is the next tap point representing 78 Ω + 5 Ω = 28 Ω for data 2H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at, Ω. Note that the wiper does not directly connect to the B terminal even for data H. See Figure 45 for a simplified diagram of the equivalent RDAC circuit. The AD84 contains one RDAC, the AD842 contains two independent RDACs, and the AD843 contains four independent RDACs. The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is D R = + (2) 256 WB ( D ) R AB RW where D, in decimal, is the data loaded into the 8-bit RDAC# latch, and RAB is the nominal end-to-end resistance. For example, when the A terminal is either open-circuited or tied to the Wiper W, the following RDAC latch codes result in the following RWB (for the kω version): Table. D (Dec) RWB (Ω) Output State 255, Full scale 28 5,5 Midscale (RS = condition) 89 LSB 5 Zero-scale (wiper contact resistance) RDAC LATCH AND DECODER R S R S =R NOMINAL /256 Bx Note that in the zero-scale condition, a finite wiper resistance of 5 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact. Figure 45. AD842/AD843 Equivalent VR (RDAC) Circuit Rev. D Page 2 of 32

21 AD84/AD842/AD843 Like a mechanical potentiometer, RDAC is symmetrical. The resistance between the Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be tied to the wiper or left floating. RWA starts at the maximum and decreases as the data loaded into the RDAC latch increases. The general transfer equation for this RWA is 256 D R WA( D) = RAB + R (3) W 256 where D is the data loaded into the 8-bit RDAC# latch, and RAB is the nominal end-to-end resistance. For example, when the B terminal is either open-circuited or tied to the Wiper W, the following RDAC latch codes result in the following RWA (for the kω version): Table. D (Dec) RWA (Ω) Output State Full-Scale 28 5,5 Midscale (RS = Condition), LSB,5 Zero-Scale The typical distribution of RAB from channel to channel matches within ±%. However, device-to-device matching is process lot dependent and has a ±2% variation. The temperature coefficient, or the change in RAB with temperature, is 5 ppm/ C. The wiper-to-end-terminal resistance temperature coefficient has the best performance over the % to % of adjustment range where the internal wiper contact switches do not contribute any significant temperature related errors. The graph in Figure 8 shows the performance of RWB tempco vs. code. Using the potentiometer with codes below 32 results in the larger temperature coefficients plotted. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper starting at V up to LSB less than 5 V. Each LSB is equal to the voltage applied across the A to B terminals divided by the 256-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to the A to B terminals is Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 5 ppm/ C. At the lower wiper position settings, the potentiometer divider temperature coefficient increases because the contribution of the CMOS switch wiper resistance becomes an appreciable portion of the total resistance from the B terminal to the Wiper W. See Figure 7 for a plot of potentiometer tempco performance vs. code setting. DIGITAL INTERFACING The AD84/AD842/AD843 contain a standard SPIcompatible, 3-wire, serial input control interface. The three inputs are clock (CLK), chip select (CS), and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. For the best result, use logic transitions faster than V/µs. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. The block diagrams in Figure 46, Figure 47, and Figure 48 show the internal digital circuitry in more detail. When CS is taken active low, the clock loads data into the -bit serial register on each positive clock edge (see Table 2). CS CLK SDI DI D 8 CS CLK SDI A A D7 -BIT SER REG DI EN ADDR DEC D7 D RDAC LATCH NO. AD84 GND Figure 46. AD84 Block Diagram A A D7 -BIT SER REG D 8 EN ADDR DEC D7 D D7 D RDAC LATCH NO. R RDAC LATCH NO. 2 R AD842 V DD A W B V DD A W B A4 W4 B D V = V + V (4) 256 W AB B SHDN DGND RS AGND Operation of the digital potentiometer in the voltage divider mode results in more accurate operation over temperature. Figure 47. AD842 Block Diagram Rev. D Page 2 of 32

22 AD84/AD842/AD843 CS CLK SDO DO A A D7 EN ADDR DEC D7 D RDAC LATCH NO. R V DD A W B If two AD843 RDACs are daisy-chained, it requires 2 bits of address and data in the format shown in Table 6. During shutdown (SHDN = logic low), the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. See Figure 5 for equivalent SDO output circuit schematic. SDI SHDN DI SER REG DGND D 8 RS D7 D AD843 RDAC LATCH NO. 4 R AGND Figure 48. AD843 Block Diagram Table 2. Input Logic Control Truth Table CLK CS RS SHDN Register Activity L L H H No SR effect; enables SDO pin P L H H Shift one bit in from the SDI pin. The th previously entered bit is shifted out of the SDO pin. X P H H Load SR data into RDAC latch based on A, A decode (Table 3). X H H H No operation X X L H Sets all RDAC latches to midscale, wiper centered, and SDO latch cleared X H P H Latches all RDAC latches to 8H X H H L Open-circuits all Resistor A terminals, connects W to B, turns off SDO output transistor. P = positive edge, X = don t care, SR = shift register The serial data output (SDO) pin, which exists only on the AD843 and not on the AD84 or AD842, contains an open-drain, n-channel FET that requires a pull-up resistor to transfer data to the SDI pin of the next package. The pull-up resistor termination voltage may be larger than the VDD supply (but less than the max VDD of 8 V) of the AD843 SDO output device. For example, the AD843 could operate at VDD = 3.3 V, and the pull-up for interface to the next device could be set at 5 V. This allows for daisy-chaining several RDACs from a single processor serial data line. The clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy-chain node SDO to SDI between devices must be accounted for in order to transfer data successfully. When daisy chain is used, CS should be kept low until all the bits of every package are clocked into their respective serial registers and the address and data bits are in the proper decoding location. A4 W4 B The data setup and hold times in the specification table determine the data valid time requirements. The last bits of the data-word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder, which enables one of the two (AD842) or four (AD843) positive edge-triggered RDAC latches. See Figure 49 and Table 3. Table 3. Address Decode Table A A Latch Decoded RDAC# RDAC#2 RDAC#3 AD843 Only RDAC#4 AD843 Only CS CLK SDI AD843 ADDR DECODE SERIAL REGISTER RDAC RDAC 2 RDAC 4 Figure 49. Equivalent Input Control Logic The target RDAC latch is loaded with the last eight bits of the serial data-word completing one RDAC update. In the case of AD843, four separate -bit data-words must be clocked in to change all four VR settings. SHDN CS SDI CLK RS SERIAL REGISTER D Q CK RS SDO Figure 5. Detailed SDO Output Schematic of the AD843 All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 5. This structure applies to digital pins CS, SDI, SDO, RS, SHDN, and CLK. The digital input ESD protection allows for mixed power supply applications where 5 V CMOS logic can be used to drive an AD84, AD842, or AD843 operating from a 3 V power supply. Analog Pin A, Pin B, and Pin W are protected with a 2 Ω series resistor and parallel Zener diode (see Figure 52) Rev. D Page 22 of 32

23 AD84/AD842/AD843 DIGITAL PINS kω LOGIC Figure 5. Equivalent ESD Protection Circuits A, B,W 2Ω Figure 52. Equivalent ESD Protection Circuit (Analog Pins) A C A RDAC kω W C W 2pF C A = 9.4pF (DW/256) + 3pF C B = 9.4pF [ (DW/256)] + 3pF Figure 53. RDAC Circuit Simulation Model for RDAC = kω The AC characteristics of the RDAC are dominated by the internal parasitic capacitances and the external capacitive loads. The 3 db bandwidth of the AD843AN ( kω resistor) measures 6 khz at half scale as a potentiometer divider. Figure 3 provides the large signal Bode plot characteristics of the three available resistor versions kω, 5 kω, and kω. The gain flatness vs. frequency graph of the kω version predicts filter applications performance (see Figure 33). A parasitic simulation model has been developed and is shown in Figure 53. Listing I provides a macro model net list for the kω RDAC. C B B Listing I. Macro Model Net List for RDAC.PARAM DW=255, RDAC=E3 *.SUBCKT DPOT (A,W,) * CA A {DW/256*9.4E-2+3E-2} RAW A W {(-DW/256)*RDAC+5} CW W 2E-2 RBW W B {DW/256*RDAC+5} CB B {(-DW/256)*9.4E-2+3E-2} *.ENDS DPOT The total harmonic distortion plus noise (THD + N), shown in Figure 4, is measured at.3% in an inverting op amp circuit using an offset ground and a rail-to-rail OP279 amplifier. Thermal noise is primarily Johnson noise, typically 9 nv/ Hz for the kω version at f = khz. For the kω device, thermal noise becomes 29 nv/ Hz. Channel-to-channel crosstalk measures less than 65 db at f = khz. To achieve this isolation, the extra ground pins provided on the package to segregate the individual RDACs must be connected to circuit ground. AGND and DGND pins should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power supply rejection is typically 35 db at khz. Care is needed to minimize power supply ripple in high accuracy applications. Rev. D Page 23 of 32

24 AD84/AD842/AD843 APPLICATIONS The digital potentiometer (RDAC) allows many of the applications of a mechanical potentiometer to be replaced by a solidstate solution offering compact size and freedom from vibration, shock, and open contact problems encountered in hostile environments. A major advantage of the digital potentiometer is its programmability. Any settings can be saved for later recall in system memory. The two major configurations of the RDAC include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in Figure 37 and Figure 38. Certain boundary conditions must be satisfied for proper AD84/AD842/AD843 operation. First, all analog signals must remain within the GND to VDD range used to operate the single-supply AD84/AD842/AD843. For standard potentiometer divider applications, the wiper output can be used directly. For low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP29 or the OP279. Second, for ac signals and bipolar dc adjustment applications, a virtual ground is generally needed. Whichever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, including adequate bypass capacitance. Figure 4 shows one channel of the AD842 connected in an inverting programmable gain amplifier circuit. The virtual ground is set at 2.5 V, which allows the circuit output to span a ±2.5 V range with respect to virtual ground. The rail-to-rail amplifier capability is necessary for the widest output swing. As the wiper is adjusted from its midscale reset position (8H) toward the A terminal (code FFH), the voltage gain of the circuit is increased in successively larger increments. Alternatively, as the wiper is adjusted toward the B terminal (code H), the signal becomes attenuated. The plot in Figure 54 shows the wiper settings for a : range of voltage gain (V/V). Note the ± db of pseudologarithmic gain around db ( V/V). This circuit is mainly useful for gain adjustments in the range of.4 V/V to 4 V/V; beyond this range the step sizes become very large, and the resistance of the driving circuit can become a significant term in the gain equation. DIGITAL CODE (Decimal) ACTIVE FILTER INVERTING GAIN (V/V) Figure 54. Inverting Programmable Gain Plot The state variable active filter is one of the standard circuits used to generate a low-pass, high-pass, or band-pass filter. The digital potentiometer allows full programmability of the frequency, gain, and Q of the filter outputs. Figure 55 shows the filter circuit using a 2.5 V virtual ground, which allows a ±2.5 VP input and output swing. RDAC2 and RDAC3 set the LP, HP, and BP cutoff and center frequencies, respectively. These variable resistors should be programmed with the same data (as with ganged potentiometers) to maintain the best Circuit Q. Figure 56 shows the measured filter response at the band-pass output as a function of the RDAC2 and RDAC3 settings that produce a range of center frequencies from 2 khz to 2 khz. The filter gain response at the band-pass output is shown in Figure 57. At a center frequency of 2 khz, the gain is adjusted over a 2 db to +2 db range determined by RDAC. Circuit Q is adjusted by RDAC4. For more detailed reading on the state variable active filter, see Analog Devices application note AN-38. V IN B RDAC A RDAC4 B kω A2 kω B RDAC2.µF A3 B RDAC3.µF A LOW- PASS OP279 2 BAND- PASS HIGH- PASS Figure 55. Programmable State Variable Active Filter Rev. D Page 24 of 32

25 AD84/AD842/AD k k 2 2 AMPLITUDE (db) 2 4 AMPLITUDE (db) k k k 2k FREQUENCY (Hz) k k k FREQUENCY (Hz) 2k Figure 56. Programmed Center Frequency Band-Pass Response Figure 57. Programmed Amplitude Band-Pass Response Rev. D Page 25 of 32

26 AD84/AD842/AD843 OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 8.75 (.3445) 8.55 (.3366) 4. (.574) 3.8 (.497) (.244) 5.8 (.2284) 4. (.575) 3.8 (.496) (.244) 5.8 (.2283).25 (.98). (.4) COPLANARITY..27 (.5) BSC SEATING PLANE.75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67) 8.5 (.96).25 (.99) (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small outline package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches).25 (.98). (.39) COPLANARITY..27 (.5) BSC.5 (.2).3 (.22).75 (.689).35 (.53) SEATING PLANE.25 (.98).7 (.67) COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8.5 (.97) (.98).27 (.5).4 (.57) Figure 6. 4-Lead Standard Small Outline Package [SOIC] Narrow Body (R-4) Dimensions shown in millimeters and (inches) PIN.2 (5.33) MAX.5 (3.8).3 (3.3). (2.79).22 (.56).8 (.46).4 (.36) (9.69).75 (9.5).735 (8.67). (2.54) BSC.7 (.78).5 (.27).45 (.4) (7.).25 (6.35).24 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).43 (.92) MAX COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS..95 (4.95).3 (3.3).5 (2.92).4 (.36). (.25).8 (.2) PIN BSC BSC.2 MAX SEATING PLANE.2.9 COPLANARITY. 8 COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure Lead Plastic Dual-In-Line Package [PDIP] Narrow Body (N-4) Dimensions shown in inches and (millimeters) Figure 6. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters Rev. D Page 26 of 32

27 AD84/AD842/AD (32.5).25 (3.75).23 (3.24) PIN.2 (5.33) MAX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.46).4 (.36) 24. (2.54) BSC.7 (.78).6 (.52).45 (.4) (7.).25 (6.35).24 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).43 (.92) MAX COMPLIANT TO JEDEC STANDARDS MS--AF CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS..95 (4.95).3 (3.3).5 (2.92).4 (.36). (.25).8 (.2) PIN BSC.3.9. COPLANARITY 2.2 MAX SEATING PLANE BSC COMPLIANT TO JEDEC STANDARDS MO-53-AD Figure Lead Plastic Dual-In-Line Package [PDIP] Narrow Body (N-24-) Dimensions shown in inches and (millimeters) Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 5.6 (.642) 5.2 (.5984) (.2992) 7.4 (.293).65 (.493). (.3937).3 (.8). (.39) COPLANARITY..27 (.5) BSC.5 (.2).3 (.2) 2.65 (.43) 2.35 (.925) 8 SEATING.33 (.3) PLANE.2 (.79).75 (.295).25 (.98) (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-3-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small Outline Package [SOIC] Wide Body (R-24) Dimensions shown in millimeters and (inches) Rev. D Page 27 of 32