4-/6-Channel Digital Potentiometers AD5204/AD5206

Transcription

1 a FETURES 256 Position Multiple Independently Programmable Channels D524 4-Channel D526 6-Channel Potentiometer Replacement k, 5 k, k 3-ire SPI-Compatible Serial Data Input +2.7 V to +5.5 V Single Supply; 2.7 V Dual Supply Operation Power ON Midscale Preset PPLICTIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset djustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching SDO 4-/6-Channel Digital Potentiometers D524/D526 FUNCTIONL LOCK DIGRMS DO SER REG DI 2 D POER- ON PRESET EN DDR DEC D524 # D R D #4 R SHDN PR GENERL DESCRIPTION The D524/D526 provides four-/six-channel, 256 position digitally-controlled Variable Resistor (VR) devices. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the D524/ D526 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the terminal and the wiper or the Terminal and the wiper. The fixed -to- terminal resistance of kω, 5 kω, or kω has a nominal temperature coefficient of 7 ppm/ C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data word when the strobe is returned to logic high. serial data output pin at the opposite end of the serial register (D524 only) allows simple daisy-chaining in multiple VR applications without additional external decoding logic. SER REG DI 2 D POER- ON PRESET EN DDR DEC D526 # D R D #6 R n optional reset (PR) pin forces all the D524 wipers to the midscale position by loading H into the VR latch. The D524/D526 is available in both surface mount (SOL-24), TSSOP-24 and the 24-lead plastic DIP package. ll parts are guaranteed to operate over the extended industrial temperature range of 4 C to +5 C. For additional single, dual, and quad channel devices, see the D4/D42/ D43 products. REV. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. One Technology ay, P.O. ox 96, Norwood, M , U.S.. Tel: 7/ orld ide eb Site: Fax: 7/ nalog Devices, Inc., 999

2 D524/D526 SPECIFICTIONS ELECTRICL CHRCTERISTI ( = +5 V % or +3 V %, = V, = +, V = V, 4 C < T < +5 C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units DC CHRCTERISTI RHEOSTT MODE Specifications pply to ll VRs Resistor Differential NL 2 R-DNL R, = No Connect ± /4 + LS Resistor Nonlinearity Error 2 R-INL R, = No Connect 2 ± /2 +2 LS Nominal Resistor Tolerance 3 R T = +25 C 3 +3 % Resistance Temperature Coefficient R / T =, iper = No Connect 7 ppm/ C Nominal Resistance Match R/R CH to 2, 3, 4, or 5, 6; =.25.5 % iper Resistance R I = V/R, = +5 V 5 Ω DC CHRCTERISTI POTENTIOMETER DIVIDER MODE Specifications pply to ll VRs Resolution N its Differential Nonlinearity 4 DNL ± /4 + LS Integral Nonlinearity 4 INL 2 ± /2 +2 LS Voltage Divider Temperature Coefficient V / T Code = 4 H 5 ppm/ C Full-Scale Error V FSE Code = 7F H 2 LS Zero-Scale Error V ZSE Code = H + +2 LS RESISTOR TERMINLS Voltage Range 5, V, V V Capacitance 6 x, x C, C f = MHz, Measured to, Code = 4 H 45 pf Capacitance 6 x C f = MHz, Measured to, Code = 4 H 6 pf Shutdown Current 7 I _SD. 5 µ Common-Mode Leakage I CM = V = V =, = +2.7 V, = 2.5 V n DIGITL INPUTS ND OUTPUTS Input Logic High V IH = +5 V/+3 V 2.4/2. V Input Logic Low V IL = +5 V/+3 V./.6 V Output Logic High V OH R PULL UP = kω to +5 V 4.9 V Output Logic Low V OL I OL =.6 m, V LOGIC = +5 V.4 V Input Current I IL V IN = V or +5 V ± µ Input Capacitance 6 C IL 5 pf POER SUPPLIES Power Single Supply Range Range = V V Power Dual Supply Range /SS Range ± 2.3 ± 2.7 V Positive Supply Current I DD V IH = +5 V or V IL = V 2 6 µ Negative Supply Current I SS = 2.5 V, = +2.7 V 2 6 µ Power Dissipation P DISS V IH = +5 V or V IL = V.3 m Power Supply Sensitivity PSS = +5 V ± %.2.5 %/% DYNMIC CHRCTERISTI 6, 9 andwidth 3 d _K R = kω 72 khz _5K R = 5 kω 37 khz _K R = kω 69 khz Total Harmonic Distortion THD =.44 V rms, V = V dc, f = khz.4 % V Settling Time (K/5K/K) t S = 5 V, V = V, ± LS Error and 2/9/ µs Resistor Noise Voltage e N_ R = 5 kω, f = khz, PR = 9 nv/ Hz 6, INTERFCE TIMING CHRCTERISTI pplies to ll Parts Input Clock Pulsewidth t CH, t CL Clock Level High or Low 2 ns Data Setup Time t DS 5 ns Data Hold Time t DH 5 ns to SDO Propagation Delay t PD R L = 2 kω, C L < 2 pf 5 ns Setup Time t S 5 ns High Pulsewidth t 4 ns Reset Pulsewidth t RS 9 ns Fall to Fall Setup t H ns Fall to Rise Hold Time t H ns Rise to Clock Rise Setup t ns NOTES Typicals represent average readings at +25 C and = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I = /R for both = +3 V or = +5 V. 3 =, iper (V ) = No connect. 4 INL and DNL are measured at V with the configured as a potentiometer divider similar to a voltage output D/ converter. = and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit. 2 REV.

3 D524/D526 5 Resistor Terminals,,, have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the x terminals. ll x terminals are open-circuited in shutdown mode. P DISS is calculated from (I DD ). CMOS logic level inputs result in minimum power dissipation. 9 ll dynamic characteristics use = +5 V. See timing diagrams for location of measured values. ll input control voltages are specified with t R = t F = 2.5 ns (% to 9% of 3 V) and timed from a voltage level of.5 V. Switching characteristics are measured using both = +3 V or +5 V. Propagation delay depends on value of, R L and C L. See Operation section. Specifications subject to change without notice. SOLUTE MXIMUM RTINGS* (T = +25 C, unless otherwise noted) to V, +7 V to V, 7 V to V, V, V to , x x, x x, x x ± 2 m Digital Input and Output Voltage to V, +7 V Operating Temperature Range C to +5 C Maximum Junction Temperature (T J MX) C Storage Temperature C to +5 C Lead Temperature (Soldering, sec) C Package Power Dissipation (T J max T )/θ J Thermal Resistance θ J P-DIP (N-24) C/ SOIC (SOL-24) C/ TSSOP C/ *Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough the D524/D526 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. RNING! ESD SENSITIVE DEVICE REV. 3

4 D524/D526 V 2 D6 D5 D4 D3 D2 D D LOD Figure. Timing Diagram PR V t RS t S LS LS ERROR ND Figure 3. D524 Preset Timing Diagram (DT IN) SDO (DT OUT) V x OR Dx x OR Dx t t DS DH x OR Dx x OR Dx t CH t H t CL t S t PD_MX t t H t t S LS ERROR ND LS Figure 2. Detail Timing Diagram ORDERING GUIDE Model k Temperature Range Package Descriptions Package Options D524N 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D524R 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D524RU 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 D524N5 5 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D524R5 5 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D524RU5 5 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 D524N 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D524R 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D524RU 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 D526N 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D526R 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D526RU 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 D526N5 5 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D526R5 5 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D526RU5 5 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 D526N 4 C to +5 C 24-Lead Narrow ody (PDIP) N-24 D526R 4 C to +5 C 24-Lead ide ody (SOIC) R-24/SOL-24 D526RU 4 C to +5 C 24-Lead Thin Shrink SO Package (TSSOP) RU-24 The D524/D526 contains 5,925 transistors. Die size; 92 mil 4 mil,,4 sq. mil. 4 REV.

5 D524/D526 D524 PIN CONFIGURTION D526 PIN CONFIGURTION NC NC PR SHDN D524 (NOT TO SCLE) D526 (NOT TO SCLE) SDO NC NC = NO CONNECT D524 PIN FUNCTION DESCRIPTIONS Pin No. Name Description, 2, 2 NC Not Connected. 3 Ground. 4 Chip Select Input, ctive Low. hen returns high, data in the serial input register is decoded based on the address bits and loaded into the target latch. 5 PR ctive low preset to midscale; sets registers to H. 6 Positive power supply, specified for operation at both +3 V or +5 V. (Sum of + <5.5 V.) 7 SHDN ctive low input. Terminal open-circuit. Shutdown controls Variable Resistors # through #4. Serial Data Input. MS First. 9 Serial Clock Input, positive edge triggered. SDO Serial Data Output, Open Drain transistor requires pull-up resistor. Negative Power Supply, specified for operation at both V or 2.7 V. (Sum of + <5.5 V.) 3 3 Terminal # iper #3, addr = Terminal #3. 6 Terminal #. 7 iper #, addr = 2. Terminal #. 9 2 Terminal # iper #2, addr = Terminal # Terminal # iper #4, addr = Terminal #4. D526 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 6 Terminal # iper #6, addr = Terminal #6. 4 Ground. 5 Chip Select Input, ctive Low. hen returns high, data in the serial input register is decoded based on the address bits and loaded into the target latch. 6 Positive power supply, specified for operation at both +3 V or +5 V. (Sum of + <5.5 V.) 7 Serial Data Input. MS First. Serial Clock Input, positive edge triggered. 9 Negative Power Supply, specified for operation at both V or 2.7 V. (Sum of + <5.5 V.) 5 Terminal #5. 5 iper #5, addr = Terminal # Terminal # iper #3, addr = Terminal #3. 6 Terminal #. 7 iper #, addr = 2. Terminal #. 9 2 Terminal # iper #2, addr = Terminal # Terminal # iper #4, addr = Terminal #4. REV. 5

6 D524/D526 Typical Performance Characteristics 2 SITCH RESISTNCE / = 2.7V / = 2.7V/V / = 5.5V/V NORMLIZED GIN d 2 4 = 2.7V = 2.7V = mv rms DT = H k k 5k COMMON MODE V k k k M Figure 4. Incremental iper ON Resistance vs. Voltage Figure 7. 3 d andwidth vs. Terminal Resistance, ±2.7 V Dual Supply Operation DT = H DT = 4 H GIN d = 2.7V = 2.7V = mv rms DT = H V = V k 5k k 6.9 k k k Figure 5. Gain Flatness vs. Frequency GIN d k DT = 2 H DT = H DT = H DT = 4 H DT = 2 H DT = H = 2.7V = 2.7V = mv rms k k Figure. andwidth vs. Code, K Version M 6 2 DT = H DT = 4 H NORMLIZED GIN d 2 4 k = 2.7V = V = mv rms DT = H 2.7V +.5V k k k k 5k Figure 6. 3 d andwidth vs. Terminal Resistance, 2.7 V Single Supply Operation M GIN d = 2.7V V 54 SS = 2.7V = mv rms 6 k DT = 2 H DT = H DT = H DT = 4 H DT = 2 H DT = H k k Figure 9. andwidth vs. Code, 5K Version M 6 REV.

7 D524/D526 GIN d = 2.7V V 54 SS = 2.7V = mv rms 6 k DT = H DT = 4 H DT = 2 H DT = H DT = H DT = 4 H DT = 2 H DT = H k k Figure. andwidth vs. Code, K Version M SUPPLY CURRENT m k I DD, / = 5.5V/V, DT = 55H I SS, / = 2.7V, DT = 55H I DD, / = 5,5V/V, DT = FFH I SS, / = 2.7V, DT = FFH I DD, / = 2.7V/V, DT = FFH I DD, / = 2.7V/V, DT = 55H k M M Figure 3. Supply Current vs. Clock Frequency = 3.V % TRIP POINT V.. SINGLE SUPPLY = DUL SUPPLY = V PSRR d = 5.V % = 3.V % SUPPLY VOLTGE Volts Figure. Digital Input Trip Point vs. Supply Voltage k k k Figure 4. Power Supply Rejection vs. Frequency SUPPLY CURRENT m.. I SS T / = 2.7V I DD T / = 5.5V/V I DD T / = 2.7V THD + NOISE %.... = +2.7V = 2.7V R = k NONINVERTING TEST CIRCUIT INVERTING TEST CIRCUIT I DD T / = 2.7V/V INCREMENTL INPUT LOGIC VOLTGE Volts Figure 2. Supply Current vs. Input Logic Voltage. k k k Figure 5. Total Harmonic Distortion Plus Noise vs. Frequency REV. 7

8 D524/D526 OPERTION The D524/D526 provides a four-/six-channel, 256-position digitally-controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a - bit serial data word into the (Serial Data Input) pin. The format of this data word is three address bits, MS first, followed by eight data bits, MS first. Table I provides the serial register data word format. Table I. Serial-Data ord Format DDR DT D6 D5 D4 D3 D2 D D MS LS MS LS See Table IV for the D524/D526 address assignments to decode the location of VR latch receiving the serial register data in its 7 through. VR outputs can be changed one at a time in random sequence. The D524 presets to a midscale by asserting the PR pin, simplifying fault condition recovery at power up. oth parts have an internal power ON preset that places the wiper in a preset midscale condition at power ON. In addition, the D524 contains a power shutdown SHDN pin which places the in a zero power consumption state where Terminals x are open circuited and the wiper x is connected to x resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained, so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values. SHDN D6 D5 D4 D3 D2 D D & DECODER R S R S R S R S Figure 6. D524/D526 Equivalent Circuit PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the between Terminals and are available with values of kω, 5 kω and kω. The last digits of the part number determine the nominal resistance value, e.g., kω = ; kω =. The nominal resistance (R ) of the VR has 256 contact points accessed by the wiper terminal, plus the terminal contact. The eight-bit data word in the latch is decoded to select one of the 256 possible settings. The wiper s first connection starts at the terminal for x x x data H. This terminal connection has a wiper contact resistance of 45 Ω. The second connection ( kω part) is the first tap point located at 4 Ω [= R (nominal resistance)/256 + R = 4 Ω + 45 Ω] for data H. The third connection is the next tap point representing = 23 Ω for data 2 H. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at 6 Ω. The wiper does not directly connect to the terminal. See Figure 6 for a simplified diagram of the equivalent circuit. The general transfer equation determining the digitally programmed output resistance between x and x is: R (Dx) = (Dx)/256 R + R () where Dx is the data contained in the -bit x latch, and R is the nominal end-to-end resistance. For example, when V = V and terminal is open-circuit, the following output resistance values will be set for the following latch codes (applies to the K potentiometer): Table II. D (DEC) R - Output State Full Scale Midscale (PR = Condition) 4 LS 45 Zero Scale (iper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 45 Ω is present. Care should be taken to limit the current flow between and in this state to a maximum value of 2 m to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the replaces, it is totally symmetrical. The resistance between the iper and Terminal produces a digitally controlled resistance R. hen these terminals are used the terminal should be tied to the wiper. Setting the resistance value for R starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: R (Dx) = (256 Dx)/256 R + R (2) where Dx is the data contained in the -bit x latch, and R is the nominal end-to-end resistance. For example, when = V and terminal is tied to the iper the following output resistance values will be set for the following latch codes: Table III. D (DEC) R - Output State Full Scale Midscale (PR = Condition) 6 LS 45 Zero Scale REV.

9 D524/D526 The typical distribution of R from channel-to-channel matches within ± %. However, device-to-device matching is process lot dependent, having a ± 3% variation. The change in R with temperature has a 7 ppm/ C temperature coefficient. PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting terminal to +5 V and terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to LS less than +5 V. Each LS of voltage is equal to the voltage applied across Terminal divided by the 256-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals is: V (Dx) = Dx/256 + V (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore, the drift improves to 5 ppm/ C. SDO (D524 ONLY) SHDN (D524 ONLY) DO DI 2 SER REG D EN DDR DEC D524/D526 # D R D PR (D524 ONLY) #4/#6 R 4/6 4/6 4/6 Figure 7. lock Diagram DIGITL INTERFCING The D524/D526 contain a standard three-wire serial input control interface. The three inputs are clock (), and serial data input (). The positive-edge sensitive input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. Figure 7 shows more detail of the internal digital circuitry. hen is taken active low the clock loads data into the serial register on each positive clock edge, see Table IV. hen using a positive ( ) and negative ( ) supply voltage, the logic levels are still referenced to digital ground (). The serial-data-output (SDO) pin contains an open drain n- channel FET. This output requires a pull-up resistor in order to transfer data to the next package s pin. The pull-up resistor termination voltage may be larger than the supply of the D524 SDO output device, e.g., the D524 could operate at = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining several s from a single processor serial-data line. Clock period needs to be increased when using a pull-up resistor to the pin of the following device in the series. Capacitive loading at the daisy chain node SDO- between devices must be accounted for to successfully transfer data. hen daisy chaining is used, the should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding location. This would require 22 bits of address and data complying to the word format provided in Table I if two D524 fourchannel s are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. See Figure 9 for equivalent SDO output circuit schematic. Table IV. Input Logic Control Truth Table PR SHDN Register ctivity L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the pin. The eleventh previously entered bit is shifted out of the SDO pin. X P H H Load SR data into latch based on 2,, decode (Table V). X H H H No Operation. X X L H Sets all latches to midscale, wiper centered and SDO latch cleared. X H P H Latches all latches to H. X H H L Open circuits all Resistor terminals, connects to, turns off SDO output transistor. NOTE: P = positive edge, X = don t care, SR = shift register. Table V. ddress Decode Table 2 Latch Decoded # #2 #3 #4 #5 D526 Only #6 D526 Only The data setup and data hold times in the specification table determine the data valid time requirements. The last bits of the data word entered into the serial register are held when returns high. t the same time goes high it gates the address decoder enabling one of four or six positive edge triggered latches, see Figure detail. REV. 9

10 D524/D526 D524/D526 DDR DECODE SERIL REGISTER 2 4/6 I MS I = V/R NOMINL V+ V V+ I V MS V 2 [V + I (R II R )] R = HERE V = V MS HEN I = ND V 2 = V MS HEN I = /R Figure. Equivalent Input Control Logic The target latch is loaded with the last eight bits of the serial data word completing one DC update. Four separate - bit data words must be clocked in to change all four VR settings. SHDN SDO V+ Figure 24. iper Resistance Test Circuit ~ V+ = ± % V MS V MS V MS % PSS (%/%) = % PSRR (d) = 2 LOG ( ) PR SERIL REGISTER D Q CK RS Figure 9. Detail SDO Output Schematic of the D524 ll digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 2. pplies to digital pins,, SDO, PR, SHDN, Figure 25. Power Supply Sensitivity Test Circuit (PSS, PSRR) OFFSET V IN OFFSET IS OP V 34k LOGIC Figure 26. Inverting Programmable Gain Test Circuit +5V Figure 2. ESD Protection of Digital Pins OP279,, OFFSET V IN OFFSET IS Figure 2. ESD Protection of Resistor Terminals V+ V+ = LS = V+/256 Figure 22. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) NO CONNECT V MS V MS I Figure 27. Noninverting Programmable Gain Test Circuit OFFSET V IN 2.5V +5V + 5V Figure 2. Gain vs. Frequency Test Circuit I S R S =.V I S CODE = ØØ H +.V Figure 23. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) TO Figure 29. Incremental ON Resistance Test Circuit REV.

11 D524/D526 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PIN.2 (5.33) MX.2 (5.5).25 (3.).22 (.55).4 (.356) 24-Lead Narrow ody PDIP (N-24).275 (32.3).25 (2.6) (2.54) SC.7 (.77).45 (.5).2 (7.).24 (6.).6 (.52).5 (.3).5 (3.) MIN SETING PLNE.325 (.25).3 (7.62).5 (.3). (.24).95 (4.95).5 (2.93) C3677 9/99 24-Lead SOIC (R-24/SOL-24).64 (5.6).595 (5.2) (7.6).294 (7.4) (.65).3937 (.) PIN.43 (2.65).926 (2.35).29 (.74) 45.9 (.25). (.3).4 (.).5 (.27) SC.92 (.49).3 (.35) SETING PLNE.25 (.32).9 (.23).5 (.27).57 (.4) 24-Lead Thin Shrink SO Package (TSSOP) (RU-24).3 (7.9).33 (7.7) 24 3 PIN.6 (.5).2 (.5) 2.77 (4.5).69 (4.3).433 (.) MX.256 (6.5).246 (6.25) PRINTED IN U.S.. SETING PLNE.256 (.65) SC. (.3).75 (.9).79 (.2).35 (.9).2 (.7).2 (.5) REV.