256-Position SPI-Compatible Digital Potentiometer AD5160

Transcription

1 Data Sheet FETURES 56-position End-to-end resistance: 5 kω, kω, 5 kω, kω Compact SOT-3-8 (.9 mm 3 mm) package SPI-compatible interface Power-on preset to midscale Single supply:.7 V to 5.5 V Low temperature coefficient: 45 ppm/ C Low power, IDD = 8 μ ide operating temperature: 4 C to +5 C Evaluation board available PPLICTIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Gain control and offset adjustment 56-Position SPI-Compatible Digital Potentiometer D56 FUNCTIONL LOCK DIGRM CS SDI CLK SPI INTERFCE IPER REGISTER V DD Figure. PIN CONFIGURTION V DD CLK 3 4 D56 TOP VIE (Not to Scale) CS SDI GENERL DESCRIPTION The D56 provides a compact.9 mm 3 mm packaged solution for 56-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors but with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. Figure. The wiper settings are controllable through an SPI-compatible digital interface. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDC latch. Operating from a.7 V to 5.5 V power supply and consuming less than 5 μ allows for usage in portable battery-operated applications. The terms digital potentiometer, VR, and RDC are used interchangeably. Rev. C Document Feedback Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology ay, P.O. ox 96, Norwood, M 6-96, U.S.. Tel: nalog Devices, Inc. ll rights reserved. Technical Support

2 D56 TLE OF CONTENTS Features... pplications... Functional lock Diagram... Pin Configuration... General Description... Revision History... Specifications... 3 Electrical Characteristics 5 kω Version... 3 kω, 5 kω, kω Versions... 4 Timing Characteristics ll Versions... 5 bsolute Maximum Ratings... 6 ESD Caution... 6 Pin Configuration and Function Descriptions... 7 Data Sheet Typical Performance Characteristics...8 Test Circuits... SPI Interface... 3 Theory of Operation... 4 Programming the Variable Resistor... 4 Programming the Potentiometer Divider... 5 SPI-Compatible 3-ire Serial us... 5 ESD Protection... 5 Power-Up Sequence... 5 Layout and Power Supply ypassing... 5 Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY /4 Rev. to Rev. C Changes to Ordering Guide /9 Rev. to Rev. Changes to Ordering Guide... 6 /9 Rev. to Rev. Deleted Shutdown Supply Current Parameter and Endnote 7, Table... 3 Changes to Resistor Noise Voltage Density Parameter, Table... 3 Deleted Shutdown Supply Current Parameter and Endnote 7, Table... 4 Changes to Resistor Noise Voltage Density Parameter, Table... 4 dded Endnote to Table Changes to Table Changes to the Rheostat Operation Section... 4 Deleted Terminal Voltage Operating Range Section and Figure 4, Renumbered Figures Sequentially... 3 Changes to Figure 4 and Figure Changes to Ordering Guide /3 Revision : Initial Version Rev. C Page of 6

3 Data Sheet D56 SPECIFICTIONS ELECTRICL CHRCTERISTICS 5 kω VERSION VDD = 5 V ± %, or 3 V ± %; V = +VDD; V = V; 4 C < T < +5 C; unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit DC CHRCTERISTICS Rheostat Mode Resistor Differential Nonlinearity R-DNL R, V = no connect.5 ±. +.5 LS Resistor Integral Nonlinearity R-INL R, V = no connect 4 ± LS Nominal Resistor Tolerance 3 R T = 5 C + % Resistance Temperature Coefficient R/ T V = VDD, wiper = no connect 45 ppm/ C iper Resistance R 5 Ω Potentiometer Divider Mode Specifications apply to all VRs Resolution N 8 its Differential Nonlinearity 4 DNL.5 ±. +.5 LS Integral Nonlinearity 4 INL.5 ± LS Voltage Divider Temperature Coefficient V/ T Code = x8 5 ppm/ C Full-Scale Error VFSE Code = xff 6.5 LS Zero-Scale Error VZSE Code = x + +6 LS RESISTOR TERMINLS Voltage Range 5 V, V, V VDD V Capacitance, Capacitance 6 C, f = MHz, measured to, code = x8 45 pf Capacitance 6 C f = MHz, measured to, code = x8 6 pf Common-Mode Leakage ICM V = V = VDD/ n DIGITL INPUTS Input Logic High VIH.4 V Input Logic Low VIL.8 V Input Logic High VIH VDD = 3 V. V Input Logic Low VIL VDD = 3 V.6 V Input Current IIL VIN = V or 5 V ± µ Input Capacitance 6 CIL 5 pf POER SUPPLIES Power Supply Range VDD RNGE V Supply Current IDD VIH = 5 V or VIL = V 3 8 µ Power Dissipation 7 PDISS VIH = 5 V or VIL = V, VDD = 5 V. m Power Supply Sensitivity PSS VDD = +5 V ± %, code = midscale ±. ±.5 %/% DYNMIC CHRCTERISTICS 6, 8 andwidth 3 d _5K R = 5 kω, code = x8. MHz Total Harmonic Distortion THD V = V rms, V = V, f = khz.5 % V Settling Time ts V = 5 V, V = V, ± LS error band µs Resistor Noise Voltage Density en_ R =.5 kω 6 nv/ Hz Typical specifications represent average readings at +5 C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 V = VDD, wiper (V) = no connect. 4 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DC). V = VDD and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal, Resistor Terminal, and Resistor Terminal have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 8 ll dynamic characteristics use VDD = 5 V. Rev. C Page 3 of 6

4 D56 Data Sheet kω, 5 kω, kω VERSIONS VDD = 5 V ± %, or 3 V ± %; V = VDD; V = V; 4 C < T < +5 C; unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit DC CHRCTERISTICS Rheostat Mode Resistor Differential Nonlinearity R-DNL R, V = no connect ±. + LS Resistor Integral Nonlinearity R-INL R, V = no connect ±.5 + LS Nominal Resistor Tolerance 3 R T = 5 C 5 +5 % Resistance Temperature Coefficient R/ T V = VDD, 45 ppm/ C iper = no connect iper Resistance R VDD = 5 V 5 Ω Potentiometer Divider Mode Specifications apply to all VRs Resolution N 8 its Differential Nonlinearity 4 DNL ±. + LS Integral Nonlinearity 4 INL ±.3 + LS Voltage Divider Temperature V/ T Code = x8 5 ppm/ C Coefficient Full-Scale Error VFSE Code = xff 3 LS Zero-Scale Error VZSE Code = x 3 LS RESISTOR TERMINLS Voltage Range 5 V,, VDD V Capacitance, Capacitance 6 C, f = MHz, measured to, code = 45 pf x8 Capacitance 6 C f = MHz, measured to, code = 6 pf x8 Common-Mode Leakage ICM V = V = VDD/ n DIGITL INPUTS Input Logic High VIH.4 V Input Logic Low VIL.8 V Input Logic High VIH VDD = 3 V. V Input Logic Low VIL VDD = 3 V.6 V Input Current IIL VIN = V or 5 V ± µ Input Capacitance 6 CIL 5 pf POER SUPPLIES Power Supply Range VDD RNGE V Supply Current IDD VIH = 5 V or VIL = V 3 8 µ Power Dissipation 7 PDISS VIH = 5 V or VIL = V, VDD = 5 V. m Power Supply Sensitivity PSS VDD = +5 V ± %, code = midscale ±. ±.5 %/% DYNMIC CHRCTERISTICS 6, 8 andwidth 3 d R = kω/5 kω/ kω, Code = x8 6//4 khz Total Harmonic Distortion THD V = V rms, V = V, f = khz, R =.5 % kω V Settling Time ( kω/5 kω/ kω) ts V = 5 V, V = V, µs ± LS error band Resistor Noise Voltage Density en_ R = 5 kω 9 nv/ Hz Typical specifications represent average readings at +5 C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 V = VDD, wiper (V) = no connect. 4 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DC). V = VDD and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal, Resistor Terminal, and Resistor Terminal have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 8 ll dynamic characteristics use VDD = 5 V. Rev. C Page 4 of 6

5 Data Sheet D56 TIMING CHRCTERISTICS LL VERSIONS VDD = +5V ± %, or +3V ± %; V = VDD; V = V; 4 C < T < +5 C; unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit SPI INTERFCE TIMING CHRCTERISTICS, Specifications apply to all parts Clock Frequency fclk 5 MHz Input Clock Pulse idth tch, tcl Clock level high or low ns Data Setup Time tds 5 ns Data Hold Time tdh 5 ns CS Setup Time tcss 5 ns CS High Pulse idth tcs 4 ns CLK Fall to CS Fall Hold Time tcsh ns CLK Fall to CS Rise Hold Time tcsh ns See the timing diagram, Figure 38, for location of measured values. ll input control voltages are specified with tr = tf = ns (% to 9% of 3 V) and timed from a voltage level of.5 V. Guaranteed by design and not subject to production test. Rev. C Page 5 of 6

6 D56 SOLUTE MXIMUM RTINGS T = +5 C, unless otherwise noted. Table 4. Parameter Rating VDD to.3 V to +7 V V, V, V to VDD Maximum Current IMX I, I Pulsed ± m I, I Continuous 5 kω, kω 4.7 m 5 kω.95 m kω.48 m Digital Inputs and Output Voltage to V to +7 V Temperature Operating Temperature Range 4 C to +5 C Maximum Junction Temperature (TJMX) 5 C Storage Temperature 65 C to +5 C Thermal Resistance (SOT-3 Package) θj Thermal Impedance 6ºC/ θjc Thermal Impedance 9 C/ Reflow Soldering (Pb-Free) Peak Temperature 6 C Time at Peak Temperature sec to 4 sec Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and applied voltage across any two of the,, and terminals at a given resistance. Package power dissipation = (TJMX T)/θJ. Data Sheet Stresses at or above those listed under bsolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CUTION Rev. C Page 6 of 6

7 Data Sheet D56 PIN CONFIGURTION ND FUNCTION DESCRIPTIONS V DD CLK 3 4 D56 TOP VIE (Not to Scale) CS SDI Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin Mnemonic Description Terminal. VDD Positive Power Supply. 3 Digital Ground. 4 CLK Serial Clock Input. Positive edge triggered. 5 SDI Serial Data Input. 6 CS Chip Select Input, ctive Low. hen CS returns high, data loads into the DC register. 7 Terminal. 8 Terminal. Rev. C Page 7 of 6

8 D56 TYPICL PERFORMNCE CHRCTERISTICS RHEOSTT MODE INL (LS)..8 5V Figure 4. R-INL vs. Code vs. Supply Voltages 3V POTENTIOMETER MODE DNL (LS) Data Sheet.8 4 C +5 C C +5 C Figure 7. DNL vs. Code, VDD = 5 V.. RHEOSTT MODE DNL (LS) V 3V POTENTIOMETER MODE INL (LS) V 3V Figure 5. R-DNL vs. Code vs. Supply Voltages Figure 8. INL vs. Code vs. Supply Voltages.. POTENTIOMETER MODE INL (LS) _ 4 C +5 C +85 C +5 C POTENTIOMETER MODE DNL(LS) V 3V Figure 6. INL vs. Code, VDD = 5 V Figure 9. DNL vs. Code vs. Supply Voltages Rev. C Page 8 of 6

9 Data Sheet D56 RHEOSTT MODE INL (LS) C +5 C +85 C +5 C ZSE, ZERO-SCLE ERROR (µ) V DD = 5.5V V DD =.7V Figure. R-INL vs. Code, VDD = 5 V TEMPERTURE ( C) Figure 3. Zero-Scale Error vs. Temperature RHEOSTT MODE DNL (LS) _ 4 C +5 C +85 C +5 C I DD SUPPLY CURRENT (µ) V DD = 5.5V V DD =.7V Figure. R-DNL vs. Code, VDD = 5 V TEMPERTURE ( C) Figure 4. Supply Current vs. Temperature.5 7 FSE, FULL-SCLE ERROR (LS) V DD =.7V V DD = 5.5V I SHUTDON CURRENT (n) V DD = 5V TEMPERTURE ( C) TEMPERTURE ( C) Figure. Full-Scale Error vs. Temperature Figure 5. Shutdown Current vs. Temperature Rev. C Page 9 of 6

10 D56 Data Sheet REF LEVEL.d /DIV 6.d MRKER Hz MG (/R) 9.49d RHEOSTT MODE TEMPCO (ppm/ C) x8 x4 x x x8 x4 x x Figure 6. Rheostat Mode Tempco R/ T vs. Code 54 6 k k k M STRT.Hz STOP.Hz Figure 9. Gain vs. Frequency vs. Code, R = kω POTENTIOMETER MODE TEMPCO (ppm/ C) REF LEVEL.d /DIV 6.d x8 x4 x x x8 x4 x x MRKER Hz MG (/R) 9.4d Figure 7. Potentiometer Mode Tempco V/ T vs. Code 54 6 k k k M STRT.Hz STOP.Hz Figure. Gain vs. Frequency vs. Code, R = 5 kω REF LEVEL.d /DIV 6.d MRKER.Hz MG (/R) 8.98d REF LEVEL.d /DIV 6.d MRKER Hz MG (/R) 9.5d 6 x8 6 x8 x4 x4 8 x 8 x 4 3 x x8 x4 4 3 x x8 36 x x 36 x4 4 4 x x k k k M STRT.Hz STOP.Hz Figure 8. Gain vs. Frequency vs. Code, R = 5 kω 6 k k k M STRT.Hz STOP.Hz Figure. Gain vs. Frequency vs. Code, R = kω Rev. C Page of 6

11 Data Sheet D56 REF LEVEL 5.d 5.5 /DIV.5d k.6 MHz k 5 MHz 5k MHz k 54 MHz V R = 5k R = 5k CLK 9.5 R = k R = k Ch mv Ch 5. V M ns CH 3. V..5 k k M M STRT.Hz STOP.Hz 6 Figure. 3 d Code = x8 CODE = x8, V = V DD, V = V Figure 5. Digital Feedthrough V = 5V V = V 4 PSRR (d) V DD = 3V DC ± % p-p C V CS V DD = 5V DC ± % p-p C k k k M FREQUENCY (Hz) Figure 3. PSRR vs. Frequency Ch mv Ch 5. V M ns CH 5mV Figure 6. Midscale Glitch, Code x8 to Code x7f V DD = 5V V = 5V V = V I DD ( ) CODE = x55 CODE = xff V CS k k M M FREQUENCY (Hz) Figure 4. IDD vs. Frequency Ch 5.V Ch 5. V M ns CH 3. V Figure 7. Large Signal Settling Time, Code xff to Code x Rev. C Page of 6

12 D56 Data Sheet TEST CIRCUITS Figure 8 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables. 5V V+ DUT V+ = V DD LS = V+/ N V IN OP79 V OUT V MS OFFSET DUT OFFSET IS Figure 8. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 33. Test Circuit for Noninverting Gain NO CONNECT DUT V MS I OFFSET V IN.5V DUT +5V D86 5V V OUT Figure 9. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 34. Test Circuit for Gain vs. Frequency V MS DUT V I = V DD /R NOMINL DUT I S R S =.V I S CODE = x.v V MS R = [V MS V MS ]/I V SS TO V DD Figure 3. Test Circuit for iper Resistance Figure 35. Test Circuit for Incremental On Resistance V+ V V DD V+ = V DD % VMS PSRR (d) = LOG V DD V MS % PSS (%/%) = V DD % V MS ( ) V DD V SS DUT NC I CM V CM NC NC = NO CONNECT Figure 3. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Figure 36. Test Circuit for Common-Mode Leakage Current DUT V IN 5V OFFSET OFFSET IS OP79 V OUT Figure 3. Test Circuit for Inverting Gain Rev. C Page of 6

13 Data Sheet D56 SPI INTERFCE Table 6. Serial Data-ord Format D7 D6 D5 D4 D3 D D D MS LS 7 SDI CLK CS VOUT D7 D6 D5 D4 D3 D D D RDC REGISTER LOD Figure 37. SPI Interface Timing Diagram (V = 5 V, V = V, V = VOUT) SDI (DT IN) Dx Dx t DS t CH CLK t CH t CS t CSHO t CL t CSH CS t CSS t CS t S V DD VOUT ±LS Figure 38. SPI Interface Detailed Timing Diagram (V = 5 V, V = V, V = VOUT) Rev. C Page 3 of 6

14 D56 THEORY OF OPERTION The D56 is a 56-position digitally controlled variable resistor (VR) device. n internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the RDC between Terminal and Terminal is available in 5 kω, kω, 5 kω, and kω. The final two or three digits of the model number as listed in the Ordering Guide section determine the nominal resistance value, for example, in model D56RJZ, the represents kω; and in D56RJZ5, the 5 represents 5 kω. The nominal resistance (R) of the VR has 56 contact points accessed by the wiper terminal, plus the terminal contact. The 8-bit data in the RDC latch is decoded to select one of the 56 possible settings. ssuming a kω part is used, the first connection of the wiper starts at the terminal for Data x. ecause there is a 6 Ω wiper contact resistance, such connection yields a minimum of 6 Ω resistance between Terminal and Terminal. The second connection is the first tap point, which corresponds to 99 Ω (R = R/56 + R = 39 Ω + 6 Ω) for Data x. The third connection is the next tap point, representing 38 Ω ( 39 Ω + 6 Ω) for Data x, and so on. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at 996 Ω (R LS + R). Figure 39 shows a simplified diagram of the equivalent RDC circuit where the last resistor string is not accessed; therefore, there is LS less of the nominal resistance at full scale in addition to the wiper resistance. D7 D6 D5 D4 D3 D D D RDC LTCH ND DECODER R S R S R S R S Figure 39. Equivalent RDC Circuit Data Sheet The general equation determining the digitally programmed output resistance between and is R D ( D) R R () 56 where: D is the decimal equivalent of the binary code loaded in the 8-bit RDC register. R is the end-to-end resistance. R is the wiper resistance contributed by the on resistance of the internal switch. In summary, if R = kω and the terminal is open circuited, the following output resistance R is set for the indicated RDC latch codes. Table 7. Codes and Corresponding R Resistance D (Dec.) R (Ω) Output State Full Scale (R LS + R) 8 56 Midscale 99 LS 6 Zero Scale (iper Contact Resistance) Note that in the zero-scale condition, a finite wiper resistance of 6 Ω is present. Take care to limit the current flow between and in this state to a maximum pulse current of no more than m. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDC between the iper and Terminal also produces a digitally controlled complementary resistance (R). hen these terminals are used, the terminal can be opened. Setting the resistance value for R starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is 56 D R ( D) R R () 56 For R = kω and the terminal is open circuited, the following output resistance R is set for the indicated RDC latch codes. Table 8. Codes and Corresponding R Resistance D (Dec.) R (Ω) Output State Full Scale 8 56 Midscale 996 LS,6 Zero Scale Typical device-to-device matching is process lot dependent and may vary by up to ±3%. ecause the resistance element is processed in thin film technology, the change in R with temperature has a very low 45 ppm/ C temperature coefficient. Rev. C Page 4 of 6

15 Data Sheet PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to- and wiper-to- proportional to the input voltage at -to-. Unlike the polarity of VDD to, which must be positive, voltage across to, to, and to can be at either polarity. If ignoring the effect of the wiper resistance for approximation, connecting the terminal to 5 V and the terminal to ground produces an output voltage at the wiper-to- starting at V up to LS less than 5 V. Each LS of voltage is equal to the voltage applied across Terminal and Terminal divided by the 56 positions of the potentiometer divider. The general equation defining the output voltage at V with respect to ground for any valid input voltage applied to Terminal and Terminal is D 56 D V ( D) V V (3) For a more accurate calculation, which includes the effect of wiper resistance, V can be found as R ( D) R ( D) V ( D) V V (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors (R and R) and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/ C. SPI-COMPTILE 3-IRE SERIL US The D56 contains a 3-wire SPI-compatible digital interface (SDI, CS, and CLK). The 8-bit serial word must be loaded MS first. The format of the word is shown in Table 6. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. hen CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 37). The data setup and data hold times in the specification table determine the valid timing requirements. The D56 uses an 8-bit serial input data register word that is transferred to the internal RDC register when the CS line returns to logic high. Extra MS bits are ignored. D56 ESD PROTECTION ll digital inputs are protected with a series input resistor and parallel Zener ESD structures are shown in Figure 4 and Figure 4. This applies to SDI, CLK, and CS, which are the digital input pins. 34Ω LOGIC Figure 4. ESD Protection of Digital Pins,, Figure 4. ESD Protection of Resistor Terminals POER-UP SEQUENCE ecause the ESD protection diodes limit the voltage compliance at the,, and terminals, it is important to power VDD/ before applying any voltage to the,, and terminals; otherwise, the diode forward biases such that VDD is powered unintentionally and may affect the rest of the user s circuit. The ideal power-up sequence is in the following order:, VDD, digital inputs, and then V//. The relative order of powering V, V, V, and the digital inputs is not important as long as they are powered after VDD/. LYOUT ND POER SUPPLY YPSSING It is a good practice to employ compact, minimum lead length layout design. Keep the leads to the inputs as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. ypass supply leads to the device with disc or chip ceramic capacitors of. μf to. μf. To minimize any transient disturbance and low frequency ripple, apply low ESR μf to μf tantalum or electrolytic capacitors at the supplies (see Figure 4). To minimize the ground bounce, join the digital ground remotely to the analog ground at a single point. V DD C3 + C F. F V DD D56 Figure 4. Power Supply ypassing Rev. C Page 5 of 6

16 D56 Data Sheet OUTLINE DIMENSIONS PIN INDICTOR MX.5 MIN.95 SC.38 MX. MIN.65 SC.45 MX.95 MIN SETING PLNE. MX.8 MIN SC COMPLINT TO JEDEC STNDRDS MO-78- Figure Lead Small Outline Transistor Package [SOT-3] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model,, 3 R (Ω) Temperature Package Description Package Option randing D56RJZ5-R 5 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D6Q D56RJZ5-RL7 5 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D6Q D56RJZ-R k 4 C to +5 C 8-Lead SOT-3 RJ-8 D9 D56RJZ-RL7 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D9 D56RJZ5-R 5 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D8J D56RJZ5-RL7 5 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D8J D56RJZ-R k 4 C to +5 C 8-Lead SOT-3 RJ-8 D D56RJZ-RL7 k 4 C to +5 C 8-Lead SOT-3 RJ-8 D EVL-D56DZ Evaluation oard The D56 contains 53 transistors. Die size: 3.7 mil 76.8 mil = 358 sq. mil. Z = RoHS Compliant Part. 3 The EVL-D56DZ board is shipped with the kω R resistor option; however, the board is compatible with all available resistor value options nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3434--/4(C) Rev. C Page 6 of 6