AD5292-EP Position, Digital Potentiometer with Maximum ±1% R-Tolerance Error and 20-TP Memory. Data Sheet FUNCTIONAL BLOCK DIAGRAM V DD FEATURES

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1 24-Position, Digital Potentiometer with Maximum ±% R-Tolerance Error and 2-TP Memory FEATURES Single-channel, 24-position resolution 2 kω nominal resistance Maximum ±% nominal resistor tolerance error (resistor performance mode) 2-times programmable wiper memory Rheostat mode temperature coefficient: 35 ppm/ C Voltage divider temperature coefficient: 5 ppm/ C +9 V to +33 V single-supply operation ±9 V to ±6.5 V dual-supply operation SPI-compatible serial interface Wiper setting readback Power-on refreshed from 2-TP memory ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC) Temperature range: 55 C to +25 C Controlled manufacturing baseline assembly/test site fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The is a single-channel, 24-position digital potentiometer that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. This device is capable of operating across a wide voltage range, supporting both dual supply operation at ±.5 V to ±6.5 V and single-supply operation at +2 V to +33 V, while ensuring less than % end-to-end resistor tolerance error and offering 2- time programmable (2-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The terms digital potentiometer and RDAC are used interchangeably. V LOGIC SCLK SYNC DIN SDO RDY FUNCTIONAL BLOCK DIAGRAM V DD POWER-ON RESET SERIAL INTERFACE DATA OTP MEMORY BLOCK V SS EXT_CAP Figure. RESET RDAC REGISTER GND The device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the 2-TP memory. The does not require any external voltage supply to facilitate fuse blow, and there are 2 opportunities for permanent programming. During 2-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). The is available in a compact 4-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of 55 C to +25 C. Additional application and technical information can be found in the AD5292 data sheet. A W B 95- Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Enhanced Product Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Resistor Performance Mode Code Range... 4 Interface Timing Specifications...5 Absolute Maximum Ratings...7 Thermal Resistance...7 ESD Caution...7 Pin Configuration and Function Descriptions...8 Typical Performance Characteristics...9 Test Circuits... 4 Outline Dimensions... 5 Ordering Guide... 5 REVISION HISTORY 9/ Revision : Initial Version Rev. Page 2 of 6

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 2 V to 33 V, VSS = V; VDD =.5 V to 6.5 V, VSS =.5 V to 6.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, 55 C < TA < +25 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resolution N Bits Resistor Differential Nonlinearity 2 R-DNL RWB, VA = NC + LSB Resistor Integral Nonlinearity 2 R-INL RAB =2 kω, VDD VSS = 26 V to 33 V 2 +2 LSB R-INL RAB =2 kω, VDD VSS = 2 V to 26 V 3 +3 LSB Nominal Resistor Tolerance (R-Perf Mode) 3 RAB/RAB See Table 2 ±.5 + % Nominal Resistor Tolerance (Normal RAB/RAB ±7 % Mode) 4 Resistance Temperature Coefficient ( RAB/RAB)/ T 6 Code = full scale; see Figure 4 35 ppm/ C Wiper Resistance RW Code= zero scale 6 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution N Bits Differential Nonlinearity 5 DNL + LSB Integral Nonlinearity 5 INL LSB Voltage Divider Temperature Coefficient 4 ( VW/VW)/ T 6 Code = half scale; see Figure 7 5 ppm/ C Full-Scale Error VWFSE Code = full scale 8 + LSB Zero-Scale Error VWZSE Code = zero scale LSB RESISTOR TERMINALS Terminal Voltage Range 6 VA, VB, VW VSS VDD V Capacitance A, Capacitance B 4 CA, CB f = MHz, measured to GND, 85 pf code = half scale Capacitance W 4 CW f = MHz, measured to GND, 65 pf code = half scale Common-Mode Leakage Current 4 ICM VA = VB = VW 2 ± 2 na DIGITAL INPUTS JEDEC compliant Input Logic High 4 VIH VLOGIC = 2.7 V to 5.5 V 2. V Input Logic Low 4 VIL VLOGIC = 2.7 V to 5.5 V.8 V Input Current IIL VIN = V or VLOGIC ± μa Input Capacitance 4 CIL 5 pf DIGITAL OUTPUTS (SDO and RDY) Output High Voltage 4 VOH RPULL_UP = 2.2 kω to VLOGIC VLOGIC.4 V Output Low Voltage 4 VOL RPULL_UP = 2.2 kω to VLOGIC GND +.4 V Three-State Leakage Current + μa Output Capacitance 4 COL 5 pf POWER SUPPLIES Single-Supply Power Range VDD VSS = V 9 33 V Dual-Supply Power Range VDD/VSS ±9 ±6.5 V Positive Supply Current IDD VDD/VSS = ±6.5 V. 2 μa Negative Supply Current ISS VDD/VSS = ±6.5 V 2. μa Logic Supply Range VLOGIC V Logic Supply Current ILOGIC VLOGIC = 5 V, VIH = 5 V or VIL = GND μa OTP Store Current 4, 7 ILOGIC_PROG VIH = 5 V or VIL = GND 25 ma OTP Read Current 4, 8 ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 ma Power Dissipation 9 PDISS VIH = 5 V or VIL = GND 8 μw Power Supply Rejection Ratio PSRR VDD/ VSS = ±5 V ± %.3 %/% Rev. Page 3 of 6

4 Parameter Symbol Conditions Min Typ Max Unit 5, DYNAMIC CHARACTERISTICS Bandwidth BW 3 db 52 khz Total Harmonic Distortion THDW VA = V rms, VB = V, f = khz 93 db VW Settling Time ts VA = 3 V, VB = V, ±.5 LSB error band, initial code = zero scale, board capacitance = 7 pf Code = full-scale, normal mode 75 ns Code = full-scale, R-Perf mode 2.5 μs Code = half-scale, normal mode 2.5 μs Code = half-scale, R-Perf mode 5 μs Resistor Noise Density en_wb Code = half-scale, TA = 25 C, khz to 2 khz nv/ Hz Typical values represent average readings at 25 C, VDD = 5 V, VSS = 5 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code xb and Code x3ff or between RWA at Code x3f3 and Code x. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of ma for VA < 2 V and.2 ma for VA 2 V. 3 Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = V. DNL specification limits of ± LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 55 μs. 8 Different from operating current; supply current for fuse read lasts approximately 55 μs. 9 PDISS is calculated from (IDD VDD) + (ISS VSS) + (ILOGIC VLOGIC). All dynamic characteristics use VDD = 5 V, VSS = 5 V, and VLOGIC = 5 V. RESISTOR PERFORMANCE MODE CODE RANGE Table 2. Resistor 55 C < TA < +25 C Tolerance per VDD VSS = 3 V to 33 V VDD VSS = 26 V to 3 V VDD VSS = 22 V to 26 V VDD VSS = 2 V to 22 V Code RWB RWA RWB RWA RWB RWA RWB RWA % R-Tolerance From xef From x From xf4 From x From xf4 From x N/A N/A to x3ff to x2 to x3ff to x2b to x3ff to x2b 2% R-Tolerance From xc3 to x3ff From x to x33c From xe6 to x3ff From x to x39 From x3 to x3ff From x to x2ce From x3 to x3ff From x to x2ce 3% R-Tolerance From x73 to x3ff From x to x38c From x87 to x3ff From x to x378 From xaf to x3ff From x to x35 From xaf to x3ff From x to x35 Rev. Page 4 of 6

5 INTERFACE TIMING SPECIFICATIONS VDD/VSS = ±5 V, VLOGIC = 2.7 V to 5.5 V, 55 C < TA < +25 C. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit Unit Description t 2 2 ns min SCLK cycle time t2 ns min SCLK high time t3 ns min SCLK low time t4 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 ns min SCLK falling edge to SYNC rising edge t8 4 3 ns min Minimum SYNC high time t9 4 ns min SYNC rising edge to next SCLK fall ignore t 4 ns min RDY rising edge to SYNC falling edge t 4 4 ns max SYNC rising edge to RDY fall time t μs max RDY low time, RDAC register write command execute time (R-Perf mode) t2 4 4 ns max RDY low time, RDAC register write command execute time (normal mode) t2 4 8 ms max RDY low time, memory program execute time t2 4.5 ms min Software/hardware reset t ns max RDY low time, RDAC register readback execute time t3 4.3 ms max RDY low time, memory readback execute time t ns max SCLK rising edge to SDO valid treset 2 ns min Minimum RESET pulse width (asynchronous) tpower-up 5 2 ms max Power-on OTP restore time All input signals are specified with tr = tf = ns/v (% to 9% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 5 MHz. 3 Refer to t2 and t3 for RDAC register and memory commands operations. 4 RPULL_UP = 2.2 kω to VLOGIC, with a capacitance load of 68 pf. 5 Maximum time after VLOGIC is equal to 2.5 V. DB9 (MSB) DB (LSB) C3 C2 C C D9 D8 D7 D6 D5 D4 D3 D2 D D CONTROL BITS Figure 2. Shift Register Content DATA BITS 95-3 Rev. Page 5 of 6

6 Timing Diagrams t 4 t 2 t t 7 SCLK t 8 t 3 t 9 SYNC t 5 t 6 DIN X X C3 C2 D7 D6 D2 D D SDO t t t 2 RDY RESET t RESET 95-4 Figure 3. Write Timing Diagram, CPOL =, CPHA = SCLK t 9 SYNC DIN X X C3 D D X X C3 D D t 4 SDO X X C3 D D RDY t t Figure 4. Read Timing Diagram, CPOL =, CPHA = Rev. Page 6 of 6

7 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 4. Parameter Rating VDD to GND.3 V to +35 V VSS to GND +.3 V to 25 V VLOGIC to GND.3 V to +7 V VDD to VSS 35 V VA, VB, VW to GND VSS.3 V, VDD +.3 V Digital Input and Output Voltage to GND.3 V to VLOGIC +.3 V EXT_CAP Voltage to GND.3 V to +7 V IA, IB, IW Continuous ±3 ma Pulsed Frequency > khz ±3/d 2 Frequency khz ±3/ d 2 Operating Temperature Range 3 55 C to +25 C Maximum Junction Temperature (TJ max) 5 C Storage Temperature Range 65 C to +5 C Reflow Soldering Peak Temperature 26 C Time at Peak Temperature 2 sec to 4 sec Package Power Dissipation (TJ max TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is defined by JEDEC specification JESD-5 and the value is dependent on the test board and test environment. Table 5. Thermal Resistance Package Type θja θjc Unit 4-Lead TSSOP 93 2 C/W JEDEC 2S2P test board, still air ( m/sec to m/sec air flow). ESD CAUTION Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of OTP memory. Rev. Page 7 of 6

8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET V SS A W B V DD EXT_CAP TOP VIEW (Not to Scale) 4 RDY 3 SDO 2 SYNC SCLK DIN 9 GND 8 V LOGIC 95-6 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 2-TP memory register. Factory default loads midscale until the first 2-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. 2 VSS Negative Supply. Connect to V for single-supply applications. This pin should be decoupled with. μf ceramic capacitors and μf capacitors. 3 A Terminal A of RDAC. VSS VA VDD. 4 W Wiper Terminal of RDAC. VSS VW VDD. 5 B Terminal B of RDAC. VSS VB VDD. 6 VDD Positive Power Supply. This pin should be decoupled with. μf ceramic capacitors and μf capacitors. 7 EXT_CAP External Capacitor. Connect a μf capacitor to EXT_CAP. This capacitor must have a voltage rating of 7 V. 8 VLOGIC Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with. μf ceramic capacitors and μf capacitors. 9 GND Ground Pin, Logic Ground Reference. DIN Serial Data Input. The has a 6-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 5 MHz. 2 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 6 th clock cycle. If SYNC is taken high before the 6 th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. 3 SDO Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. 4 RDY Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory. Rev. Page 8 of 6

9 TYPICAL PERFORMANCE CHARACTERISTICS INL (LSB). 4 C C +5 C DNL (LSB) C +25 C +5 C Figure 6. R-INL in R-Perf Mode vs. Code Figure 9. R-DNL in R-Perf Mode vs. Code INL (LSB).5 DNL (LSB) C +25 C +5 C C +25 C +5 C Figure 7. INL in R-Perf Mode vs. Code Figure. DNL in R-Perf Mode vs. Code INL (LSB).4.2 DNL (LSB) C +25 C +5 C C +25 C +5 C Figure 8. R-INL in Normal Mode vs. Code Figure. R-DNL in Normal Mode vs. Code Rev. Page 9 of 6

10 C +25 C +5 C..5 4 C +25 C +5 C.4 INL (LSB).2.2 DNL (LSB) Figure 2. INL in Normal Mode vs. Code Figure 5. DNL in Normal Mode vs. Code V DD /V SS = ±5V V LOGIC = +5V.2.8 V DD = ±5V SUPPLY CURRENT (na) I LOGIC I DD SUPPLY CURRENT I LOGIC (ma) I SS TEMPERATURE ( C) Figure 3. Supply Current (IDD, ISS, ILOGIC) vs. Temperature DIGITAL INPUT VOLTAGE (V) Figure 6. Supply Current ILOGIC vs. Digital Input Voltage 95-3 RHEOSTAT MODE TEMPCO (ppm/ C) V DD = 3V V SS = V POTENTIOMETER MODE TEMPCO (ppm/ C) V DD = 3V V SS = V Figure 4. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 7. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code Rev. Page of 6

11 5 x2 x 5 x8 2 GAIN (db) x4 x2 x x8 PSRR (db) x4 45 x2 5 x k k FREQUENCY (Hz) k M k k FREQUENCY (Hz) k M Figure 8. 2 kω Gain vs. Frequency vs. Code Figure 2. Power Supply Rejection Ratio vs. Frequency 5 3 V DD /V SS = ±5V CODE = HALF SCALE V IN = V rms NOISE BW = 22kHz 2 4 V DD /V SS = ±5V, CODE = HALF SCALE f IN = khz NOISE BW = 22kHz THD + N (db) THD + N (db) k k k FREQUENCY (Hz) Figure 9. THD + Noise vs. Frequency AMPLITUDE (V rms) Figure 22. THD + Noise vs. Amplitude 95-22,, 35 BANDWIDTH (Hz) 9, 8, 7, 6, 5, 4, 3, 2, pf 75pF 5pF 25pF SUPPLY CURRENT I DD (ma) , TIME (ms) Figure 2. Bandwidth vs. Code vs. Net Capacitance Figure 23. IDD Waveform While Blowing/Reading Fuse Rev. Page of 6

12 VOLTAGE (V) SYNC 2 V WB, CODE: FULL SCALE, NORMAL MODE V WB, CODE: FULL SCALE, R-PERF MODE TIME (µs) Figure 24. Large-Signal Settling Time from Code Zero Scale V DD /V SS = 3V/V V LOGIC = 5V V A = V DD V B = V SS V WB, CODE: HALF-SCALE, NORMAL MODE V WB, CODE: HALF-SCALE, R-PERF MODE VOLTAGE (μv) V DD /V SS = ±5V V A = V DD V B = V SS CODE = HALF CODE TIME (µs) Figure 27. Digital Feedthrough V DD /V SS = 3V/V V A = V DD V B = V SS 6 5 V DD /V SS = ±5V V LOGIC = +5V THEORETICAL I WB_MAX (ma) VOLTAGE (V) Figure 25. Theoretical Maximum Current vs. Code TIME (ms) Figure 28. VEXT_CAP Waveform While Reading Fuse Or Calibration V DD /V SS = ±5V V LOGIC = +5V V A = V DD V B = V SS 8 6 V DD /V SS = ±5V V LOGIC = +5V.6 VOLTAGE (V).4.2 VOLTAGE (V) TIME (µs) Figure 26. Maximum Transition Glitch TIME (ms) Figure 29. VEXT_CAP Waveform While Writing Fuse Rev. Page 2 of 6

13 3 25 V DD /V SS = ±5V 8 7 V A = V DD V B = V SS TEMPERATURE = 25 C 6 NUMBER OF CODES 2 5 NUMBER OF CODES TEMPERATURE ( C) Figure 3. Code Range > % R-Tolerance Error vs. Temperature VOLTAGE V DD /V SS Figure 3. Code Range > % R-Tolerance Error vs. Voltage Rev. Page 3 of 6

14 TEST CIRCUITS Figure 32 to Figure 37 define the test conditions used in the Specifications section. NC DUT A W B V MS I W NC = NO CONNECT 95-4 V+ ~ V DD V A A B W V MS V+ = V DD ± % PSRR (db) = 2 log V MS V DD V MS % PSS (%/%) = V DD % Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 35. Power Supply Sensitivity (PSS, PSRR) V+ DUT A W B V+ = V DD LSB = V+/2 N V MS OFFSET GND V IN A DUT B 2.5V W +5V OP42 5V V OUT Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 36. Gain vs. Frequency +5V 5V NC GND DUT A W B R WB =.V I WB CODE = x R W = R WB + 2.V I WB V DD DUT V SS GND A B W I CM GND GND +5V 5V A = NC V SS TO V DD Figure 34. Wiper Resistance NC GND NC = NO CONNECT +5V 5V Figure 37. Common-Mode Leakage Current Rev. Page 4 of 6

15 OUTLINE DIMENSIONS BSC PIN BSC COPLANARITY.9..2 MAX SEATING PLANE.2.9 COMPLIANT TO JEDEC STANDARDS MO-53-AB- Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters A ORDERING GUIDE Model RAB (kω) Resolution Memory Temperature Range Package Description Package Option AD5292SRU-2-EP TP 55 C to +25 C 4-Lead TSSOP RU-4 Rev. Page 5 of 6

17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD5292BRUZ-2 AD5292BRUZ-5 AD5292BRUZ--RL7 AD5292BRUZ- EVAL-AD5292EBZ AD5292BRUZ- 5-RL7 AD5292SRU-2-EP AD5292BRUZ-2-RL7

AD5293. Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer. Preliminary Technical Data

AD5293. Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer. Preliminary Technical Data Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer FEATURES Single-channel, 1024-position resolution 20 kω, 50 kω and 100 kω nominal resistance Calibrated 1% Nominal Resistor Tolerance Rheostat