I 2 C-Compatible, 256-Position Digital Potentiometers AD5241/AD5242

Transcription

1 I 2 C-Compatible, 256-Position Digital Potentiometers AD524/AD5242 FEATURES 256 positions kω, kω, MΩ Low temperature coefficient: 3 ppm/ C Internal power on midscale preset Single-supply 2.7 V to 5.5 V or dual-supply ±2.7 V for ac or bipolar operation I 2 C-compatible interface with readback capability Extra programmable logic outputs Self-contained shutdown feature Extended temperature range: 4 C to +5 C APPLICATIONS Multimedia, video, and audio Communications Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage-to-current conversion Line impedance matching SHDN SHDN V DD V SS SDA SCL GND FUNCTIONAL LOCK DIAGRAM A O O 2 RDAC REGISTER ADDR DECODE AD524 8 SERIAL INPUT REGISTER REGISTER 2 PR-ON RESET AD AD Figure. AD524 Functional lock Diagram A A O O 2 REGISTER 926- V DD V SS RDAC REGISTER RDAC REGISTER 2 SDA SCL GND ADDR DECODE AD5242 SERIAL INPUT REGISTER 8 PR-ON RESET AD AD Figure 2. AD5242 Functional lock Diagram GENERAL DESCRIPTION The AD524/AD5242 provide a single-/dual-channel, 256- position, digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper, or the terminal and the wiper. For the AD5242, the fixed A-to- terminal resistance of kω, kω, or MΩ has a % channel-to-channel matching tolerance. The nominal temperature coefficient of both parts is 3 ppm/ C. iper position programming defaults to midscale at system power on. hen powered, the VR wiper position is programmed by an I 2 C -compatible, 2-wire serial data interface. oth parts have two extra programmable logic outputs available that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. The AD524/AD5242 are available in surface-mount, 4-lead SOIC and 6-lead SOIC packages and, for ultracompact solutions, 4-lead TSSOP and 6-lead TSSOP packages. All parts are guaranteed to operate over the extended temperature range of 4 C to +5 C. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology ay, P.O. ox 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TALE OF CONTENTS Features... Applications... Functional lock Diagram... General Description... Revision History... 2 Specifications... 3 kω, kω, MΩ Version... 3 Timing Diagrams... 5 Absolute Maximum Ratings... 6 ESD Caution... 6 Pin Configurations and Function Descriptions... 7 Typical Performance Characteristics... 8 Test Circuits... Theory of Operation... 2 Programming the Variable Resistor... 2 Programming the Potentiometer Divider... 3 Digital Interface... 3 Readback RDAC Value... 4 Multiple Devices on One us... 4 Level-Shift for idirectional Interface... 4 Additional Programmable Logic Output... 5 Shutdown Function... 5 Outline Dimensions... 6 Ordering Guide... 8 REVISION HISTORY 2/9 Rev. to Rev. C Changes to Features Section... Changes to kω, kω, MΩ Version Section... 3 Changes to Table Deleted Digital Potentiometer Selection Guide Section... 4 Changed Self-Contained Shutdown Function Section to Shutdown Function Section... 5 Changes to Shutdown Function Section... 5 Changes to Ordering Guide /2 Rev. A to Rev. Additions to Features... Changes to General Description... Changes to Specifications... 2 Changes to Absolute Maximum Ratings... 4 Additions to Ordering Guide... 4 Changes to TPC 8 and TPC Changes to Readback RDAC Value Section... Changes to Additional Programmable Logic Output Section.. Added Self-Contained Shutdown Section... 2 Added Figure Changes to Digital Potentiometer Selection Guide /2 Rev. to Rev. A Edits to Features... Edits to Functional lock Diagrams... Edits to Absolute Maximum Ratings... 4 Changes to Ordering Guide... 4 Edits to Pin Function Descriptions... 5 Edits to Figures, 2, Added Readback RDAC Value Section, Additional Programmable Logic Output Section, and Figure 7; Renumbered Sequentially... Changes to Digital Potentiometer Selection Guide... 4 Rev. C Page 2 of 2

3 SPECIFICATIONS kω, kω, MΩ VERSION VDD = 2.7 V to 5.5 V, VA = VDD, V = V, 4 C < TA < +5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS, RHEOSTAT MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution N 8 its Resistor Differential Nonlinearity 2 R-DNL R, VA = no connect ±.4 + LS Resistor Integral Nonlinearity 2 R-INL R, VA = no connect 2 ±.5 +2 LS Nominal Resistor Tolerance ΔRA/RA TA = 25 C, RA = kω 3 +3 % TA = 25 C, 3 +5 % RA = kω/ MΩ Resistance Temperature Coefficient (ΔRA/RA)/ VA = VDD, wiper = 3 ppm/ C ΔT 6 no connect iper Resistance R I = VDD/R 6 2 Ω DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution N 8 its Differential Nonlinearity 3 DNL ±.4 + LS Integral Nonlinearity 3 INL 2 ±.5 +2 LS Voltage Divider Temperature Coefficient (ΔV/V)/ T 6 Code = x8 5 ppm/ C Full-Scale Error VFSE Code = xff.5 LS Zero-Scale Error VZSE Code = x.5 LS RESISTOR TERMINALS Voltage Range 4 VA, V, V VSS VDD V Capacitance (A, ) 5 CA, C f = MHz, measured 45 pf to GND, code = x8 Capacitance () 5 C f = MHz, measured 6 pf to GND, code = x8 Common-Mode Leakage ICM VA = V = V na DIGITAL INPUTS Input Logic High (SDA and SCL) VIH.7 VDD VDD +.5 V V Input Logic Low (SDA and SCL) VIL VDD V Input Logic High (AD and AD) VIH VDD = 5 V 2.4 VDD V Input Logic Low (AD and AD) VIL VDD = 5 V.8 V Input Logic High VIH VDD = 3 V 2. VDD V Input Logic Low VIL VDD = 3 V.6 V Input Current IIL VIH = 5 V or VIL = GND μa Input Capacitance 5 CIL 3 pf DIGITAL OUTPUT VOL IOL = 3 ma.4 V Output Logic Low (SDA) VOL IOL = 6 ma.6 V Output Logic Low (O and O2) VOL ISINK =.6 ma.4 V Output Logic High (O and O2) VOH ISOURCE = 4 μa 4 V Three-State Leakage Current (SDA) IOZ VIH = 5 V or VIL = GND ± μa Output Capacitance 5 COZ 3 8 pf POER SUPPLIES Power Single-Supply Range VDD RANGE VSS = V V Power Dual-Supply Range VDD/VSS RANGE ±2.3 ±2.7 V Positive Supply Current IDD VIH = 5 V or VIL = GND. 5 μa Negative Supply Current ISS VSS = 2.5 V, VDD = +2.5 V +. 5 μa Power Dissipation 6 PDISS VIH = 5 V or VIL = GND,.5 25 VDD = 5 V μ Power Supply Sensitivity PSS %/% Rev. C Page 3 of 2

4 Parameter Symbol Conditions Min Typ Max Unit 5, 7, 8 DYNAMIC CHARACTERISTICS 3 d andwidth _ kω RA = kω, code = x8 65 khz _ kω RA = kω, code = x8 69 khz _ MΩ RA = MΩ, code = x8 6 khz Total Harmonic Distortion THD VA = V rms + 2 V dc,.5 % V = 2 V dc, f = khz V Settling Time ts VA = VDD, V = V, ± LS 2 μs error band, RA = kω Resistor Noise Voltage en_ R = 5 kω, f = khz 4 nv Hz INTERFACE TIMING CHARACTERISTICS (APPLIES TO ALL PARTS 5, 9 ) SCL Clock Frequency fscl 4 khz us Free Time etween Stop and Start, tuf t.3 μs Hold Time (Repeated Start), thd; STA t2 After this period, the first 6 ns clock pulse is generated Low Period of SCL Clock, tlo t3.3 μs High Period of SCL Clock, thigh t4.6 5 μs Setup Time for Repeated Start Condition, tsu; STA t5 6 ns Data Hold Time, thd; DAT t6 9 ns Data Setup Time, tsu; DAT t7 ns Rise Time of oth SDA and SCL Signals, tr t8 3 ns Fall Time of oth SDA and SCL Signals, tf t9 3 ns Setup Time for Stop Condition, tsu; STO t Typicals represent average readings at 25 C, VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits. 3 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. See Figure Resistor Terminal A, Resistor Terminal, and Resistor Terminal have no limitations on polarity with respect to each other. 5 Guaranteed by design, not subject to production test. 6 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 7 andwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use VDD = 5 V. 9 See timing diagram in Figure 3 for location of measured values. Rev. C Page 4 of 2

5 TIMING DIAGRAMS t 8 SDA t t8 t 9 t 2 SCL t 2 t 4 P S t 3 t 6 t 7 S Figure 3. Detail Timing Diagram t 5 P t Data of AD524/AD5242 is accepted from the I 2 C bus in the following serial format. Table 2. S AD AD R/ A A/ RS SD O O2 X X X A D7 D6 D5 D4 D3 D2 D D A P Slave Address yte Instruction yte Data yte where: S = start condition P = stop condition A = acknowledge X = don t care AD, AD = Package pin programmable address bits. Must be matched with the logic states at Pins AD and AD. R/ = Read enable at high and output to SDA. rite enable at low. A/ = RDAC subaddress select; for RDAC and for RDAC2. RS = Midscale reset, active high. SD = Shutdown in active high. Same as SHDN except inverse logic. O, O2 = Output logic pin latched values D7, D6, D5, D4, D3, D2, D, D = data bits. SCL SDA AD AD R/ A/ RS SD O O2 X X X D7 D6 D5 D4 D3 D2 D D START Y MASTER FRAME SLAVE ADDRESS YTE ACK Y AD524 FRAME 2 INSTRUCTION YTE Figure 4. riting to the RDAC Serial Register ACK Y AD524 FRAME 3 DATA YTE ACK Y AD524 STOP Y MASTER SCL 9 9 SDA AD AD R/ D7 D6 D5 D4 D3 D2 D D ACK Y AD524 START Y MASTER FRAME SLAVE ADDRESS YTE NO ACK Y MASTER FRAME 2 DATA YTE FROM PREVIOUSLY SELECTED RDAC REGISTER IN RITE MODE Figure 5. Reading Data from a Previously Selected RDAC Register in rite Mode STOP Y MASTER Rev. C Page 5 of 2

6 ASOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, V, V to GND IA, I, I Rating.3 V to +7 V V to 7 V 7 V VSS to VDD RA = kω in TSSOP-4 5. ma RA = kω in TSSOP-4.5 ma RA = MΩ in TSSOP-4.5 ma Digital Input Voltage to GND V to VDD +.3 V Operating Temperature Range 4 C to +5 C Thermal Resistance θja 4-Lead SOIC 58 C/ 6-Lead SOIC 73 C/ 4-Lead TSSOP 26 C/ 6-Lead TSSOP 8 C/ Maximum Junction Temperature (TJ max) 5 C Package Power Dissipation PD = (TJ max TA)/θJA Storage Temperature Range 65 C to +5 C Lead Temperature Vapor Phase, 6 sec 25 C Infrared, 5 sec 22 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Maximum current increases at lower resistance and different packages. Rev. C Page 6 of 2

7 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A 4 O O 6 A NC A V DD SHDN SCL SDA 3 2 AD524 O 2 4 TOP VIE V SS 5 (Not to Scale) DGND 6 9 AD 7 8 AD NC = NO CONNECT Figure 6. AD524 Pin Configuration V DD SHDN SCL SDA 3 4 AD5242 TOP VIE 5 (Not to Scale) O 2 2 V SS DGND AD 9 AD Figure 7. AD5242 Pin Configuration Table 4. AD524 Pin Function Descriptions Pin No. Mnemonic Description A Resistor Terminal A. 2 iper Terminal. 3 Resistor Terminal. 4 VDD Positive Power Supply, Specified for Operation from 2.2 V to 5.5 V. 5 SHDN Active low, asynchronous connection of iper to Terminal, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. 6 SCL Serial Clock Input. 7 SDA Serial Data Input/Output. 8 AD Programmable Address it for Multiple Package Decoding. it AD and it AD provide four possible addresses. 9 AD Programmable Address it for Multiple Package Decoding. it AD and it AD provide four possible addresses. DGND Common Ground. VSS Negative Power Supply, Specified for Operation from V to 2.7 V. 2 O2 Logic Output Terminal O2. 3 NC No Connect. 4 O Logic Output Terminal O. Table 5. AD5242 Pin Function Descriptions Pin No. Mnemonic Description O Logic Output Terminal O. 2 A Resistor Terminal A. 3 iper Terminal. 4 Resistor Terminal. 5 VDD Positive Power Supply, Specified for Operation from 2.2 V to 5.5 V. 6 SHDN Active Low, Asynchronous Connection of iper to Terminal, and Open Circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD, if not used. 7 SCL Serial Clock Input. 8 SDA Serial Data Input/Output. 9 AD Programmable Address it for Multiple Package Decoding. it AD and it AD provide four possible addresses. AD Programmable Address it for Multiple Package Decoding. it AD and it AD provide four possible addresses. DGND Common Ground. 2 VSS Negative Power Supply, Specified for Operation from V to 2.7 V. 3 O2 Logic Output Terminal O Resistor Terminal iper Terminal 2. 6 A2 Resistor Terminal A2. Rev. C Page 7 of 2

8 POTENTIOMETER MODE DIFFERENTIAL NONLINEARITY (LS) I DD SUPPLY CURRENT (µa) RHEOSTAT MODE INTEGRAL NONLINEARITY (LS) NOMINAL RESISTANCE (kω) RHEOSTAT MODE DIFFERENTIAL NONLINEARITY (LS) POTENTIOMETER MODE INTEGRAL NONLINEARITY (LS) AD524/AD5242 TYPICAL PERFORMANCE CHARACTERISTICS. V DD = +2.7V V DD = +5.5V V DD = ±2.7V.5 V DD = +2.7V V DD = +5.5V V DD = ±2.7V.5.25 V DD /V SS = +2.7V/V V DD /V SS = +2.7V V DD /V SS = +2.7V/V, +5.5V/V.5 V DD /V SS = +5.5V/V, ±2.7V CODE (Decimal) Figure 8. RDNL vs. Code CODE (Decimal) Figure. INL vs. Code V DD /V SS = +2.7V/V V DD = +2.7V V DD = +5.5V V DD = ±2.7V k k MΩ V DD = 2.7V T A = 25 C kω.5 V DD /V SS = +5.5V/V, ±2.7V kω CODE (Decimal) TEMPERATURE ( C) Figure 9. RINL vs. Code Figure 2. Nominal Resistance vs. Temperature.25 V DD = +2.7V V DD = +5.5V V DD = ±2.7V k.3 V DD /V SS = +2.7V/V, +5.5V/V, ±2.7V k V DD = 5V V DD = 3V.3 V DD = 2.5V CODE (Decimal) INPUT LOGIC VOLTAGE (V) Figure. DNL vs. Code Figure 3. Supply Current vs. Input Logic Voltage Rev. C Page 8 of 2

9 RHEOSTAT MODE TEMPCO (ppm/ C) GAIN (d) I DD SUPPLY CURRENT (µa) IPER RESISTANCE (Ω) AD524/AD5242. R A = kω V DD = 5.5V 9 T A = 25 C SHUTDON CURRENT (µa) V DD /V SS = +2.7V/V V DD /V SS = ±2.7V/V V DD /V SS = +5.5V/V TEMPERATURE ( C) Figure 4. Shutdown Current vs. Temperature COMMON-MODE (V) Figure 7. Incremental iper Contact vs. VDD/VSS POTENTIOMETER MODE TEMPCO (ppm/ C) MΩ VERSION kω VERSION kω VERSION V DD /V SS = 2.7V/V T A = 25 C A: V DD /V SS = 5.5V/V CODE = xff : V DD /V SS = 3.3V/V CODE = xff C: V DD /V SS = 2.5V/V CODE = xff D: V DD /V SS = 5.5V/V CODE = x55 E: V DD /V SS = 3.3V/V CODE = x55 F: V DD /V SS = 2.5V/V CODE = x55 D A E F C CODE (Decimal) Figure 5. ΔV/ΔT Potentiometer Mode Temperature Coefficient FREQUENCY (khz) Figure 8. Supply Current vs. Frequency k kω VERSION MΩ VERSION kω VERSION V DD /V SS = 2.7V/V T A = 25 C CODE (Decimal) Figure 6. ΔR/ΔT Rheostat Mode Temperature Coefficient xff x8 6 x4 2 x2 8 x 24 x8 3 x4 36 x2 42 x k k k FREQUENCY (Hz) Figure 9. AD5242 k Ω Gain vs. Frequency vs. Code M Rev. C Page 9 of 2

10 GAIN (d) GAIN (d) AD524/AD xff x8 x4 x2 x x8 x4 x2 x xff x8 x4 x2 x x8 x4 x2 x 54 k k k FREQUENCY (Hz) Figure 2. AD5242 kω Gain vs. Frequency vs. Code k k k FREQUENCY (Hz) Figure 2. AD5242 MΩ Gain vs. Frequency vs. Code Rev. C Page of 2

11 TEST CIRCUITS Figure 22 to Figure 3 define the test conditions used in the product specifications table. 5V V+ DUT A V+ = V DD LS = V+/2 N V MS Figure 22. Potentiometer Divider Nonlinearity Error (INL, DNL) OFFSET GND V IN A DUT OFFSET IAS OP279 Figure 27. Noninverting Gain V OUT NO CONNECT DUT A V MS Figure 23. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) I OFFSET GND V IN 2.5V DUT A +5V OP42 5V Figure 28. Gain vs. Frequency V OUT V MS2 DUT A V I = V DD /R NOMINAL DUT I S R S =.V I S CODE = x.v V MS R = [V MS V MS2 ]/I Figure 24. iper Resistance V SS TO V DD Figure 29. Incremental On Resistance V+ V A V DD A V+ = V DD ±% ΔV MS PSRR (d) = 2 LOG ΔV DD ΔV MS % PSS (%/%) = ΔV DD % V MS Figure 25. Power Supply Sensitivity (PSS, PSRR) V DD DUT V SS GND NC A NC I CM V CM Figure 3. Common-Mode Leakage Current A DUT 5V OFFSET GND OFFSET IAS OP279 Figure 26. Inverting Gain V OUT Rev. C Page of 2

12 THEORY OF OPERATION The AD524/AD5242 provide a single-/dual-channel, 256- position digitally controlled variable resistor (VR) device. The terms VR, RDAC, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. To program the VR settings, refer to the Digital Interface section. oth parts have an internal power-on preset that places the wiper in midscale during power-on that simplifies the fault condition recovery at power-up. In addition, the shutdown pin (SHDN) of AD524/AD5242 places the RDAC in an almost zero power consumption state where Terminal A is open circuited and iper is connected to Terminal, resulting in only leakage current being consumed in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. hen the part returns from shutdown, the stored VR setting is applied to the RDAC. D7 D6 D5 D4 D3 D2 D D SHDN RDAC LATCH AND DECODER R R R R A S SHDN S 2 N S N 2 2 S S R R A /2 N DIGITAL CIRCUITRY OMITTED FOR CLARITY Figure 3. Equivalent RDAC Circuit PROGRAMMING THE VARIALE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal is available in kω, kω, and MΩ. The final two or three digits of the part number determine the nominal resistance value, for example, kω =, kω =, and MΩ = M. The nominal resistance (RA) of the VR has 256 contact points accessed by the wiper terminal, plus the terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a kω part is used; the first connection of the wiper starts at the terminal for Data x. ecause there is a 6 Ω wiper contact resistance, such connection yields a minimum of 6 Ω resistance between Terminal and Terminal. The second connection is the first tap point that corresponds to 99 Ω (R = RA/256 + R = ) for Data x. The third connection is the next tap point representing 38 Ω ( ) for Data x2, and so on. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at,2 Ω [RA LS + R] Figure 3 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string is not accessed; therefore, there is LS less of the nominal resistance at full scale in addition to the wiper resistance. The general equation determining the digitally programmed resistance between and is D R(D) = RA + R () 256 where: D is the decimal equivalent of the binary code between and 255, which is loaded in the 8-bit RDAC register. RA is the nominal end-to-end resistance. R is the wiper resistance contributed by the on resistance of the internal switch. Again, if RA = kω, Terminal A can be either open circuit or tied to. Table 6 shows the R resistance based on the code set in the RDAC latch. Table 6. R (D) at Selected Codes for RA = kω D (DEC) R (Ω) Output State Full-scale (R LS + R) Midscale 99 LS 6 Zero-scale (wiper contact resistance) Note that in the zero-scale condition, a finite wiper resistance of 6 Ω is present. Care should be taken to limit the current flow between and in this state to a maximum current of no more than 2 ma. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between iper and Terminal A also produces a digitally controlled resistance, RA. hen these terminals are used, Terminal can be opened or tied to the wiper terminal. The minimum RA resistance is for Data xff and increases as the data loaded in the latch decreases in value. The general equation for this operation is 256 D RA(D) = RA + R (2) 256 For RA = kω, Terminal can be either open circuit or tied to. Table 7 shows the RA resistance based on the code set in the RDAC latch. Table 7. RA (D) at Selected Codes for RA = kω D (DEC) RA (Ω) Output State Full-scale Midscale 2 LS 6 Zero-scale Rev. C Page 2 of 2

13 The typical distribution of the nominal resistance RA from channel to channel matches within ±% for AD5242. Deviceto-device matching is process lot dependent, and it is possible to have ±3% variation. ecause the resistance element is processed in thin film technology, the change in RA with temperature has no more than a 3 ppm/ C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to- and wiper-to-a to be proportional to the input voltage at A-to-. Unlike the polarity of VDD /VSS, which must be positive, voltage across terminal A to terminal, terminal to terminal A, and terminal to terminal can be at either polarity provided that VSS is powered by a negative supply. If ignoring the effect of the wiper resistance for approximation, connecting Terminal A to 5 V and Terminal to ground produces an output voltage at the wiper-to- starting at V up to LS less than 5 V. Each LS of voltage is equal to the voltage applied across Terminal A divided by the 256 positions of the potentiometer divider. ecause AD524/AD5242 can be supplied by dual supplies, the general equation defining the output voltage at V with respect to ground for any valid input voltage applied to Terminal A and Terminal is D 256 D V ( D) = VA + V (3) which can be simplified to D V ( D) = V + V (4) 256 A where D is the decimal equivalent of the binary code between to 255 that is loaded in the 8-bit RDAC register. For a more accurate calculation, including the effects of wiper resistance, V can be found as V R ( D) RA ( D) ( D) = VA + V (5) R R A where R(D) and RA(D) can be obtained from Equation and Equation 2. Operation of the digital potentiometer in divider mode results in a more accurate operation over temperature. Unlike rheostat mode, the output voltage is dependent on the ratio of the internal resistors, RA and R, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/ C. A DIGITAL INTERFACE 2-ire Serial us The AD524/AD5242 are controlled via an I 2 C-compatible serial bus. The RDACs are connected to this bus as slave devices. Referring to Figure 3 and Figure 4, the first byte of AD524/ AD5242 is a slave address byte. It has a 7-bit slave address and an R/ bit. The five MSs are and the following two bits are determined by the state of the AD and AD pins of the device. AD and AD allow users to use up to four of these devices on one bus. The 2-wire, I 2 C serial bus protocol operates as follows:. The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The following byte is the Frame, slave address byte, which consists of the 7-bit slave address followed by an R/ bit (this bit determines whether data is read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/ bit is high, the master reads from the slave device. If the R/ bit is low, the master writes to the slave device. 2. A write operation contains an extra instruction byte more than the read operation. The Frame 2 instruction byte in write mode follows the slave address byte. The MS of the instruction byte labeled A/ is the RDAC subaddress select. A low selects RDAC and a high selects RDAC2 for the dualchannel AD5242. Set A/ to low for the AD524. The second MS, RS, is the midscale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where RA = R. The third MS, SD, is a shutdown bit. A logic high on SD causes the RDAC to open circuit at Terminal A while shorting the wiper to Terminal. This operation yields almost a Ω rheostat mode or V in potentiometer mode. This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low. The following two bits are O2 and O. They are extra programmable logic outputs that users can use to drive other digital loads, logic gates, LED drivers, analog switches, and the like. The three LSs are don t care (see Figure 4). 3. After acknowledging the instruction byte, the last byte in write mode is the, Frame 3 data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 4). Rev. C Page 3 of 2

14 4. Unlike the write mode, the data byte follows immediately after the acknowledgment of the slave address byte in Frame 2 read mode. Data is transmitted over the serial bus in sequences of nine clock pulses (slightly different from the write mode, there are eight data bits followed by a no acknowledge Logic bit in read mode). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 5). 5. hen all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 4). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, which goes high to establish a stop condition (see Figure 5). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte updates the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output is updated. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. If different instructions are needed, the write mode has to start a completely new sequence with a new slave address, instruction, and data bytes transferred again. Similarly, a repeated read function of the RDAC is also allowed. READACK RDAC VALUE Specific to the AD5242 dual-channel device, the channel of interest is the one that was previously selected in the write mode. In addition, to read both RDAC values consecutively, users have to perform two write-read cycles. For example, users may first specify the RDAC subaddress in write mode (it is not necessary to issue the data byte and stop condition), and then change to read mode to read the RDAC value. To continue reading the RDAC2 value, users have to switch back to write mode, specify the subaddress, and then switch once again to read mode to read the RDAC2 value. It is not necessary to issue the write mode data byte or the first stop condition for this operation. Users should refer to Figure 4 and Figure 5 for the programming format. MULTIPLE DEVICES ON ONE US Figure 33 shows four AD5242 devices on the same serial bus. Each has a different slave address because the state of their AD and AD pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I 2 C-compatible interface. Note, a device is addressed properly only if the bit information of AD and AD in the slave address byte matches with the logic inputs at the AD and AD pins of that particular device. LEVEL-SHIFT FOR IDIRECTIONAL INTERFACE hile most old systems can operate at one voltage, a new component may be optimized at another. hen they operate the same signal at two different voltages, a proper method of level-shifting is needed. For instance, a 3.3 V E 2 PROM can be used to interface with a 5 V digital potentiometer. A level-shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E 2 PROM. Figure 32 shows one of the techniques. M and M2 can be N-channel FETs (2N72) or low threshold FDV3N if VDD falls below 2.5 V. V DD = 3.3V SDA SCL R P 3.3V E 2 PROM R P G S D M G S D M2 R P R P V DD = 5V 5V AD5242 Figure 32. Level-Shift for Different Voltage Devices Operation SDA2 SCL V R P R P MASTER SDA SCL SDA SCL AD V DD SDA SCL AD V DD SDA SCL AD V DD SDA SCL AD AD AD AD AD AD5242 AD5242 AD5242 AD5242 Figure 33. Multiple AD5242 Devices on One us Rev. C Page 4 of 2

15 ADDITIONAL PROGRAMMALE LOGIC OUTPUT The AD524/AD5242 feature additional programmable logic outputs, O and O2, that can be used to drive digital load, analog switches, and logic gates. They can also be used as a self-contained shutdown preset to Logic that is further explained in the Shutdown Function section. O and O2 default to Logic during power-up. The logic states of O and O2 can be programmed in Frame 2 under the write mode (see Figure 4). Figure 34 shows the output stage of O, which employs large P-channel and N- channel MOSFETs in push-pull configuration. As shown in Figure 34, the output is equal to VDD or VSS, and these logic outputs have adequate current driving capability to drive milliamperes of load. IN 2 O DATA IN FRAME 2 OF RITE MODE M P M N V DD V SS O Figure 34. Output Stage of Logic Output, O Users can also activate O and O2 in the following three different ways without affecting the wiper settings:. Start, slave address byte, acknowledge, instruction byte with O and O2 specified, acknowledge, stop. 2. Complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with O and O2 specified, acknowledge, stop. 3. Do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with O and O2 specified, acknowledge, stop. All digital inputs are protected with a series input resistor and the parallel Zener ESD structures shown in Figure 36. This applies to the digital input pins, SDA, SCL, and SHDN SHUTDON FUNCTION Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the write mode instruction byte (see Table 2). If the RDAC Register or RDAC Register 2 (AD5242 only) is placed in shutdown mode by the software, SD bit, the part returns the wiper to its prior position when a new command is received. In addition, shutdown can be implemented with the device digital output, as shown in Figure 35. In this configuration, the device is shutdown during power-up but users are allowed to program the device. Thus, when O is programmed high, the device exits shutdown mode and responds to the new setting. This self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, and it does not add extra components. R PD O SHDN SDA SCL Figure 35. Shutdown by Internal Logic Output, O 34Ω V SS LOGIC Figure 36. ESD Protection of Digital Pins A,, V SS Figure 37. ESD Protection of Resistor Terminals Rev. C Page 5 of 2

16 OUTLINE DIMENSIONS SC 7 PIN SC COPLANARITY.9..2 MAX SEATING PLANE.2.9 COMPLIANT TO JEDEC STANDARDS MO-53-A- Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters A 8.75 (.3445) 8.55 (.3366) 4. (.575) 3.8 (.496) (.244) 5.8 (.2283).25 (.98). (.39) COPLANARITY..27 (.5) SC.5 (.2).3 (.22).75 (.689).35 (.53) SEATING PLANE 8.25 (.98).7 (.67).5 (.97).25 (.98).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow ody (R-4) Dimensions shown in millimeters and (inches) 666-A Rev. C Page 6 of 2

17 SC PIN.65 SC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-A Figure 4. 6-Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters. (.3937) 9.8 (.3858) 4. (.575) 3.8 (.496) (.244) 5.8 (.2283).25 (.98). (.39) COPLANARITY..27 (.5) SC.5 (.2).3 (.22).75 (.689).35 (.53) SEATING PLANE 8.25 (.98).7 (.67).5 (.97).25 (.98).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 6-Lead Standard Small Outline Package [SOIC_N] Narrow ody (R-6) Dimensions shown in millimeters and (inches) 666-A Rev. C Page 7 of 2

18 ORDERING GUIDE Model, 2 No. of Channels End-to-End RA Temperature Range Package Description Package Option AD524R kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524R-REEL7 kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZ kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZ-RL7 kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RU kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RU-REEL7 kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZ kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZ-R7 kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524R kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524R-REEL7 kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZ kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZ-RL7 kω 4 C to +5 C 4-Lead SOIC_N R-4 AD524RU kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RU-REEL7 kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZ kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZ-R7 kω 4 C to +5 C 4-Lead TSSOP RU-4 AD524RM MΩ 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZM MΩ 4 C to +5 C 4-Lead SOIC_N R-4 AD524RZM-REEL MΩ 4 C to +5 C 4-Lead SOIC_N R-4 AD524RUM MΩ 4 C to +5 C 4-Lead SOIC_N R-4 AD524RUM-REEL7 MΩ 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZM MΩ 4 C to +5 C 4-Lead TSSOP RU-4 AD524RUZM-R7 MΩ 4 C to +5 C 4-Lead TSSOP RU-4 AD5242R 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242R-REEL7 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RZ 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RZ-REEL7 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RU 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RU-REEL7 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZ 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZ-RL7 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242R 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242R-REEL7 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RZ 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RZ-REEL7 2 kω 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RU 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RU-REEL7 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZ 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZ-RL7 2 kω 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RM 2 MΩ 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RZM 2 MΩ 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RUM 2 MΩ 4 C to +5 C 6-Lead SOIC_N R-6 AD5242RUM-REEL7 2 MΩ 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZM 2 MΩ 4 C to +5 C 6-Lead TSSOP RU-6 AD5242RUZM-REEL7 2 MΩ 4 C to +5 C 6-Lead TSSOP RU-6 EVAL-AD5242EZ 2 Evaluation oard The AD524/AD5242 die size is 69 mil 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5,495,245 applies. 2 Z = RoHS Compliant Part. Rev. C Page 8 of 2

19 NOTES Rev. C Page 9 of 2

20 NOTES 2 29 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D926--2/9(C) Rev. C Page 2 of 2