AD5272/AD5274. Single-Channel, digipot+ 1% Resistor Tolerance, 1024-/256-Position Digital Variable FEATURES FUNCTIONAL BLOCK DIAGRAM V DD APPLICATIONS

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1 Single-Channel, digipot+ % Resistor Tolerance, 24-/256-Position Digital Variable AD5272/AD5274 FEATURES Single-channel, 24-/256-position resolution 2 kω nominal resistance Maximum ±% nominal resistor tolerance error 5-times programmable (5-TP) wiper memory Rheostat mode temperature coefficient: 5 ppm/ C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operations I 2 C-compatible interface Wiper setting readback Power on refreshed from 5-TP memory Compact MSOP, -lead 3 mm 4. mm. mm package APPLICATIONS Mechanical potentiometer replacements Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5272/AD5274, members of the Analog Devices, Inc., digipot+ family of potentiometers, are single-channel, 24-/ 256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. The AD5272/AD5274 ensure less than % end-to-end resistor tolerance error and offer 5-times programmable (5-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. SCL SDA ADDR RESET FUNCTIONAL BLOCK DIAGRAM V DD POWER-ON RESET I 2 C SERIAL INTERFACE /8 AD5272/AD5274 RDAC REGISTER 5-TP MEMORY BLOCK V SS EXT_CAP GND Figure. The AD5272/AD5274 device wiper settings are controllable through the I 2 C-compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 5-TP memory. The AD5272/AD5274 do not require any external voltage supply to facilitate fuse blow and there are 5 opportunities for permanent programming. During 5-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). The AD5272/AD5274 are available in a compact -lead MSOP. The parts are guaranteed to operate over the extended industrial temperature range of 4 C to +25 C. A W 876- Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 6, Norwood, MA 262-6, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 Electrical Characteristics AD Electrical Characteristics AD Interface Timing Specifications... 6 Absolute Maximum Ratings... 8 Thermal Resistance... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Test Circuits... 4 Theory of Operation... 5 Serial Data Interface... 5 Shift Register... 5 Write Operation... 6 Read Operation... 8 RDAC Register... 5-TP Memory Block... Write Protection... 5-TP Memory Write-Acknowledge Polling... 2 Reset... 2 Resistor Performance Mode... 2 Shutdown Mode... 2 RDAC Architecture... 2 Programming the Variable Resistor... 2 EXT_CAP Capacitor Terminal Voltage Operating Range Power-Up Sequence Outline Dimensions Ordering Guide REVISION HISTORY / Revision : Initial Version Rev. Page 2 of 24

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS AD5272 VDD = 2.7 V to 5.5 V, VSS = V; VDD = 2.5 V to 2.75 V, VSS = 2.5 V to 2.75 V; 4 C < TA < +25 C, unless otherwise noted. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resolution Bits Resistor Integral Nonlinearity 2, 3 R-INL VDD VSS = 3. V to 5.5 V + LSB VDD VSS = 2.7 V to 3. V +.5 LSB Resistor Differential Nonlinearity 2 R-DNL + LSB Nominal Resistor Tolerance R-Perf Mode 4 See Table 2 ±.5 + % Normal Mode ±5 % Resistance Temperature Coefficient 5, 6 Code = full scale 5 ppm/ C Wiper Resistance Code = zero scale 35 7 Ω RESISTOR TERMINALS Terminal Voltage Range 5, 7 VSS VDD V Capacitance 5 A f = MHz, measured to GND, code = half pf scale Capacitance 5 W f = MHz, measured to GND, code = half scale 4 pf Common-Mode Leakage Current 5 VA = VW 5 na DIGITAL INPUTS Input Logic 5 High VINH 2. V Low VINL.8 V Input Current IIN ± μa Input Capacitance 5 CIN 5 pf DIGITAL OUTPUT Output Voltage 5 High VOH RPULL_UP = 2.2 kω to VDD VDD. V Low VOL RPULL_UP = 2.2 kω to VDD VDD = 2.7 V to 5.5 V, VSS = V.4 V VDD = 2.5 V to 2.75 V, VSS = 2.5 V to 2.75 V.6 V Tristate Leakage Current + μa Output Capacitance 5 5 pf POWER SUPPLIES Single-Supply Power Range VSS = V V Dual-Supply Power Range ±2.5 ±2.75 V Supply Current Positive IDD μa Negative ISS μa OTP Store Current 5, 8 Positive IDD_OTP_STORE 4 ma Negative ISS_OTP_STORE 4 ma Rev. Page 3 of 24

4 Parameter Symbol Test Conditions/Comments Min Typ Max Unit OTP Read Current 5, Positive IDD_OTP_READ 5 μa Negative ISS_OTP_READ 5 μa Power Dissipation VIH = VDD or VIL = GND 5.5 μw Power Supply Rejection Ratio 5 PSRR ΔVDD/ΔVSS = ±5 V ± % db 5, DYNAMIC CHARACTERISTICS Bandwidth 3 db, RAW = kω, Terminal W, see Figure 27 3 khz Total Harmonic Distortion VA = V rms, f = khz, RAW = kω db Resistor Noise Density RWB = kω, TA = 25 C, f = khz 5 nv/ Hz Typical specifications represent average readings at 25 C, VDD = 5 V, and VSS = V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD )/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 4 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. Different from operating current, the supply current for the fuse read lasts approximately 5 ns. PDISS is calculated from (IDD VDD) + (ISS VSS). All dynamic characteristics use VDD = +2.5 V, VSS = 2.5 V. Table 2. AD5272 Resistor Performance Mode Code Range Resistor Tolerance Per Code VDD VSS = 4.5 V to 5.5 V VDD VSS = 2.7 V to 4.5 V R-TOLERANCE % R-TOLERANCE From x78 to x3ff From xbe to x3ff 2% R-TOLERANCE From x37 to x3ff From x55 to x3ff 3% R-TOLERANCE From x28 to x3ff From x37 to x3ff Rev. Page 4 of 24

5 ELECTRICAL CHARACTERISTICS AD5274 VDD = 2.7 V to 5.5 V, VSS = V; VDD = 2.5 V to 2.75 V, VSS = 2.5 V to 2.75 V; 4 C < TA < +25 C, unless otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resolution 8 Bits Resistor Integral Nonlinearity 2, 3 R-INL + LSB Resistor Differential R-DNL + LSB Nonlinearity 2 Nominal Resistor Tolerance R-Perf Mode 4 See Table 4 ±.5 + % Normal Mode ±5 % Resistance Temperature Code = full scale 5 ppm/ C Coefficient 5, 6 Wiper Resistance Code = zero scale 35 7 Ω RESISTOR TERMINALS Terminal Voltage Range 5, 7 VSS VDD V Capacitance 5 A f = MHz, measured to GND, code = half scale pf Capacitance 5 W f = MHz, measured to GND, code = half scale 4 pf Common-Mode Leakage VA = VW na Current 5 DIGITAL INPUTS Input Logic 5 High VINH 2. V Low VINL.8 V Input Current IIN ± μa Input Capacitance 5 CIN 5 pf DIGITAL OUTPUT Output Voltage 5 High VOH RPULL_UP = 2.2 kω to VDD VDD. V Low VOL RPULL_UP = 2.2 kω to VDD VDD = 2.7 V to 5.5 V, VSS = V.4 V VDD = 2.5 V to 2.75 V, VSS = 2.5 V to 2.75 V.6 V Tristate Leakage Current + μa Output Capacitance 5 5 pf POWER SUPPLIES Single-Supply Power Range VSS = V V Dual-Supply Power Range ±2.5 ±2.75 V Supply Current Positive IDD μa Negative ISS μa OTP Store Current 5, 8 Positive IDD_OTP_STORE 4 ma Negative ISS_OTP_STORE 4 ma OTP Read Current 5, Positive IDD_OTP_READ 5 μa Negative ISS_OTP_READ 5 μa Power Dissipation VIH = VDD or VIL = GND 5.5 μw Power Supply Rejection Ratio 5 PSRR ΔVDD/ΔVSS = ±5 V ± % db Rev. Page 5 of 24

6 Parameter Symbol Test Conditions/Comments Min Typ Max Unit 5, DYNAMIC CHARACTERISTICS Bandwidth 3 db, RAW = kω, Terminal W, see Figure 27 3 khz Total Harmonic Distortion VA = V rms, f = khz, RAW = kω db Resistor Noise Density RWB = kω, TA = 25 C, f = khz 5 nv/ Hz Typical specifications represent average readings at 25 C, VDD = 5 V, and VSS = V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD )/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 4 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. Different from operating current, the supply current for the fuse read lasts approximately 5 ns. PDISS is calculated from (IDD VDD) + (ISS VSS). All dynamic characteristics use VDD = +2.5 V, VSS = 2.5 V. Table 4. AD5274 Resistor Performance Mode Code Range Resistor Tolerance per Code VDD VSS = 4.5 V to 5.5 V VDD VSS = 2.7 V to 4.5 V R-TOLERANCE % R-Tolerance From xe to xff From x32 to xff 2% R-Tolerance From xf to xff From x to xff 3% R-Tolerance From x6 to xff From xe to xff INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description fscl 2 Standard mode khz Serial clock frequency Fast mode 4 khz Serial clock frequency t Standard mode 4 μs thigh, SCL high time Fast mode.6 μs thigh, SCL high time t2 Standard mode 4.7 μs tlow, SCL low time Fast mode.3 μs tlow, SCL low time t3 Standard mode 25 ns tsu;dat, data setup time Fast mode ns tsu;dat, data setup time t4 Standard mode 3.45 μs thd;dat, data hold time Fast mode. μs thd;dat, data hold time t5 Standard mode 4.7 μs tsu;sta, set-up time for a repeated start condition Fast mode.6 μs tsu;sta, set-up time for a repeated start condition t6 Standard mode 4 μs thd;sta, hold time (repeated) start condition Fast mode.6 μs thd;sta, hold time (repeated) start condition High speed mode 6 ns thd;sta, hold time (repeated) start condition t7 Standard mode 4.7 μs tbuf, bus free time between a stop and a start condition Fast mode.3 μs tbuf, bus free time between a stop and a start condition t8 Standard mode 4 μs tsu;sto, setup time for a stop condition Fast mode.6 μs tsu;sto, setup time for a stop condition t Standard mode ns trda, rise time of SDA signal Fast mode 3 ns trda, rise time of SDA signal Rev. Page 6 of 24

7 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description t Standard mode 3 ns tfda, fall time of SDA signal Fast mode 3 ns tfda, fall time of SDA signal t Standard mode ns trcl, rise time of SCL signal Fast mode 3 ns trcl, rise time of SCL signal ta Standard mode ns trcl, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 3 ns trcl, rise time of SCL signal after a repeated start condition and after an acknowledge bit t2 Standard mode 3 ns tfcl, fall time of SCL signal Fast mode 3 ns tfcl, fall time of SCL signal t3 RESET pulse time 2 ns Minimum RESET low time tsp 3 Fast mode 5 ns Pulse width of spike suppressed texec 4, 5 5 ns Command execute time trdac_r-perf 2 μs RDAC register write command execute time (R-Perf mode) trdac_normal 6 ns RDAC register write command execute time (normal mode) tmemory_read 6 μs Memory readback execute time tmemory_program 35 ms Memory program time treset 6 μs Reset OTP restore time t 6 POWER-UP 2 ms Power-on OTP restore time Maximum bus capacitance is limited to 4 pf. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 5 ns for fast mode. 4 Refer to trdac_r-perf and trdac_normal for RDAC register write operations. 5 Refer to t MEMORY_READ and t MEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD VSS is equal to 2.5 V. Shift Register and Timing Diagrams DB (MSB) DB (LSB) C3 C2 C C D D8 D7 D6 D5 D4 D3 D2 D D CONTROL BITS Figure 2. Shift Register Content DATA BITS t t 2 t 6 t 8 SCL t 2 t 6 t 4 t t 3 t 5 t t SDA t 7 P S S P t 3 RESET Figure 3. 2-Wire Serial Interface Timing Diagram Rev. Page 7 of 24

8 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 6. Parameter Rating VDD to GND.3 V to +7. V VSS to GND +.3 V to 7. V VDD to VSS 7 V VA, VW to GND VSS.3 V, VDD +.3 V Digital Input and Output Voltage to GND.3 V to VDD +.3 V EXT_CAP to VSS 7 V IA, IW Pulsed Frequency > khz ±3 ma/d 2 Frequency khz ±3 ma/ d 2 Continuous ±3 ma Operating Temperature Range 3 4 C to +25 C Maximum Junction Temperature 5 C (TJ Maximum) Storage Temperature Range 65 C to +5 C Reflow Soldering Peak Temperature 26 C Time at Peak Temperature 2 sec to 4 sec Package Power Dissipation (TJ max TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is defined by JEDEC specification JESD-5 and the value is dependent on the test board and test environment. Table 7. Thermal Resistance Package Type θja θjc Unit -Lead MSOP 35 N/A C/W JEDEC 2S2P test board, still air ( m/s air flow). ESD CAUTION Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of OTP memory. Rev. Page 8 of 24

9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions V DD A W V SS EXT_CAP AD5272/ AD5274 TOP VIEW (Not to Scale) ADDR 8 7 SCL SDA RESET 6 GND Figure 4. Pin Configuration Pin No. Mnemonic Description VDD Positive Power Supply. Decouple this pin with. μf ceramic capacitors and μf capacitors. 2 A Terminal A of RDAC. VSS VA VDD. 3 W Wiper terminal of RDAC. VSS VW VDD. 4 VSS Negative Supply. Connect to V for single-supply applications. Decouple this pin with. μf ceramic capacitors and μf capacitors. 5 EXT_CAP External Capacitor. Connect a μf capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of 7 V. 6 GND Ground Pin, Logic Ground Reference. 7 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 5-TP memory register. Factory default loads midscale until the first 5-TP wiper memory location is programmed. RESET is active low. Tie RESET to VDD if not used. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 6-bit input registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 6-bit input registers. ADDR Tristate Address Input. Sets the two least significant bits (Bit A, Bit A) of the 7-bit slave address (see Table ) Rev. Page of 24

10 TYPICAL PERFORMANCE CHARACTERISTICS C +25 C 4 C INL (LSB).2 DNL (LSB) CODE (Decimal) Figure 5. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5272) C +25 C 4 C CODE (Decimal) Figure 8. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5272) C +25 C 4 C C +25 C 4 C.3.5 INL (LSB).2 DNL (LSB) CODE (Decimal) Figure 6. R-INL in Normal Mode vs. Code vs. Temperature (AD5272) CODE (Decimal) Figure. R-DNL in Normal Mode vs. Code vs. Temperature (AD5272) C +25 C 4 C C +25 C 4 C INL (LSB)..5 DNL (LSB) CODE (Decimal) Figure 7. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5274) CODE (Decimal) Figure. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5274) Rev. Page of 24

11 INL (LSB) C +25 C 4 C RHEOSTAT MODE TEMPCO (ppm/ C) V DD /V SS = 5V/V CODE (Decimal) Figure. R-INL in Normal Mode vs. Code vs. Temperature (AD5274) CODE (Decimal) Figure 4. Tempco ΔRWA/ΔT vs. Code AD5272 AD CURRENT (na) 5 4 I DD = 5V 3 2 I DD = 3V I SS = 3V 2 I SS = 5V TEMPERATURE ( C) THEORETICAL I WA_MAX (ma) V DD /V SS = 5V/V CODE (Decimal) AD5272 AD Figure 2. Supply Current (IDD, ISS) vs. Temperature Figure 5. Theoretical Maximum Current vs. Code C +25 C 4 C x2 (x8) x (x4) AD5272 (AD5274) x8 (x2). 2 x4 (x) DNL (LSB)..2 GAIN (db) x2 (x8) x (x4) x8 (x2) x4 (x) x2 x CODE (Decimal) Figure 3. R-DNL in Normal Mode vs. Code vs. Temperature (AD5274) k k k M M FREQUENCY (Hz) Figure 6. Bandwidth vs. Code vs. Frequency Rev. Page of 24

12 V DD /V SS = 5V/V CODE = HALF SCALE V IN = V rms V DD /V SS = 5V/V CODE = HALF SCALE THD + N (db) PSRR (db) k k k FREQUENCY (Hz) Figure 7. THD + N vs. Frequency k k k M FREQUENCY (Hz) Figure. PSRR vs. Frequency V DD /V SS = 5V/V 35 3 V DD /V SS = 5V/V CODE = HALF SCALE f IN = khz NUMBER OF CODES (AD5274) NUMBER OF CODES (AD5272) THD + N (db) TEMPERATURE ( C) VOLTAGE (V P ) Figure 8. Maximum Code Loss vs. Temperature Figure 2. THD + N vs. Amplitude Rev. Page 2 of 24

13 8.75 T A = 25 C 7.5 I AW = 2µA NUMBER OF CODES (AD5274) NUMBER OF CODES (AD5272) VOLTAGE (V) V DD (V) TIME (µs) Figure 2. Maximum Code Loss vs. Power Supply Range Figure 23. Maximum Glitch Energy 8 7 VOLTAGE (V) TIME (Seconds) Figure 22. VEXT_CAP Waveform While Writing Fuse Rev. Page 3 of 24

14 TEST CIRCUITS Figure 24 to Figure 28 define the test conditions used in the Specifications section DUT A W V MS Figure 24. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) I W DUT W GΩ A V V MS Figure 27. Gain vs. Frequency DUT A CODE = x W V MS I W R WA = V MS I W R W = R WA 2 Figure 25. Wiper Resistance DUT GND I CM W +2.75V 2.75V A GND NC GND NC = NO CONNECT +2.75V 2.75V Figure 28. Common Leakage Current V+ = V DD ±% V+ V DD A W I W PSRR (db) = 2 log ΔV MS % PSS (%/%) = ΔV DD % V MS V DD V MS Figure 26. Power Supply Sensitivity (PSS, PSRR) Rev. Page 4 of 24

15 THEORY OF OPERATION The AD5272 and AD5274, members of the Analog Devices, Inc., digipot+ family of potentiometers, are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I 2 C interface. When a desirable wiper position is found, this value can be stored in a 5-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of 5-TP data takes approximately 35 ms; during this time, the AD5272/AD5274 is locked and does not acknowledge any new command thereby preventing any changes from taking place. The acknowledge bit can be polled to verify that the fuse program command is complete. The AD5272/AD5274 also feature a patented % end-to-end resistor tolerance. This simplifies precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. SERIAL DATA INTERFACE The AD5272/AD5274 have 2-wire I 2 C-compatible serial interfaces. Each of these devices can be connected to an I 2 C bus as a slave device under the control of a master device; see Figure 3 for a timing diagram of a typical write sequence. The AD5272/AD5274 support standard ( khz) and fast (4 khz) data transfer modes. Support is not provided for -bit addressing and general call addressing. The AD5272/AD5274 each has a 7-bit slave address. The five MSBs are and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table. The 2-wire serial bus protocol operates as follows: The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The next byte is the address byte, which consists of the 7-bit slave address and a R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the th clock pulse, and then high during the th clock pulse to establish a stop condition. SHIFT REGISTER For the AD5272/AD5274, the shift register is 6 bits wide, as shown in Figure 2. The 6-bit word consists of two unused bits, which should be set to zero, followed by four control bits and RDAC data bits (note that for the AD5274 only, the lower two RDAC data bits are don t care if the RDAC register is read from or written to), and data is loaded MSB first (Bit 5). The four control bits determine the function of the software command (Table ). Figure 2 shows a timing diagram of a typical AD5272/ AD5274 write sequence. The command bits (Cx) control the operation of the digital potentiometer and the internal 5-TP memory. The data bits (Dx) are the values that are loaded into the decoded register. Table. Device Address Selection ADDR A A 7-Bit I 2 C Device Address GND VDD NC (No Connection) Not available in bipolar mode. VSS < V. Rev. Page 5 of 24

16 WRITE OPERATION It is possible to write data for the RDAC register or the control register. When writing to the AD5272/AD5274, the user must begin with a start command followed by an address byte (R/W = ), after which the AD5272/AD5274 acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5272/AD5274. A stop condition follows. The write operations for the AD5272/ AD5274 are shown in Figure 2. A repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in Figure 3. SCL SDA START BY MASTER A A C3 C2 C C D D8 FRAME SERIAL BUS ADDRESS BYTE R/W ACKNOWLEDGED BY AD52722/AD5274 ACKNOWLEDGED BY AD52722/AD5274 FRAME 2 MOST SIGNIFICANT DATA BYTE SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D D FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 2. Write Command ACK. BY AD5272 STOP BY MASTER Rev. Page 6 of 24

17 SCL SDA START BY MASTER A A R/W C3 C2 C C D D8 FRAME SERIAL BUS ADDRESS BYTE SCL (CONTINUED) ACK. BY AD5272/AD5274 FRAME 2 MOST SIGNIFICANT DATA BYTE ACK. BY AD5272/AD5274 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D D FRAME 3 LEAST SIGNIFICANT DATA BYTE ACK. BY AD5272/AD5274 SCL (CONTINUED) SDA (CONTINUED) C3 C2 C C D D8 FRAME 4 MOST SIGNIFICANT DATA BYTE ACK. BY AD5272/AD5274 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D D Figure 3. Multiple Write FRAME 5 LEAST SIGNIFICANT DATA BYTE ACK. BY AD5272/AD5274 STOP BY MASTER Rev. Page 7 of 24

18 READ OPERATION When reading data back from the AD5272/AD5274, the user must first issue a readback command to the device, this begins with a start command followed by an address byte (R/W = ), after which the AD5272/AD5274 acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the AD5272/AD5274, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5272/AD5274. A stop condition follows. These bytes contain the read instruction, which enables readback of the RDAC register, 5-TP memory, or the control register. The user can then read back the data beginning with a start command followed by an address byte (R/W = ), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, as shown in Figure 3. A stop condition follows. If the master does not acknowledge the first byte, the second byte is not transmitted by the AD5272/AD5274. SCL SDA START BY MASTER A A R/W C3 C2 C C D D8 FRAME SERIAL BUS ADDRESS BYTE SCL (CONTINUED) ACK. BY AD5272/4 FRAME 2 MOST SIGNIFICANT DATA BYTE ACK. BY AD5272/4 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D D FRAME 3 LEAST SIGNIFICANT DATA BYTE ACK. BY AD5272/4 STOP BY MASTER SCL SDA START BY MASTER A A R/W X X X X D D8 FRAME SERIAL BUS ADDRESS BYTE SCL (CONTINUED) ACK. BY AD5272/4 FRAME 2 MOST SIGNIFICANT DATA BYTE ACK. BY MASTER SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D D FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 3. Read Command NO ACK BY MASTER STOP BY MASTER Rev. Page 8 of 24

19 RDAC REGISTER The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal A of the variable resistor. It is possible to both write to and read from the RDAC register using the I 2 C interface. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. 5-TP MEMORY BLOCK The AD5272/AD5274 contain an array of 5-TP programmable memory registers, which allow the wiper position to be programmed up to 5 times. Table 4 shows the memory map. Command 3 in Table programs the contents of the RDAC register to memory. The first address to be programmed is Location x, see Table 4, and the AD5272/AD5274 increments the 5-TP memory address for each subsequent program until the memory is full. Programming data to 5-TP consumes approximately 4 ma for 55 ms, and takes approximately 35 ms to complete, during which time the shift register is locked preventing any changes from taking place. Bit C3 of the control register in Table 3 can be polled to verify that the fuse program command was successful. No change in supply voltage is required to program the 5-TP memory; however, a μf capacitor on the EXT_CAP pin is required as shown in Figure 33. Prior to 5-TP activation, the AD5272/AD5274 preset to midscale on power-up. It is possible to read back the contents of any of the 5-TP memory registers through the I 2 C interface by using Command 5 in Table. The lower six LSB bits, D to D5 of the data byte, select which memory location is to be read back. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 in Table. This can be used to monitor the spare memory status of the 5-TP memory block. WRITE PROTECTION On power-up, serial data input register write commands for both the RDAC register and the 5-TP memory registers are disabled. The RDAC write protect bit (Bit C) of the control register (see Table 2 and Table 3), is set to by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 5-TP memory using the software reset, Command 4, or through hardware by the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit (Bit C) of the control register must first be programmed. This is accomplished by loading the serial data input register with Command 7 (see Table ). To enable programming of the 5-TP memory block, Bit C of the control register, which is set to by default, must first be set to. Table. Command Operation Truth Table Command Command[DB3:DB] Data[DB:B] Number C3 C2 C C D D8 D7 D6 D5 D4 D3 D2 D D Operation X X X X X X X X X X NOP: do nothing. D D8 D7 D6 D5 D4 D3 D2 D 2 D 2 Write contents of serial register data to RDAC. 2 X X X X X X X X X X Read contents of RDAC wiper register. 3 X X X X X X X X X X Store wiper setting: store RDAC setting to 5-TP. 4 X X X X X X X X X X Software reset: refresh RDAC with the last 5-TP memory stored value. 5 3 X X X X D5 D4 D3 D2 D D Read contents of 5-TP from the SDO output in the next frame. 6 X X X X X X X X X X Read address of the last 5-TP programmed memory location. 7 4 X X X X X X X D2 D D Write contents of the serial register data to the control register. 8 X X X X X X X X X X Read contents of the control register. X X X X X X X X X D Software shutdown. D = ; normal mode. D = ; shutdown mode. X = don t care. 2 AD5274 = don t care. 3 See Table 4 for the OTP memory map. 4 See Table 3 for bit details. Rev. Page of 24

20 Table. Write and Read to RDAC and 5-TP memory DIN SDO Action xc3 xxxxx Enable update of wiper position and 5-TP memory contents through digital interface. x5 xc3 Write x to the RDAC register, wiper moves to ¼ full-scale position. x8 x5 Prepare data read from RDAC register. xc x Stores RDAC register content into 5-TP memory. 6-bit word appears out of SDO, where last -bits contain the contents of the RDAC Register x. x8 xc Prepare data read of last programmed 5-TP memory monitor location. x xxx NOP Instruction sends a 6-bit word out of SDO, where the six LSBs last 6-bits contain the binary address of the last programmed 5-TP memory location, for example, x (see Table 4). x4 x Prepares data read from Memory Location x. x2 x Prepare data read from the control register. Sends a 6-bit word out of SDO, where the last -bits contain the contents of Memory Location x. x xxxxx NOP Instruction sends a 6-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 =, fuse program command successful. X is don t care. Table 2. Control Register Bit Map DB DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C3 C2 C C Table 3. Control Register Description Bit Name C C C2 C3 Description 5-TP program enable = 5-TP program disabled (default) = enable device for 5-TP program RDAC register write protect = wiper position frozen to value in OTP memory (default) = allow update of wiper position through a digital interface Resistor performance enable = RDAC resistor tolerance calibration enabled (default) = RDAC resistor tolerance calibration disabled 5-TP memory program success bit = fuse program command unsuccessful (default) = fuse program command successful Wiper position is frozen to the last value programmed in the 5-TP memory. Wiper freezes to midscale if 5-TP memory has not been previously programmed. Table 4. Memory Map Command Number Data Byte [DB:DB8] D D8 D7 D6 D5 D4 D3 D2 D D 5 X X X Reserved X is don t care. Register Contents X X X st programmed wiper location (x) X X X 2nd programmed wiper location (x2) X X X 3rd programmed wiper location (x3) X X X 4th programmed wiper location (x4) X X X th programmed wiper location (xa) X X X 2th programmed wiper location (x4) X X X 3th programmed wiper location (xe) X X X 4th programmed wiper location (x28) X X X 5th programmed wiper location (x32) Rev. Page 2 of 24

21 5-TP MEMORY WRITE-ACKNOWLEDGE POLLING After each write operation to the 5-TP registers, an internal write cycle begins. The I 2 C interface of the device is disabled. To determine if the internal write cycle is complete and the I 2 C interface is enabled, interface polling can be executed. I 2 C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I 2 C interface responds with an acknowledge (ACK), the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, I 2 C interface polling can be repeated until it completes. RESET The AD5272/AD5274 can be reset through software by executing Command 4 (see Table ) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the most recently programmed 5-TP memory location. The RDAC register loads with midscale if no 5-TP memory location has been previously programmed. Tie RESET to VDD if the RESET pin is not used. RESISTOR PERFORMANCE MODE This mode activates a new, patented % end-to-end resistor tolerance that ensures a ±% resistor tolerance on each code, that is, code = half scale and RWA = kω ± Ω. See Table 2 and Table 4 to check which codes achieve ±% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 2 and Table 3). SHUTDOWN MODE The AD5272/AD5274 can be shut down by executing the software shutdown command, Command (see Table ), and setting the LSB to. This feature places the RDAC in a zeropower-consumption state where Terminal Ax is disconnected from the wiper terminal. It is possible to execute any command from Table while the AD5272 or AD5274 is in shutdown mode. The part can be taken out of shutdown mode by executing Command and setting the LSB to, or by issuing a software or hardware reset. RDAC ARCHITECTURE To achieve optimum performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5272/AD5274 employ a three-stage segmentation approach, as shown in Figure 32. The AD5272/AD5274 wiper switch is designed with the transmission gate CMOS topology. 8/-BIT ADDRESS DECODER A R L R L R M R M R W R W Figure 32. Simplified RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation % Resistor Tolerance The nominal resistance between Terminal W and Terminal A, RWA, is available in 2 kω and has 24-/256-tap points accessed by the wiper terminal. The -/8-bit data in the RDAC latch is decoded to select one of the 24 or 256 possible wiper settings. The AD5272/ AD5274 contain an internal ±% resistor tolerance calibration feature which can be disabled or enabled, enabled by default, or by programming Bit C2 of the control register (see Table 3). The digitally programmed output resistance between the W terminal and the A terminal, RWA, is calibrated to give a maximum of ±% absolute resistance error over both the full supply and temperature ranges. As a result, the general equations for determining the digitally programmed output resistance between the W terminal and A terminal are as follows: For the AD5272 D R WA( D) = R WA () 24 For the AD5274 D R WA( D) = R WA (2) 256 where: D is the decimal equivalent of the binary code loaded in the -/8-bit RDAC register. RWA is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 2 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between the A terminal to B terminal, W terminal to A terminal, and W terminal to B terminal, to the maximum continuous current of ±3 ma, or the pulse current specified in Table 6. Otherwise, degradation or possible destruction of the internal switch contact can occur. S W W Rev. Page 2 of 24

22 EXT_CAP CAPACITOR A μf capacitor to VSS must be connected to the EXT_CAP pin (see Figure 33) on power-up and throughout the operation of the AD5272/AD5274. EXT_CAP C µf AD5272/ AD5274 5_OTP MEMORY BLOCK V SS V SS Figure 33. EXT_CAP Hardware Setup TERMINAL VOLTAGE OPERATING RANGE The positive VDD and negative VSS power supplies of the AD5272/AD5274 define the boundary conditions for proper 2-terminal digital resistor operation. Supply signals present on Terminal A and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 34) V DD The ground pins of the AD5272/AD5274 devices are primarily used as digital ground references. To minimize the digital ground bounce, join the AD5272/AD5274 ground terminal remotely to the common ground. The digital input control signals to the AD5272/AD5274 must be referenced to the device ground pin (GND) and satisfy the logic level defined in the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 34), it is important to power VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS are powered unintentionally. The ideal power-up sequence is VSS, GND, VDD, digital inputs, VA, and VW. The order of powering VA, VW, and digital inputs is not important as long as they are powered after VDD/VSS. As soon as VDD is powered, the power-on preset activates, which first sets the RDAC to midscale and then restores the last programmed 5-TP value to the RDAC register. A W V SS 876- Figure 34. Maximum Terminal Voltages Set by VDD and VSS Rev. Page 22 of 24

23 OUTLINE DIMENSIONS PIN IDENTIFIER.5 BSC COPLANARITY MAX 6 5 MAX.23.3 COMPLIANT TO JEDEC STANDARDS MO-87-BA Figure 35. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters ORDERING GUIDE Model RAB (kω) Resolution Temperature Range Package Description Package Option Branding AD5272BRMZ2 2,24 4 C to +25 C -Lead MSOP RM- DE6 AD5272BRMZ2-RL7 2,24 4 C to +25 C -Lead MSOP RM- DE6 AD5274BRMZ C to +25 C -Lead MSOP RM- DEE AD5274BRMZ2-RL C to +25 C -Lead MSOP RM- DEE Z = RoHS Compliant Part A Rev. Page 23 of 24

24 NOTES 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D876--/() Rev. Page 24 of 24