1-/2-/4-Channel Digital Potentiometers AD8400/AD8402/AD8403

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1 a FEATURES 256-Position Replaces, 2, or 4 Potentiometers k, k, 5 k, k Power Shutdown Less than 5 A 3-Wire SPI-Compatible Serial Data Input MHz Update Data Loading Rate 2.7 V to 5.5 V Single-Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Programmable Filters, Delays, Time Constants Volume Control, Panning Line Impedance Matching Power Supply Adjustment V DD DGND SDI CLK -/2-/4-Channel Digital Potentiometers AD4/AD42/AD43 FUNCTIONAL LOCK DIAGRAM AD43 DAC SELECT 2 D A, A 2 -IT SERIAL 3 4 CK Q RS -IT CK RS -IT CK RS -IT CK RS -IT CK RS RDAC SHDN RDAC2 SHDN RDAC3 SHDN RDAC4 SHDN A W AGND A2 W2 2 AGND2 A3 W3 3 AGND3 A4 W4 4 AGND4 GENERAL DESCRIPTION The AD4/AD42/AD43 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD4 contains a single variable resistor in the compact SO- package. The AD42 contains two independent variable resistors in space-saving SO-4 surfacemount packages. The AD43 contains four independent variable resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the terminal and the wiper. The fixed A to terminal resistance of kω, kω, 5 kω, or kω has a ±% channel-to-channel matching tolerance with a nominal temperature coefficient of 5 ppm/ C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation. Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serialto-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading H into the VR latch. The SHDN pin forces the resistor Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. SDO SHDN to an end-to-end open circuit condition on the A terminal and shorts the wiper to the terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. The AD4 is available in both the SO- surface-mount and the -lead plastic DIP package. The AD42 is available in both surface mount (SO-4) and 4-lead plastic DIP packages, while the AD43 is available in a narrow body 24-lead plastic DIP and a 24-lead surface-mount package. The AD42/AD43 are also offered in the. mm thin TSSOP-4/TSSOP-24 packages for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of 4 C to +25 C. R WA (D), R W (D) % of Nominal R A R WA CODE Decimal One Technology Way, P.O. ox 96, Norwood, MA , U.S.A. Tel: 7/ Fax: 7/ Analog Devices, Inc., 22 RS R W Figure. RWA and RW vs. Code

2 AD4/AD42/AD43 SPECIFICATIONS (V DD = 3 V % or 5 V %, V A = V DD, V = V, 4 C T A +25 C unless otherwise noted.) ELECTRICAL CHARACTERISTI k VERSION Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTI RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL 2 R-DNL R W, V A = No Connect ± /4 + LS Resistor Nonlinearity 2 R-INL R W, V A = No Connect 2 ± /2 +2 LS Nominal Resistance 3 R A T A = 25 C, Model: AD4XYY 2 kω Resistance Tempco R A / T V A = V DD, Wiper = No Connect 5 ppm/ C Wiper Resistance R W I W = V/R 5 Ω Nominal Resistance Match R/R A CH to 2, 3, or 4, V A = V DD, T A = 25 C.2 % DC CHARACTERISTI POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N its Integral Nonlinearity 4 INL 2 ± /2 +2 LS Differential Nonlinearity 4 DNL V DD = 5 V ± /4 + LS DNL V DD = 3 V T A = 25 C ± /4 + LS DNL V DD = 3 V T A = 4 C, +5 C.5 ± /2 +.5 LS Voltage Divider Tempco V W / T Code = H 5 ppm/ C Full-Scale Error V WFSE Code = FF H 4 2. LS Zero-Scale Error V WZSE Code = H.3 2 LS RESISTOR TERMINALS Voltage Range 5 V A,, W V DD V Capacitance 6 Ax, x C A, f = MHz, Measured to GND, Code = H 75 pf Capacitance 6 Wx C W f = MHz, Measured to GND, Code = H 2 pf Shutdown Current 7 I A_SD V A = V DD, V = V, SHDN =. 5 µa Shutdown Wiper Resistance R W_SD V A = V DD, V = V, SHDN =, V DD = 5 V 2 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V IH V DD = 5 V 2.4 V Input Logic Low V IL V DD = 5 V. V Input Logic High V IH V DD = 3 V 2. V Input Logic Low V IL V DD = 3 V.6 V Output Logic High V OH R L = 2.2 kω to V DD V DD. V Output Logic Low V OL I OL =.6 ma, V DD = 5 V.4 V Input Current I IL V IN = V or +5 V, V DD = 5 V ± µa Input Capacitance 6 C IL 5 pf POWER SUPPLIES Power Supply Range V DD Range V Supply Current (CMOS) I DD V IH = V DD or V IL = V. 5 µa Supply Current (TTL) I DD V IH = 2.4 V or. V, V DD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 P DISS V IH = V DD or V IL = V, V DD = 5.5 V 27.5 µw Power Supply Sensitivity PSS V DD = 5 V ± %.2. %/% PSS V DD = 3 V ± %.6.3 %/% 6, DYNAMIC CHARACTERISTI andwidth 3 d W_K R = kω 6 khz Total Harmonic Distortion THD W V A = V rms + 2 V dc, V = 2 V dc, f = khz.3 % V W Settling Time t S V A = V DD, V = V, ±% Error and 2 µs Resistor Noise Voltage e NW R W = 5 kω, f = khz, RS = 9 nv/ Hz Crosstalk C T V A = V DD, V = V 65 d NOTES Typicals represent average readings at 25 C and V DD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit. I W = 5 µa for V DD = 3 V and I W = 4 µa for V DD = 5 V for the kω versions. 3 V A = V DD, Wiper (V W ) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V = V. DNL Specification limits of ± LS maximum are Guaranteed Monotonic operating conditions. See TPC 2 test circuit. 5 Resistor terminals A,, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 2 for a plot of I DD versus logic voltage. 9 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. All Dynamic Characteristics use V DD = 5 V. Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. 2

3 3 AD4/AD42/AD43 SPECIFICATIONS (V DD = 3 V % or 5 V %, V A = V DD, V = V, 4 C T A +25 C unless otherwise noted.) ELECTRICAL CHARACTERISTI 5 k and k VERSIONS Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTI RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL 2 R-DNL R W, V A = No Connect ± /4 + LS Resistor Nonlinearity 2 R-INL R W, V A = No Connect 2 ± /2 +2 LS Nominal Resistance 3 R A T A = 25 C, Model: AD4XYY kω R A T A = 25 C, Model: AD4XYY 7 3 kω Resistance Tempco R A / T V A = V DD, Wiper = No Connect 5 ppm/ C Wiper Resistance R W I W = V/R 53 Ω Nominal Resistance Match R/R A CH to 2, 3, or 4, V A = V DD, T A = 25 C.2 % DC CHARACTERISTI POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N its Integral Nonlinearity 4 INL 4 ± +4 LS Differential Nonlinearity 4 DNL V DD = 5 V ± /4 + LS DNL V DD = 3 V T A = 25 C ± /4 + LS DNL V DD = 3 V T A = 4 C, +5 C.5 ± /2 +.5 LS Voltage Divider Tempco V W / T Code = H 5 ppm/ C Full-Scale Error V WFSE Code = FF H.25 LS Zero-Scale Error V WZSE Code = H +. + LS RESISTOR TERMINALS Voltage Range 5 V A,, W V DD V Capacitance 6 Ax, x C A, f = MHz, Measured to GND, Code = H 5 pf Capacitance 6 Wx C W f = MHz, Measured to GND, Code = H pf Shutdown Current 7 I A_SD V A = V DD, V = V, SHDN =. 5 µa Shutdown Wiper Resistance R W_SD V A = V DD, V = V, SHDN =, V DD = 5 V 2 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V IH V DD = 5 V 2.4 V Input Logic Low V IL V DD = 5 V. V Input Logic High V IH V DD = 3 V 2. V Input Logic Low V IL V DD = 3 V.6 V Output Logic High V OH R L = 2.2 kω to V DD V DD. V Output Logic Low V OL I OL =.6 ma, V DD = 5 V.4 V Input Current I IL V IN = V or 5 V, V DD = 5 V ± µa Input Capacitance 6 C IL 5 pf POWER SUPPLIES Power Supply Range V DD Range V Supply Current (CMOS) I DD V IH = V DD or V IL = V. 5 µa Supply Current (TTL) I DD V IH = 2.4 V or. V, V DD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 P DISS V IH = V DD or V IL = V, V DD = 5.5 V 27.5 µw Power Supply Sensitivity PSS V DD = 5 V ± %.2. %/% PSS V DD = 3 V ± %.6.3 %/% 6, DYNAMIC CHARACTERISTI andwidth 3 d W_5K R = 5 kω 25 khz W_K R = kω 7 khz Total Harmonic Distortion THD W V A = V rms + 2 V dc, V = 2 V dc, f = khz.3 % V W Settling Time t S _5K V A = V DD, V = V, ±% Error and 9 µs t S _K V A = V DD, V = V, ±% Error and µs Resistor Noise Voltage e NW _5K R W = 25 kω, f = khz, RS = 2 nv/ Hz e NW _K R W = 5 kω, f = khz, RS = 29 nv/ Hz Crosstalk C T V A = V DD, V = V 65 d NOTES Typicals represent average readings at 25 C and V DD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit. I W = V DD /R for V DD = 3 V or 5 V for the 5 kω and kω versions. 3 V A = V DD, Wiper (V W ) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V = V. DNL Specification limits of ± LS maximum are Guaranteed Monotonic operating conditions. See TPC 2 test circuit. 5 Resistor terminals A,, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 2 for a plot of I DD versus logic voltage. 9 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. All Dynamic Characteristics use V DD = 5 V. Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice.

4 AD4/AD42/AD43 SPECIFICATIONS (V DD = 3 V % or 5 V %, V A = V DD, V = V, 4 C T A +25 C unless otherwise noted.) ELECTRICAL CHARACTERISTI k VERSION Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTI RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R W, V A = No Connect 5 +3 LS Resistor Nonlinearity 2 R-INL R W, V A = No Connect 4 ±.5 +4 LS Nominal Resistance 3 R A T A = 25 C, Model: AD4XYY..2.6 kω Resistance Tempco R A / T V A = V DD, Wiper = No Connect 7 ppm/ C Wiper Resistance R W I W = V/R A 53 Ω Nominal Resistance Match R/R A CH to 2, V A = V DD, T A = 25 C.75 2 % DC CHARACTERISTI POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N its Integral Nonlinearity 4 INL 6 ± 2 +6 LS Differential Nonlinearity 4 DNL V DD = 5 V LS DNL V DD = 3 V, T A = 25 C LS Voltage Divider Temperature Coefficent V W / T Code = H 25 ppm/ C Full-Scale Error V WFSE Code = FF H 2 2 LS Zero-Scale Error V WZSE Code = H 6 LS RESISTOR TERMINALS Voltage Range 5 V A,, W V DD V Capacitance 6 Ax, x C A, f = MHz, Measured to GND, Code = H 75 pf Capacitance 6 Wx C W f = MHz, Measured to GND, Code = H 2 pf Shutdown Supply Current 7 I A_SD V A = V DD, V = V, SHDN =. 5 µa Shutdown Wiper Resistance R W_SD V A = V DD, V = V, SHDN =, V DD = 5 V 5 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V IH V DD = 5 V 2.4 V Input Logic Low V IL V DD = 5 V. V Input Logic High V IH V DD = 3 V 2. V Input Logic Low V IL V DD = 3 V.6 V Output Logic High V OH R L = 2.2 kω to V DD V DD. V Output Logic Low V OL I OL =.6 ma, V DD = 5 V.4 V Input Current I IL V IN = V or 5 V, V DD = 5 V ± µa Input Capacitance 6 C IL 5 pf POWER SUPPLIES Power Supply Range V DD Range V Supply Current (CMOS) I DD V IH = V DD or V IL = V. 5 µa Supply Current (TTL) I DD V IH = 2.4 V or. V, V DD = 5.5 V.9 4 ma Power Dissipation (CMOS) 9 P DISS V IH = V DD or V IL = V, V DD = 5.5 V 27.5 µw Power Supply Sensitivity PSS V DD = 5 V ± %.35. %/% PSS V DD = 3 V ± %.5.3 %/% 6, DYNAMIC CHARACTERISTI andwidth 3 d W_K R = kω 5, khz Total Harmonic Distortion THD W V A = V rms + 2 V dc, V = 2 V dc, f = khz.5 % V W Settling Time t S V A = V DD, V = V, ± % Error and.5 µs Resistor Noise Voltage e NW R W = 5 Ω, f = khz, RS = 3 nv/ Hz Crosstalk C T V A = V DD, V = V 65 d NOTES Typicals represent average readings at 25 C and V DD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC 29 test circuit. I W = 5 µa for V DD = 3 V and I W = 2.5 ma for V DD = 5 V for kω version. 3 V A = V DD, Wiper (V W ) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V = V. DNL Specification limits of ± LS maximum are Guaranteed Monotonic operating conditions. See TPC 2 test circuit. 5 Resistor terminals A,, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 2 for a plot of I DD versus logic voltage. 9 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. All Dynamic Characteristics use V DD = 5 V. Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. 4

5 AD4/AD42/AD43 SPECIFICATIONS (V DD = 3 V % or 5 V %, V A = V DD, V = V, 4 C T A +25 C unless otherwise noted.) ELECTRICAL CHARACTERISTI ALL VERSIONS Parameter Symbol Conditions Min Typ Max Unit SWITCHING CHARACTERISTI 2, 3 Input Clock Pulsewidth t CH, t CL Clock Level High or Low ns Data Setup Time t DS 5 ns Data Hold Time t DH 5 ns CLK to SDO Propagation Delay 4 t PD R L = kω to 5 V, C L 2 pf 25 ns Setup Time t S ns High Pulsewidth t W ns Reset Pulsewidth t RS 5 ns CLK Fall to Rise Hold Time t H ns Rise to Clock Rise Setup t ns NOTES Typicals represent average readings at 25 C and V DD = 5 V. 2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 3 See timing diagram for location of measured values. All input control voltages are specified with t R = t F = ns (% to 9% of V DD ) and timed from a voltage level of.6 V. Switching characteristics are measured using V DD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of V/µs should be maintained. 4 Propagation Delay depends on value of V DD, R L, and C L see Applications section. Specifications subject to change without notice. SDI CLK V DD V OUT V A A D7 D6 D5 D4 D3 D2 D D DAC REGISTER LOAD SDI (DATA IN) SDO (DATA OUT) CLK Ax OR Dx A'x OR D'x t PD_MIN t CH t S Ax OR Dx t DS t DH A'x OR D'x t CL t H t PD_MAX t t W t S V DD V OUT V % ERROR AND % Figure 2a. Timing Diagram Figure 2b. Detail Timing Diagram RS t RS V DD V OUT V DD /2 t S % ERROR AND % Figure 2c. Reset Timing Diagram 5

6 AD4/AD42/AD43 ASOLUTE MAXIMUM RATINGS* (T A = 25 C, unless otherwise noted.) V DD to GND V, + V V A, V, V W to GND V, V DD A X X, A X W X, X W X ± 2 ma Digital Input and Output Voltage to GND V, 7 V Operating Temperature Range C to +5 C Maximum Junction Temperature (T J max) C Storage Temperature C to +5 C Lead Temperature (Soldering, sec) C Package Power Dissipation (T J max T A )/θ JA Thermal Resistance (θ JA ) P-DIP (N-) C/W SOIC (SO-) C/W P-DIP (N-4) C/W P-DIP (N-24) C/W SOIC (SO-4) C/W SOIC (SOL-24) C/W TSSOP-4 (RU-4) C/W TSSOP-24 (RU-24) C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table I. Serial Data Word Format ADDR DATA A A D7 D6 D5 D4 D3 D2 D D MS LS MS LS CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD4/AD42/AD43 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 6

7 AD4/AD42/AD43 Number of Number of End-to-End Temperature Package Package Devices per randing Model Channels R A (k ) Range ( C) Description Option* Container Information AD4AN 4 to +25 PDIP- N- 5 4A AD4AR 4 to +25 SO- SO- 9 4A AD42AN 2 4 to +25 PDIP-4 N A AD42AR 2 4 to +25 SO-4 SO A AD42ARU 2 4 to +25 TSSOP-4 RU A AD42ARU-REEL 2 4 to +25 TSSOP-4 RU-4 2,5 4A AD43AN 4 4 to +25 PDIP-24 N A AD43AR 4 4 to +25 SOIC-24 SOL A AD43ARU 4 4 to +25 TSSOP-24 RU A AD43ARU-REEL 4 4 to +25 TSSOP-24 RU-24 2,5 4A AD4AN5 5 4 to +25 PDIP- N- 5 4A5 AD4AR5 5 4 to +25 SO- SO- 9 4A5 AD42AN to +25 PDIP-4 N A5 AD42AR to +25 SO-4 SO A5 AD42ARU to +25 TSSOP-4 RU A5 AD42ARU5-REEL to +25 TSSOP-4 RU-4 2,5 4A5 AD43AN to +25 PDIP-24 N A5 AD43AR to +25 SOIC-24 SOL A5 AD43ARU to +25 TSSOP-24 RU A5 AD43ARU5-REEL to +25 TSSOP-24 RU-24 2,5 4A5 AD4AN 4 to +25 PDIP- N- 5 4A AD4AR 4 to +25 SO- SO- 9 4A AD42AN 2 4 to +25 PDIP-4 N A AD42AR 2 4 to +25 SO-4 SO A AD42ARU 2 4 to +25 TSSOP-4 RU A AD42ARU-REEL 2 4 to +25 TSSOP-4 RU-4 2,5 4A AD43AN 4 4 to +25 PDIP-24 N A AD43AR 4 4 to +25 SOIC-24 SOL A AD43ARU 4 4 to +25 TSSOP-24 RU A AD43ARU-REEL 4 4 to +25 TSSOP-24 RU-24 2,5 4A AD4AN 4 to +25 PDIP- N- 5 4A AD4AR 4 to +25 SO- SO- 9 4A AD42AN 2 4 to +25 PDIP-4 N A AD42AR 2 4 to +25 SO-4 SO A AD42ARU 2 4 to +25 TSSOP-4 RU A AD42ARU-REEL 2 4 to +25 TSSOP-4 RU-4 2,5 4A AD43AN 4 4 to +25 PDIP-24 N A AD43AR 4 4 to +25 SOIC-24 SOL A AD43ARU 4 4 to +25 TSSOP-24 RU A AD43ARU-REEL 4 4 to +25 TSSOP-24 RU-24 2,5 4A *N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO. The AD4, AD42, and AD43 contain 72 transistors. ORDERING GUIDE 7

8 AD4/AD42/AD43 PIN CONFIGURATIONS AD4 PIN FUNCTION DESCRIPTIONS GND SDI AGND 2 A2 W2 DGND SHDN AD4 TOP VIEW (Not to Scale) A 7 W 6 V DD 5 CLK 2 3 AD A W 4 TOP VIEW V DD 5 (Not to Scale) RS CLK SDI Pin Name Description Terminal RDAC 2 GND Ground 3 Chip Select Input, Active Low. When returns high, data in the serial input register is loaded into the DAC register. 4 SDI Serial Data Input 5 CLK Serial Clock Input, Positive Edge Triggered. 6 V DD Positive power supply, specified for operation at both 3 V and 5 V. 7 W Wiper RDAC, Addr = 2 A Terminal A RDAC AGND A2 W2 AGND AD43 23 A 22 W 2 AGND TOP VIEW 9 A3 A4 W4 DGND 7 9 (Not to Scale) W3 7 AGND3 6 V DD SHDN 5 RS SDI 2 4 CLK 3 SDO AD42 PIN FUNCTION DESCRIPTIONS Pin Name Description AGND Analog Ground* 2 2 Terminal RDAC #2 3 A2 Terminal A RDAC #2 4 W2 Wiper RDAC #2, Addr = 2. 5 DGND Digital Ground* 6 SHDN Terminal A Open Circuit. Shutdown controls Variable Resistors # and #2. 7 Chip Select Input, Active Low. When returns high, data in the serial input register is decoded based on the address bits and loaded into the target DAC register. SDI Serial Data Input 9 CLK Serial Clock Input, Positive Edge Triggered. RS Active low reset to midscale; sets RDAC registers to H. V DD Positive power supply, specified for operation at both 3 V and 5 V. 2 W Wiper RDAC #, Addr = 2. 3 A Terminal A RDAC # 4 Terminal RDAC # *All AGNDs must be connected to DGND. AD43 PIN FUNCTION DESCRIPTIONS Pin Name Description AGND2 Analog Ground #2* 2 2 Terminal RDAC #2 3 A2 Terminal A RDAC #2 4 W2 Wiper RDAC #2, Addr = 2. 5 AGND4 Analog Ground #4* 6 4 Terminal RDAC #4 7 A4 Terminal A RDAC #4 W4 Wiper RDAC #4, Addr = 2. 9 DGND Digital Ground* SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistors # through #4. Chip Select Input, Active Low. When returns high, data in the serial input register is decoded based on the address bits and loaded into the target DAC register. 2 SDI Serial Data Input 3 SDO Serial Data Output, Open Drain transistor requires pull-up resistor. 4 CLK Serial Clock Input, Positive Edge Triggered 5 RS Active Low reset to midscale; sets RDAC registers to H. 6 V DD Positive power supply, specified for operation at both 3 V and 5 V. 7 AGND3 Analog Ground #3* W3 Wiper RDAC #3, Addr = 2 9 A3 Terminal A RDAC #3 2 3 Terminal RDAC #3 2 AGND Analog Ground #* 22 W Wiper RDAC #, Addr = 2 23 A Terminal A RDAC # 24 Terminal RDAC # *All AGNDs must be connected to DGND.

9 Typical Performance Characteristics AD4/AD42/AD43 RESISTANCE k R W V DD = 3V OR 5V R A = k R WA V W VOLTAGE V H 4 H FF H 2 H 5 H CODE = H R-INL ERROR LS.5.5 T A = 4 C T A = +5 C T A = +25 C CODE Decimal TPC. Wiper to End Terminal Resistance vs. Code I W CURRENT ma TPC 2. Resistance Linearity vs. Conduction Current DIGITAL INPUT CODE Decimal TPC 3. Resistance Step Position Nonlinearity Error vs. Code FREQUENCY SS = 25 UNITS V DD = 4.5V INL NONLINEARITY ERROR LS.5.5 T A = +25 C T A = 4 C T A = +5 C FREQUENCY SS = 4 UNITS V DD = 4.5V WIPER RESISTANCE DIGITAL INPUT CODE Decimal WIPER RESISTANCE TPC 4. kω Wiper-Contact- Resistance Histogram TPC 5. Potentiometer Divider Nonlinearity Error vs. Code TPC 6. 5 k Wiper-Contact- Resistance Histogram FREQUENCY SS = 4 UNITS V DD = 4.5V WIPER RESISTANCE TPC 7. kω Wiper-Contact- Resistance Histogram NOMINAL RESISTANCE k R A (END-TO-END) R W (WIPER-TO-END) CODE = H R A = k TEMPERATURE C TPC. Nominal Resistance vs. Temperature POTENTIOMETER MODE TEMPCO ppm/ C T A = 4 C/+5 C V A = 2.V V = V CODE Decimal TPC 9. DV W /DT Potentiometer Mode Tempco 9

10 AD4/AD42/AD43 RHEOSTAT MODE TEMPCO ppm/ C T A = 4 C/+5 C V A = NO CONNECT R W MEASURED CODE Decimal R W (2mV/DIV) (5V/DIV) TIME 5ns/DIV GAIN d CODE = FF 42 4 T A = +25 C SEE TEST CIRCUIT 7 54 k k k M TPC. R W / T Rheostat Mode Tempco TPC. One Position Step Change at Half-Scale (Code 7F H to H ) TPC 2. kω Gain vs. Frequency.75.5 CODE = H SS = 5 UNITS 6 6 CODE = FF H R W RESISTANCE % AVG + 2 SIGMA AVG 2 SIGMA AVG HOURS OF OPERATION AT 5 C OUTPUT INPUT TIME 5 s/div GAIN d 2 H 4 H 2 H 24 3 H H 36 4 H 42 2 H 4 H 54 k k k M TPC 3. Long-Term Drift Accelerated by urn-in TPC 4. Large Signal Settling Time TPC 5. 5 kω Gain vs. Frequency vs. Code THD + NOISE %.. FILTER = 22kHz SEE TEST CIRCUIT 5 SEE TEST CIRCUIT 6. k k k TPC 6. Total Harmonic Distortion Plus Noise vs. Frequency V OUT (5mV/DIV) TIME 2ns/DIV TPC 7. Digital Feedthrough vs. Time GAIN d H 4 H 2 H H H 4 H 2 H H CODE = FF H 54 k k k M TPC. kω Gain vs. Frequency vs. Code

11 NORMALIZED GAIN FLATNESS.d/DIV SEE TEST CIRCUIT 7 CODE = H R = 5k R = k R = k k k k M TPC 9. Normalized Gain Flatness vs. Frequency IDD SUPPLY CURRENT ma. V DD = 3V DIGITAL INPUT VOLTAGE V TPC 2. Supply Current vs. Digital Input Voltage AD4/AD42/AD43 PSRR d V DD = +5V DC V p-p AC CODE = H C L = pf V A = 4V, V = V SEE TEST CIRCUIT 4 k k k M TPC 2. Power Supply Rejection vs. Frequency GAIN d f 3d = 7kHz, R = k f 3d = 7kHz, R = k f 3d = 25kHz, R = 5k 3 V IN = mv rms 36 R L = M 42 k k k M TPC d andwidths I DD SUPPLY CURRENT µa 2 A V DD = 5.5V CODE = 55 H V DD = 3.3V CODE = 55 H C V DD = 5.5V CODE = FF H 6 D V DD = 3.3V CODE = FF H 4 2 D k k k M M TPC 23. Supply Current vs. Clock Frequency A C R ON V DD = 2.7V V DD = 5.5V SEE TEST CIRCUIT V IAS V TPC 24. AD43 Incremental Wiper ON Resistance vs. V DD GAIN d PHASE Degrees WIPER SET AT HALF-SCALE H I A SHUTDOWN CURRENT na IDD SUPPLY CURRENT A.. LOGIC INPUT VOLTAGE =, V DD V DD = 5.5V V DD = 3.3V k 2k 4k M 2M 4M 6M M TPC 25. kω Gain and Phase vs. Frequency TEMPERATURE C TPC 26. Shutdown Current vs. Temperature TEMPERATURE C TPC 27. Supply Current vs. Temperature

12 AD4/AD42/AD43 TEST CIRCUITS A DUT V+ DUT A W V+ = V DD LS = V+/256 V MS OFFSET GND ~ W V IN 2.5V DC OP279 5V V OUT Test Circuit. Potentiometer Divider Nonlinearity Error (INL, DNL) Test Circuit 5. Inverting Programmable Gain 5V NO CONNECT DUT A W V MS I W OFFSET GND V IN ~ OP279 W A DUT 2.5V V OUT Test Circuit 2. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Test Circuit 6. Noninverting Programmable Gain A +5V I MS V+ DUT A W V W I W = V/R NOMINAL V MS V+ V DD V W2 [V W + I W (R AW II R W )] R W = I W WHERE V W = V MS WHEN I W = AND V W2 = V MS WHEN I W = /R OFFSET GND V IN ~ W DUT 2.5V OP42 5V V OUT Test Circuit 3. Wiper Resistance Test Circuit 7. Gain vs. Frequency V+ ~ V DD V A A W V MS V+ = V DD % V MS PSRR (d) = 2LOG ( ) V DD V MS % PSS (%/%) = V DD % DUT W R SW =.V I SW CODE = ØØ H I SW V IAS +.V A = NC Test Circuit 4. Power Supply Sensitivity (PSS, PSRR) Test Circuit. Incremental ON Resistance 2

13 AD4/AD42/AD43 OPERATION The AD4/AD42/AD43 provide a single, dual, and quad channel, 256-position digitally controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a -bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is two address bits, MS first, followed by eight data bits, MS first. Table I provides the serial register data word format. The AD4/AD42/AD43 has the following address assignments for the ADDR decode, which determines the location of VR latch receiving the serial register data in its 7 through : VR# = A 2 + A + () The single-channel AD4 requires A = A =. The dualchannel AD42 requires A =. VR settings can be changed one at a time in random sequence. The serial clock running at MHz makes it possible to load all four VRs in under 4 µs ( 4 ns) for the AD43. The exact timing requirements are shown in Figures 2a, 2b, and 2c. The AD42/AD43 resets to midscale by asserting the RS pin, simplifying initial conditions at power up. oth parts have a power shutdown SHDN pin that places the VR in a zero power consumption state where terminals Ax are open circuited and the wiper Wx is connected to x resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained so that returning to operational mode from power shutdown, the VR settings return to their previous resistance values. The digital interface is still active in shutdown, except that SDO is deactivated. Code changes in the registers can be made that will produce new wiper positions when the device is taken out of shutdown. SHDN D7 D6 D5 D4 D3 D2 D D RDAC AND DECODER R S R S R S R S R S = R NOMINAL /256 Figure 3. AD42/AD43 Equivalent VR (RDAC) Circuit Ax Wx x PROGRAMMING THE VARIALE RESISTOR Rheostat Operation The nominal resistance of the VR (RDAC) between terminals A and is available with values of kω, kω, 5 kω, and kω. The final digits of the part number determine the nominal resistance value, e.g., kω = ; kω =. The nominal resistance (R A ) of the VR has 256 contact points accessed by the wiper terminal, plus the terminal contact. The -bit data word in the RDAC latch is decoded to select one of the 256 possible settings. The wiper s first connection starts at the terminal for data H. This terminal connection has a wiper contact resistance of 5 Ω. The second connection ( kω part) is the first tap point located at 9 Ω [= R A (nominal resistance)/256 + R W = 39 Ω + 5 Ω] for data H. The third connection is the next tap point representing = 2 Ω for data 2 H. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at, Ω. The wiper does not directly connect to the terminal. See Figure 3 for a simplified diagram of the equivalent RDAC circuit. The AD4 contains one RDAC, the AD42 contains two independent RDACs, and the AD43 contains four independent RDACs. The general transfer equation that determines the digitally programmed output resistance between Wx and x is: ( )= ( ) + R Dx Dx / 256 R R (2) W A W where Dx is the data contained in the -bit RDAC# latch, and R A is the nominal end-to-end resistance. For example, when V = V and when the A terminal is open circuit, the following output resistance values will be set for the following RDAC latch codes (applies to kω potentiometers): D R W (Dec) ( ) Output State 255, Full Scale 2 5,5 Midscale (RS = Condition) 9 LS 5 Zero-Scale (Wiper Contact Resistance) Note in the zero-scale condition a finite wiper resistance of 5 Ω is present. Care should be taken to limit the current flow between W and in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance R WA. When these terminals are used, the terminal can be tied to the wiper or left floating. Setting the resistance value for R WA starts at a maximum value of resistance and decreases as the data loaded in the RDAC latch is increased in value. The general transfer equation for this operation is: RWA( DX)= ( 256 DX) 256 RA + RW (3) 3

14 AD4/AD42/AD43 where Dx is the data contained in the -bit RDAC# latch, and R A is the nominal end-to-end resistance. For example, when V A = V and terminal is open circuit, the following output resistance values will be set for the following RDAC latch codes (applies to kω potentiometers): D R WA (Dec) ( ) Output State Full Scale 2 5,5 Midscale (RS = Condition), LS,5 Zero Scale CLK SDI A A D7 -IT SER REG DI D EN ADDR DEC D7 RDAC D # AD4 GND V DD A W The typical distribution of R A from channel to channel matches within ± %. However, device-to-device matching is process lotdependent, having a ± 2% variation. The change in R A with temperature has a positive 5 ppm/ C temperature coefficient. The wiper-to-end-terminal resistance temperature coefficient has the best performance over the % to % of adjustment range where the internal wiper contact switches do not contribute any significant temperature related errors. The graph in TPC shows the performance of R W tempco versus code: using the trimmer with codes below 32 results in the larger temperature coefficients plotted. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting A terminal to 5 V and terminal to ground produces an output voltage at the wiper starting at zero volts up to LS less than 5 V. Each LS of voltage is equal to the voltage applied across terminal A divided by the 256 position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals A is: VW ( DX)= DX 256 VA + V (4) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 5 ppm/ C. At the lower wiper position settings, the potentiometer divider temperature coefficient increases due to the contributions of the CMOS switch wiper resistance becoming an appreciable portion of the total resistance from Terminal to the wiper. See TPC 9 for a plot of potentiometer tempco performance versus code setting. DIGITAL INTERFACING The AD4/AD42/AD43 contain a standard SPI compatible three-wire serial input control interface. The three inputs are clock (CLK), and serial data input (SDI). The positiveedge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. For best results use logic transitions faster than V/µs. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. The Figure 4 block diagrams show more detail of the internal digital circuitry. When is taken active low, the clock loads data into the -bit serial register on each positive clock edge (see Table II). CLK SDO SDI SHDN CLK SDI SHDN DO DI A A D7 -IT SER REG DI D DGND A A D7 SER REG DGND D EN ADDR DEC EN ADDR DEC RS RS a. b. D7 D D7 D D7 D D7 D RDAC # R RDAC #2 R RDAC # R AD42 AGND AD43 RDAC #4 R c. Figure 4. lock Diagrams AGND V DD A W A4 W4 4 V DD A W A4 W4 4 4

15 AD4/AD42/AD43 Table II. Input Logic Control Truth Table CLK RS SHDN Register Activity L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the SDI pin. The tenth previously entered bit is shifted out of the SDO pin. X P H H Load SR data into RDAC latch based on A, A decode (Table III). X H H H No Operation X X L H Sets all RDAC latches to midscale, wiper centered, and SDO latch cleared. X H P H Latches all RDAC latches to H. X H H L Open circuits all resistor A-terminals, connects W to, turns off SDO output transistor. NOTE: P = positive edge, X = don t care, SR = shift register. The serial data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package s SDI pin. The pull-up resistor termination voltage may be larger than the V DD supply (but less than max V DD of V) of the AD43 SDO output device, e.g., the AD43 could operate at V DD = 3.3 V and the pull-up for interface to the next device could be set at 5 V. This allows for daisy-chaining several RDACs from a single processor serial data line. The clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy-chain node SDO SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the should be kept low until all the bits of every package are clocked into their respective serial registers ensuring that the address bits and data bits are in the proper decoding location. This would require 2 bits of address and data complying to the word format provided in Table I if two AD43 four-channel RDACs are daisy-chained. Note, only the AD43 has a SDO pin. During shutdown SHDN the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. See Figure 6 for equivalent SDO output circuit schematic. The data setup and data hold times in the specification table determine the data valid time requirements. The last bits of the data word entered into the serial register are held when returns high. At the same time goes high it gates the address decoder, which enables one of the two (AD42) or four (AD43) positive edge triggered RDAC latches. See Figure 5 detail and Table III Address Decode Table. Table III. Address Decode Table A A Latch Decoded RDAC# RDAC#2 RDAC#3 AD43 Only RDAC#4 AD43 Only CLK SDI AD43 ADDR DECODE SERIAL REGISTER RDAC RDAC 2 RDAC 4 Figure 5. Equivalent Input Control Logic The target RDAC latch is loaded with the last eight bits of the serial data word completing one DAC update. In the case of the AD43 four separate -bit data words must be clocked in to change all four VR settings. SHDN SDI CLK RS SERIAL REGISTER D Q CK RS SDO Figure 6. Detail SDO Output Schematic of the AD43 All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 7a. This structure applies to digital pins, SDI, SDO, RS, SHDN, CLK. The digital input ESD protection allows for mixed power supply applications where 5 V CMOS logic can be used to drive an AD4/AD42 or AD43 operating from a 3 V power supply. The analog pins A,, and W are protected with a 2 Ω series resistor and parallel Zener. (see Figure 7b). DIGITAL PINS k LOGIC Figure 7a. Equivalent ESD Protection Circuits A,, W 2 Figure 7b. Equivalent ESD Protection Circuit (Analog Pins) A C A C A = 9.4pF ( DW ) + 3pF 256 RDAC k W C W 2pF C C = 9.4pF ( Figure. RDAC Circuit Simulation Model for RDAC = kω DW ) + 3pF 256 5

16 AD4/AD42/AD43 The ac characteristics of the RDACs are dominated by the internal parasitic capacitances and the external capacitive loads. The 3 d bandwidth of the AD43AN ( kω resistor) measures 6 khz at half scale as a potentiometer divider. TPC 22 provides the large signal ODE plot characteristics of the three available resistor versions kω, 5 kω, and kω. The gain flatness versus frequency graph, TPC 25, predicts filter applications performance. A parasitic simulation model has been developed, and is shown in Figure. Listing I provides a macro model net list for the kω RDAC: Listing I. Macro Model Net List for RDAC.PARAM DW=255, RDAC=E3 *.SUCKT DPOT (A,W,) * CA A {DW/256*9.4E-2+3E-2} RAW A W {(-DW/256)*RDAC+5} CW W 2E-2 RW W {DW/256*RDAC+5} C {(-DW/256)*9.4E-2+3E-2} *.ENDS DPOT The total harmonic distortion plus noise (THD+N) is measured at.3% in an inverting op amp circuit using an offset ground and a rail-to-rail OP279 amplifier, Test Circuit 5. Thermal noise is primarily Johnson noise, typically 9 nv/ Hz for the kω version at f = khz. For the kω device, thermal noise becomes 29 nv/ Hz. Channel-to-channel crosstalk measures less than 65 d at f = khz. To achieve this isolation, the extra ground pins provided on the package to segregate the individual RDACs must be connected to circuit ground. AGND and DGND pins should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power supply rejection is typically 35 d at khz (care is needed to minimize power supply ripple in high accuracy applications). APPLICATIONS The digital potentiometer (RDAC) allows many of the applications of trimming potentiometers to be replaced by a solid-state solution offering compact size and freedom from vibration, shock and open contact problems encountered in hostile environments. A major advantage of the digital potentiometer is its programmability. Any settings can be saved for later recall in system memory. The two major configurations of the RDAC include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in Test Circuits and 2 (see page ). Certain boundary conditions must be satisfied for proper AD4/ AD42/AD43 operation. First, all analog signals must remain within the to V DD range used to operate the single-supply AD4/AD42/AD43 products. For standard potentiometer divider applications, the wiper output can be used directly. For low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP29 or the OP279. Second, for ac signals and bipolar dc adjustment applications, a virtual ground will generally be needed. Whatever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, including adequate bypass capacitance. Test Circuit 5 (see page ) shows one channel of the AD42 connected in an inverting programmable gain amplifier circuit. The virtual ground is set at 2.5 V, which allows the circuit output to span a ±2.5 volt range with respect to virtual ground. The rail-to-rail amplifier capability is necessary for the widest output swing. As the wiper is adjusted from its midscale reset position ( H ) toward the A terminal (code FF H ), the voltage gain of the circuit is increased in successfully larger increments. Alternatively, as the wiper is adjusted toward the terminal (code H ), the signal becomes attenuated. The plot in Figure 9 shows the wiper settings for a : range of voltage gain (V/V). Note the ± d of pseudo-logarithmic gain around d ( V/V). This circuit is mainly useful for gain adjustments in the range of.4 V/V to 4 V/V; beyond this range the step sizes become very large and the resistance of the driving circuit can become a significant term in the gain equation. DIGITAL CODE Decimal INVERTING GAIN V/V Figure 9. Inverting Programmable Gain Plot 6

17 AD4/AD42/AD43 ACTIVE FILTER One of the standard circuits used to generate a low-pass, highpass, or band-pass filter is the state variable active filter. The digital potentiometer allows full programmability of the frequency, gain and Q of the filter outputs. Figure shows the filter circuit using a 2.5 V virtual ground, which allows a ±2.5 V P input and output swing. RDAC2 and 3 set the LP, HP, and P cutoff and center frequencies, respectively. These variable resistors should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit Q. Figure shows the measured filter response at the band-pass output as a function of the RDAC2 and RDAC3 settings which produce a range of center frequencies from 2 khz to 2 khz. The filter gain response at the band-pass output is shown in Figure 2. At a center frequency of 2 khz, the gain is adjusted over a 2 d to +2 d range determined by RDAC. Circuit Q is adjusted by RDAC4. For more detailed reading on the state variable active filter, see Analog Devices application note, AN-3. AMPLITUDE d k A 2 k k k 2k Figure. Programmed Center Frequency and-pass Response V IN RDAC A RDAC4 k k A2 RDAC2 OP F A3 RDAC3. F A4 LOW- PASS AND- PASS AMPLITUDE d k A HIGH- PASS 6 Figure. Programmable State Variable Active Filter 2 k k k 2k Figure 2. Programmed Amplitude and-pass Response 7

18 AD4/AD42/AD43 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead Plastic DIP (N-).43 (.92).34 (.4) (7.).24 (6.) PIN.2 (5.33) MAX.6 (4.6).5 (2.93). (2.54) SC.22 (.55).4 (.356).7 (.77).45 (.5).6 (.52).5 (.3).3 (3.3) MIN SEATING PLANE.325 (.25).3 (7.62).95 (4.95).5 (2.93).5 (.3). (.24) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN -Lead SOIC (R-).96 (5.).9 (4.).574 (4.).497 (3.) (6.2).224 (5.) PIN.9 (.25).4 (.).6 (.75).532 (.35).96 (.5).99 (.25) x 45 SEATING PLANE.5.92 (.49) (.27).3 (.35) SC.9 (.25).75 (.9).5 (.27).6 (.4) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 4-Lead Plastic DIP Package (N-4) PIN.2 (5.33) MAX.6 (4.6).5 (2.93).795 (2.9).725 (.42) 4 7. (2.54) SC.22 (.55).4 (.356).7 (.77).45 (.5).2 (7.).24 (6.).6 (.52).5 (.3).3 (3.3) MIN SEATING PLANE.325 (.25).3 (7.62).5 (.3). (.24).95 (4.95).5 (2.93) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

19 AD4/AD42/AD43 4-Lead Narrow ody SOIC Package (SO-4).3444 (.75).3367 (.55).574 (4.).497 (3.) (6.2).224 (5.) PIN.5 (.27) SC.6 (.75).532 (.35).96 (.5) (.25).9 (.25).4 (.).92 (.49).3 (.35) SEATING PLANE.99 (.25).75 (.9).5 (.27).6 (.4) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 4-Lead TSSOP (RU-4).2 (5.).93 (4.9) (4.5).69 (4.3).256 (6.5).246 (6.25) PIN.6 (.5).2 (.5).433 (.) MAX SEATING PLANE.256 (.65) SC. (.3).75 (.9).79 (.2).35 (.9).2 (.7).2 (.5) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 24-Lead Narrow ody Plastic DIP Package (N-24) PIN.2 (5.33) MAX.2 (5.5).25 (3.).275 (32.3).25 (2.6) (.55).4 (.356). (2.54) SC.7 (.77).45 (.5).2 (7.).24 (6.).6 (.52).5 (.3).5 (3.) MIN SEATING PLANE.325 (.25).3 (7.62).5 (.3). (.24) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.95 (4.95).5 (2.93) 9

20 AD4/AD42/AD43 OUTLINE DIMENSIONS (continued) Dimensions shown in inches and (mm). 24-Lead SOIC Package (SOL-24) (7.6).294 (7.4).64 (5.6).595 (5.2) (.65).3937 (.) C92 2/2(C) PIN.43 (2.65).926 (2.35).29 (.74) 45.9 (.25). (.3).4 (.).5 (.27) SC.92 (.49).3 (.35) SEATING PLANE.25 (.32).9 (.23).5 (.27).57 (.4) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 24-Lead Thin Surface-Mount TSSOP Package (RU-24).3 (7.9).33 (7.7) (4.5).69 (4.3).256 (6.5).246 (6.25) PIN.6 (.5).2 (.5).433 (.) MAX SEATING PLANE.256 (.65). (.3) SC.75 (.9).79 (.2).35 (.9).2 (.7).2 (.5) CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page Data Sheet changed from REV. to. Addition of new Figure Edits to SPECIFICATIONS Edits to ASOLUTE MAXIMUM RATINGS Edits to TPCs,, 2, 6, 2, 24, Edits to PROGRAMMING THE VARIALE RESISTOR section PRINTED IN U.S.A. 2

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