256-Position and 33-Position Digital Potentiometers AD5200/AD5201

Transcription

1 a FETUES D52 25-Position D52 33-Position k, 5 k 3-ire SPI-Compatible Serial Data Input Single Supply 2.7 V to 5.5 V or Dual Supply 2.7 V for C or ipolar Operations Internal Power-On Midscale Preset PPLICTIONS Mechanical Potentiometer eplacement Instrumentation: Gain, Offset djustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching 25-Position and 33-Position Digital Potentiometers D52/D52 V DD CS CLK SDI GND FUNCTIONL LOCK DIGM D52/D52 SE EG Dx P-ON PESET 8/ DC EG V SS SHDN GENEL DESCIPTION The D52 and D52 are programmable resistor devices, with 25 positions and 33 positions respectively, that can be digitally controlled through a 3-wire SPI serial interface. The terms programmable resistor, variable resistor (V), and DC are commonly used interchangeably to refer to digital potentiometers. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. oth D52/D52 contain a single variable resistor in the compact µsoic- package. Each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code. The code is loaded in the serial input register. The resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the V latch. Each variable resistor offers a completely programmable value of resistance, between the terminal and the wiper, or the terminal and the wiper. The fixed -to- terminal resistance of kω or 5 kω has a nominal temperature coefficient of 5 ppm/ C. The V has a V latch that holds its programmed resistance value. The V latch is updated from an SPI-compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits for the D52 and six data bits for the D52 make up the data word that is clocked into the serial input register. The internal preset forces the wiper to the midscale position by loading 8 H and H into D52 and D52 V latches respectively. The SHDN pin forces the resistor to an end-to-end open-circuit condition on the terminal and shorts the wiper to the terminal, achieving a microwatt power shutdown state. hen SHDN is returned to logic high, the previous latch setting puts the wiper in the same resistance setting prior to shutdown. The digital interface is still active during shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown. ll parts are guaranteed to operate over the extended industrial temperature range of 4 C to +85 C. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. One Technology ay, P.O. ox 9, Norwood, M 22-9, U.S.. Tel: 78/ Fax: 78/ nalog Devices, Inc., 2

2 D52/D52 SPECIFICTIONS D52 ELECTICL CHCTEISTICS (V DD = 5 V %, or 3 V %, V SS = V, V = +V DD, V = V, 4 C < T < +85 C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit DC CHCTEISTICS HEOSTT MODE esistor Differential Nonlinearity 2 -DNL, V = No Connect ±.25 + LS esistor Integral Nonlinearity 2 -INL, V = No Connect 2 ±.5 +2 LS Nominal esistor Tolerance 3 T = 25 C 3 +3 % esistance Temperature Coefficient / T V = V DD, iper = No Connect 5 ppm/ C iper esistance V DD = 5 V 5 Ω DC CHCTEISTICS POTENTIOMETE DIVIDE MODE (Specifications apply to all Vs.) esolution N 8 its Differential Nonlinearity 4 DNL ± /4 + LS Integral Nonlinearity 4 INL 2 ± /2 +2 LS Voltage Divider Temperature Coefficient V / T Code = 8 H 5 ppm/ C Full-Scale Error V FSE Code = FF H.5.5 LS Zero-Scale Error V ZSE Code = H LS ESISTO TEMINLS Voltage ange 5 V,, V SS V DD V Capacitance, C, f = MHz, Measured to GND, Code = 8 H 45 pf Capacitance C f = MHz, Measured to GND, Code = 8 H pf Shutdown Supply Current 7 I DD_SD V DD = 5.5 V. 5 µ Common-Mode Leakage I CM V = V = V DD /2 n DIGITL INPUTS ND OUTPUTS Input Logic High V IH 2.4 V Input Logic Low V IL.8 V Input Logic High V IH V DD = 3 V, V SS = V 2. V Input Logic Low V IL V DD = 3 V, V SS = V. V Input Current I IL V IN = V or 5 V ± µ Input Capacitance C IL 5 pf POE SUPPLIES Logic Supply V LOGIC V Power Single-Supply ange V DD NGE V SS = V V Power Dual-Supply ange V DD/SS NGE ± 2.3 ± 2.7 V Positive Supply Current I DD V IH = +5 V or V IL = V 5 4 µ Negative Supply Current I SS V SS = 5 V 5 4 µ Power Dissipation 8 P DISS V IH = +5 V or V IL = V, V DD = +5 V, V SS = V.2 m Power Supply Sensitivity PSS V DD = +5 V ± %, Code = Midscale.. +. %/% DYNMIC CHCTEISTICS, 9 andwidth 3 d _ kω = kω, Code = 8 H khz _5 kω = 5 kω, Code = 8 H khz Total Harmonic Distortion THD V = V rms, V = V, f = khz, = kω.3 % V Settling Time ( kω/5 kω) t S V = 5 V, V = V, ± LS Error and 2/9 µs esistor Noise Voltage Density e N_ = 5 kω, S = 9 nv Hz NOTES Typicals represent average readings at 25 C and V DD = 5 V, V SS = V. 2 esistor position nonlinearity error -INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. -DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V DD / for both V DD = +2.7 V, V SS = 2.7 V. 3 V = V DD, iper (V ) = No connect. 4 INL and DNL are measured at V with the DC configured as a potentiometer divider similar to a voltage output D/ converter. V = V DD and V = V. DNL specification limits of ± LS maximum are Guaranteed Monotonic operating conditions. 5 esistor Terminals,, have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. 7 Measured at the terminal. terminal is open-circuited in shutdown mode. 8 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. 9 ll dynamic characteristics use V DD = 5 V, V SS = V. Specifications subject to change without notice. 2

3 D52 ELECTICL CHCTEISTICS D52/D52 (V DD = 5 V %, or 3 V %, V SS = V, V = +V DD, V = V, 4 C < T < +85 C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit DC CHCTEISTICS HEOSTT MODE esistor Differential Nonlinearity 2 -DNL, V = No Connect.5 ± LS esistor Integral Nonlinearity 2 -INL, V = No Connect ±. + LS Nominal esistor Tolerance 3 T = 25 C 3 +3 % esistance Temperature Coefficient / T V = V DD, iper = No Connect 5 ppm/ C iper esistance V DD = 5 V 5 Ω DC CHCTEISTICS POTENTIOMETE DIVIDE MODE (Specifications apply to all Vs.) esolution 4 N its Differential Nonlinearity 5 DNL.5 ±. +.5 LS Integral Nonlinearity 5 INL ±.2 + LS Voltage Divider Temperature Coefficient V / T Code = H 5 ppm/ C Full-Scale Error V FSE Code = 2 H /2 /4 LS Zero-Scale Error V ZSE Code = H +/4 +/2 LS ESISTO TEMINLS Voltage ange V,, V SS V DD V Capacitance 7, C, f = MHz, Measured to GND, Code = H 45 pf Capacitance 7 C f = MHz, Measured to GND, Code = H pf Shutdown Supply Current 8 I DD_SD V DD = 5.5 V. 5 µ Common-Mode Leakage I CM V = V = V DD /2 n DIGITL INPUTS ND OUTPUTS Input Logic High V IH 2.4 V Input Logic Low V IL.8 V Input Logic High V IH V DD = 3 V, V SS = V 2. V Input Logic Low V IL V DD = 3 V, V SS = V. V Input Current I IL V IN = V or 5 V ± µ Input Capacitance 7 C IL 5 pf POE SUPPLIES Logic Supply V LOGIC V Power Single-Supply ange V DD NGE V SS = V V Power Dual-Supply ange V DD/SS NGE ± 2.3 ± 2.7 V Positive Supply Current I DD V IH = +5 V or V IL = V 5 4 µ Negative Supply Current I SS V SS = 5 V 5 4 µ Power Dissipation 9 P DISS V IH = +5 V or V IL = V, V DD = +5 V, V SS = 5 V.2 m Power Supply Sensitivity PSS V DD = +5 V ± %.. +. %/% 7, DYNMIC CHCTEISTICS andwidth 3 d _ kω = kω, Code = H khz _5 kω = 5 kω, Code = H khz Total Harmonic Distortion THD V = V rms, V = V, f = khz, = kω.3 % V Settling Time ( kω/5 kω) t S V = 5 V, V = V, ± LS Error and 2/9 µs esistor Noise Voltage Density e N_ = 5 kω, S = 9 nv Hz NOTES Typicals represent average readings at 25 C and V DD = 5 V, V SS = V. 2 esistor position nonlinearity error -INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. -DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V DD / for both V DD = +2.7 V, V SS = 2.7 V. 3 V = V DD, iper (V ) = No connect. 4 Six bits are needed for 33 positions even though it is not a 4-position device. 5 INL and DNL are measured at V with the DC configured as a potentiometer divider similar to a voltage output D/ converter. V = V DD and V = V. DNL specification limits of ± LS maximum are Guaranteed Monotonic operating conditions. esistor Terminals,, have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the terminal. terminal is open-circuited in shutdown mode. 9 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. ll dynamic characteristics use V DD = 5 V, V SS = V. Specifications subject to change without notice. 3

4 D52/D52 SPECIFICTIONS ELECTICL CHCTEISTICS (V DD = 5 V %, or 3 V %, V SS = V, V = +V DD, V = V, 4 C < T < +85 C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit INTEFCE TIMING CHCTEISTICS (pplies to ll Parts [Notes 2, 3]) Input Clock Pulsewidth t CH, t CL Clock Level High or Low 2 ns Data Setup Time t DS 5 ns Data Hold Time t DH 5 ns CS Setup Time t CSS 5 ns CS High Pulsewidth t CS 4 ns CLK Fall to CS Fall Hold Time t CSH ns CLK Fall to CS ise Hold Time t CSH ns CS ise to Clock ise Setup t CS ns NOTES Typicals represent average readings at 25 C and V DD = 5 V, V SS = V. 2 Guaranteed by design and not subject to production test. 3 See timing diagram for location of measured values. ll input control voltages are specified with t = t F = 2 ns (% to 9% of 3 V) and timed from a voltage level of.5 V. Switching characteristics are measured using V LOGIC = 5 V. Specifications subject to change without notice. SDI CLK CS VOUT D7 D D5 D4 D3 D2 D D DC EGISTE LOD Figure a. D52 Timing Diagram SDI D5 D4 D3 D2 D D CLK DC EGISTE LOD CS VOUT Figure b. D52 Timing Diagram SDI (DT IN) CLK CS V DD VOUT Dx t CSH tcss Dx t CH t DS tdh tcs t CL t CSH t CS t S LS Figure c. Detail Timing Diagram 4

5 D52/D52 SOLUTE MXIMUM TINGS (T = 25 C, unless otherwise noted) V DD to V SS V V DD to GND , +7 V V SS to GND V, 7 V V, V, V to GND V SS, V DD I MX ± 2 m 2 Digital Inputs and Output Voltage to GND V, 7 V Operating Temperature ange C to +85 C Maximum Junction Temperature (T J Max) C Storage Temperature C to +5 C Lead Temperature (Soldering, sec) C Thermal esistance θ J, µsoic C/ Package Power Dissipation = (T J Max T )/θ J NOTES Stresses above those listed under bsolute Maximum atings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the,, and terminals at a given resistance. Please refer to TPC 3 and TPC 32 for detail. PIN FUNCTION DESCIPTIONS Pin Name Description Terminal. 2 V SS Negative Power Supply, specified for operation from V to 2.7 V. 3 GND Ground. 4 CS Chip Select Input, ctive Low. hen CS returns high, data will be loaded into the DC register. 5 SDI Serial Data Input. CLK Serial Clock Input, positive edge triggered. 7 SHDN ctive Low Input. Terminal open circuit. Shutdown controls Variable esistors of DC to temporary infinite. 8 V DD Positive Power Supply (Sum of V DD + V SS 5.5 V). 9 iper Terminal. Terminal. PIN CONFIGUTION V SS GND CS SDI D52/ D52 TOP VIE (Not to Scale) V DD SHDN CLK ODEING GUIDE Temperature Package Package Full randing Model ES k ange Description Option eel Qty. Information D52M-EEL C/+85 C µsoic- M- 5 DL D52M5-EEL C/+85 C µsoic- M- 5 DL D52M-EEL C/+85 C µsoic- M- 5 DM D52M5-EEL C/+85 C µsoic- M- 5 DM CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough the D52/D52 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. NING! ESD SENSITIVE DEVICE 5

6 D52/D52 Typical Performance Characteristics.2.5. V DD = 2.7V, V SS = V.2..8 V DD = 5.5V, V SS = V DNL LS.5..5 INL LS..4 V DD = +2.7V V SS = 2.7V. V DD = +2.7V, V SS = 2.7V.5 V DD = 5.5V, V SS = V TPC. D52 kω DNL vs. Code.2 V DD = 2.7V, V SS = V TPC 4. D52 kω INL vs. Code.3.2 V DD = 5.5V, V SS = V V DD = 2.7V, V SS = V..5 V DD = 2.7V, V SS = V. DNL LS... V DD = +2.7V, V SS = 2.7V TPC 2. D52 kω DNL vs. Code DNL LS V DD = 5.5V, V SS = V.25 V DD = +2.7V, V SS = 2.7V TPC 5. D52 kω DNL vs. Code.7.2 INL LS V DD = 2.7V, V SS = V V DD = 5.5V, V SS = V V DD = +2.7V, V SS = 2.7V TPC 3. D52 kω INL vs. Code DNL LS.5. V DD = 5.5V, V SS = V V DD = +2.7V, V SS = 2.7V.5..5 V DD = 2.7V, V SS = V TPC. D52 kω DNL vs. Code

7 D52/D52 INL LS.3.2 V DD = 5.5V, V SS = V V DD = +2.7V, V SS = 2.7V.4 V DD = 2.7V, V SS = V TPC 7. D52 kω INL vs. Code I DD SUPPLY CUENT V DD = 5.5V V DD = 2.7V V IL = V SS V IH = V DD TEMPETUE C TPC. Supply Current vs. Temperature.2 V DD = +2.7V, V SS = 2.7V 4 V DD = 5.5V.5 2 INL LS..5. V DD = 5.5V, V SS = V I SHUTDON CUENT n V DD = 2.7V, V SS = V TPC 8. D52 kω INL vs. Code TEMPETUE C TPC. Shutdown Current vs. Temperature I V DD /V SS = 5V/V 4 SEE TEST CICUIT 3 T = 25 C. 2 I DD /I SS m. I V DD /V SS = 2.5V I V DD /V SS = 2.5V ON 8 V DD = 2.7V V DD = 5.5V. 4 I V DD /V SS = 3V/V V IH V V SUPPLY V TPC 9. Supply Current vs. Logic Input Voltage TPC 2. iper ON esistance vs. V SUPPLY 7

8 D52/D CODE FF H 8 H H I DD /I SS I V DD /V SS = 2.5V I V DD /V SS = 2.5V I V DD /V SS = 5V/V I V DD /V SS = 3V/V GIN d H H 8 H 4 H 2 H H k k M M FEQUENCY Hz TPC 3. D52 kω Supply Current vs. Clock Frequency 54 k k k M FEQUENCY Hz TPC. D52 kω Gain vs. Frequency vs. Code 5 45 CODE 55 H 4 8 H H I DD /I SS I V DD /V SS = 2.5V I V DD /V SS = 2.5V GIN d H H 8 H 5 5 I V DD /V SS = 5V/V I V DD /V SS = 3V/V H 2 H H k k M M FEQUENCY Hz TPC 4. D52 kω Supply Current vs. Clock Frequency 54 k k k M FEQUENCY Hz TPC 7. D52 5 kω Gain vs. Frequency vs. Code 8 CODE = 8 H, V = V DD, V = V V DD = 5V DC % p-p C 2 H 8 H PS d 4 V DD = 3V DC % p-p C GIN d H 2 H H 2 V DD = 3V DC % p-p C k k k M FEQUENCY Hz TPC 5. Power Supply ejection atio vs. Frequency 54 k k k M FEQUENCY Hz TPC 8. D52 kω Gain vs. Frequency vs. Code 8

9 D52/D52 GIN d H 8 H 4 H 2 H H NOMLIZED GIN FLTNESS.d/DIV SEE TEST CICUIT CODE = 8 H V DD = 5V T = 25 C 5k k 54 k k k M FEQUENCY Hz TPC 9. D52 5 kω Gain vs. Frequency vs. Code 48 k k k M FEQUENCY Hz TPC 22. Normalized Gain Flatness vs. Frequency GIN d k 5k V IN = mv rms V DD = 5V L = M NOMLIZED GIN FLTNESS.d/DIV SEE TEST CICUIT CODE = H V DD = 5V T = 25 C 5k k 48 k k k M FEQUENCY Hz TPC 2. D52 3 d andwidth 48 k k k M FEQUENCY Hz TPC 23. D52 Normalized Gain Flatness vs. Frequency 2 k GIN d k V (2mV/DIV) V IN = mv rms V DD = 5V L = M CS (5V/DIV) 48 k k k M FEQUENCY Hz TPC 2. D52 3 d andwidth TPC 24. One Position Step Change at Half Scale 9

10 D52/D52 35 OUTPUT (2V/DIV) INPUT (5V/DIV) HEOSTT MODE TEMPCO ppm/ C TPC 25. Large Signal Settling Time TPC 28. D52 / T heostat Mode Temperature Coefficient 3 V OUT (2mV/DIV) POTENTIOMETE MODE TEMPCO ppm/ C TPC 2. Digital Feedthrough vs. Time TPC 29. D52 Potentiometer Mode Temperature Coefficient 4 POTENTIOMETE MODE TEMPCO ppm/ C TPC 27. D52 V / T Potentiometer Mode Temperature Coefficient POTENTIOMETE MODE TEMPCO ppm/ C TPC 3. D52 V / T Potentiometer Mode Tempco

11 D52/D52. Table I. D52 Serial-Data ord Format THEOETICL I MX m.. = k = 5k D7 D D5 D4 D3 D2 D D MS LS Table II. D52 Serial-Data ord Format TPC 3. D52 I MX vs. Code 5* D 5* D4 D3 D2 D D MS LS THEOETICL I MX m = k = 5k TPC 32. D52 I MX vs. Code OPETION The D52/D52 provide 255 and 33 positions digitallycontrolled variable resistor (V) devices. Changing the programmed V settings is accomplished by clocking in an 8-bit serial data word for D52, and a -bit serial data word for D52, into the SDI (Serial Data Input) pins. Table I provides the serial register data word format. The D52/D52 are preset to a midscale internally during power-on condition. In addition, the D52/D52 contain power shutdown SHDN pins that place the DC in a zero power consumption state where the immediate switches next to Terminals and are open-circuited. Meanwhile, the wiper is connected to terminal, resulting in only leakage current consumption in the V structure. During shutdown, the V latch contents are maintained when the DC is inactive. hen the part is returned from shutdown, the stored V setting will be applied to the DC. *Six data bits are needed for 33 positions. POGMMING THE VILE ESISTO heostat Operation The nominal resistance of the DC between Terminals and are available with values of kω and 5 kω. The final two digits of the part number determine the nominal resistance value, e.g., kω = and 5 kω = 5. The nominal resistance ( ) of D52 has 25 contact points accessed by the wiper terminal. The 8-bit data word in the DC latch of D52 is decoded to select one of the 25 possible settings. In both parts, the wiper s first connection starts at the terminal for data H. This -terminal connection has a wiper contact resistance of 5 Ω as long as valid V DD /V SS is applied, regardless of the nominal resistance. For a kω part, the second connection of D52 is the first tap point with 89 Ω [ = /255 + = 39 Ω + 5 Ω] for data H. The third connection is the next tap point representing = 28 Ω for data 2 H. Due to its unique internal structure, D52 has 5-bit + resolution, but needs a -bit data word to achieve the full 33 steps resolution. The -bit data word in the DC latch is decoded to select one of the 33 possible settings. Data 34 to 3 will automatically be equal to Position 33. The wiper H connection of D52 gives 5 Ω. Similarly, for a kω part, the first tap point of D52 yields 33 Ω for data H, 75 Ω for data 2 H. For both D52 and D52, each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached. Figures 2a and 2b show the simplified diagrams of the equivalent DC circuits.

12 D52/D52 D7 D D5 D4 D3 D2 D D SHDN DC LTCH & DECODE S SHDN S 2 N S 2 N 2 S S 2 N DIGITL CICUITY OMITTED FO CLITY Figure 2a. D52 Equivalent DC Circuit. 255 positions can be achieved up to Switch S 2 N. D5 D4 D3 D2 D D SHDN DC LTCH & DECODE S SHDN S 2 N S 2 N S 2 N 2 S S 2 N DIGITL CICUITY OMITTED FO CLITY Figure 2b. D52 Equivalent DC Circuit. Unlike D52, 33 positions can be achieved all the way to Switch S 2 N. The general equation determining the digitally programmed output resistance between and is: D ( D)= + 5 Ω for D52 () 255 D ( D)= + 5 Ω 32 for D52 (2) where: D is the decimal equivalent of the data contained in DC latch. is the nominal end-to-end resistance. is the wiper resistance contributed by the on-resistance of the internal switch. Note D in D52 is between to 255 for 25 positions. On the other hand, D in D52 is between to 32 so that 33 positions can be achieved due to the slight internal structure difference, Figure 2b. gain if = kω and terminal can be opened or tied to, the following output resistance between to will be set for the following DC latch codes: D52 iper-to- esistance D (DEC) ( ) Output State Full-Scale ( + ) Midscale 89 LS 5 Zero-Scale (iper Contact esistance) D52 iper-to- esistance D (DEC) ( ) Output State 32 5 Full-Scale ( + ) 55 Midscale 33 LS 5 Zero-Scale (iper Contact esistance) Note that in the zero-scale condition a finite wiper resistance of 5 Ω is present. Care should be taken to limit the current flow between and in this state to no more than ± 2 m to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the DC replaces, it is totally symmetrical. The resistance between the wiper and Terminal also produces a digitally controlled resistance. hen these terminals are used, the terminal should be tied to the wiper. Setting the resistance value for starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is: ( D)= ( ) 255 D 255 ( ) + 5 Ω for D52 (3) 32 D ( D)= + 5 Ω for D52 (4) 32 Similarly, D in D52 is between to 255, whereas D in D52 is between to 32. For = kω and terminal is opened or tied to the wiper, the following output resistance between and will be set for the following DC latch codes: 2

13 D52/D52 D52 iper-to- esistance D (DEC) ( ) Output State Full-Scale ( ) Midscale LS 5 Zero-Scale ( + ) D52 iper-to- esistance D (DEC) ( ) Output State 32 5 Full-Scale ( ) 55 Midscale 9738 LS 5 Zero-Scale ( + ) The tolerance of the nominal resistance can be ± 3% due to process lot dependance. If users apply the DC in rheostat (variable resistance) mode, they should be aware of such specification of tolerance. The change in with temperature has a 5 ppm/ C temperature coefficient. POGMMING THE POTENTIOMETE DIVIDE Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to- and wiper-to- to be proportional to the input voltage at to. Unlike the polarity of V DD V SS, which must be positive, voltage across,, and can be at either polarity. If ignoring the effects of the wiper resistance for an approximation, connecting terminal to 5 V and terminal to ground produces an output voltage at the wiper which can be any value starting at almost zero to almost full scale with the minor deviation contributed by the wiper resistance. Each LS of voltage is equal to the voltage applied across Terminal divided by the 2 N - and 2 N position resolution of the potentiometer divider for D52 and D52 respectively. The general equation defining the output voltage with respect to ground for any valid input voltage applied to Terminals and is: Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute values; therefore, the drift reduces to 5 ppm/ C. DIGITL INTEFCING The D52/D52 contain a standard three-wire serial input control interface. The three inputs are clock (CLK), CS, and serial data input (SDI). The positive-edge-sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 3 shows more detail of the internal digital circuitry. hen CS is low, the clock loads data into the serial register on each positive clock edge (see Table III). V DD CS CLK SDI GND P-ON PESET D52/D52 SE EG 8/ Dx DC EG Figure 3. lock Diagram V SS SHDN Table III. Input Logic Control Truth Table CLK CS SHDN egister ctivity L L H No S effect. P L H Shift one bit in from the SDI pin. X P H Load S data into DC latch. X H H No operation. X H L Open circuit on terminal and short circuit between to terminals. NOTE P = positive edge, X = don t care, S = shift register. ll digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 4. pplies to digital input pins CS, SDI, SHDN, CLK. V D ( D)= V + V 255 for D52 (5) 34 LOGIC V D ( D)= V + V 32 for D52 () V SS Figure 4. ESD Protection of Digital Pins where D in D52 is between to 255 and D in D52 is between to 32. For more accurate calculation, including the effects of wiper resistance, V can be found as: ( ) ( ) (7) V D D D ( )= V + V where (D) and (D) can be obtained from Equations to 4.,, V SS Figure 5. ESD Protection of esistor Terminals 3

14 D52/D52 TEST CICUITS Figures to 4 define the test conditions used in the product specification table. OP279 5V V OUT V+ DUT V+ = V DD LS = V+/2 N V MS OFFSET GND V IN DUT OFFSET IS Figure. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure. Noninverting Gain Test Circuit NO CONNECT DUT V MS I OFFSET GND V IN 2.5V +5V OP42 5V V OUT Figure 7. esistor Position Nonlinearity Error (heostat Operation; -INL, -DNL) Figure 2. Gain vs. Frequency Test Circuit DUT S =.V I S V MS2 DUT I = V DD / NOMINL V I S CODE = OO H +.V V MS V SS TO V DD = [V MS V MS2 ]/I Figure 8. iper esistance Test Circuit Figure 3. Incremental ON esistance Test Circuit NC V V+ V DD V MS V+ = V DD % PS (d) = 2 LOG V MS V DD V MS % PSS (%/%) = V DD % V DD DUT V SS GND NC NC = NO CONNECT I CM V CM Figure 9. Power Supply Sensitivity Test Circuit (PSS, PS) Figure 4. Common-Mode Leakage Current Test Circuit DUT 5V OFFSET GND V IN OP279 V OUT OFFSET IS Figure. Inverting Gain Test Circuit 4

15 D52/D52 DIGITL POTENTIOMETE SELECTION GUIDE Number esolution Power of Vs Terminal Interface Nominal (Number Supply Part per Voltage Data esistance Of iper Current Number Package ange Control (k ) Positions) (I DD ) Packages Comments D52 ± 3 V, +5.5 V 3-ire, 5 33 µ µsoic- Full C Specs, Dual Supply, Pwr-On-eset, Low Cost D V Up/Down, 5, 28 4 µ PDIP, SO-8, µsoic-8 No ollover, Pwr-On-eset D737 ± 5 V, +28 V 3-ire, 5,, 28 µ PDIP-4, SOL-, Single 28 V or Dual ± 5 V TSSOP-4 Supply Operation D52 ± 3 V, +5.5 V 3-ire, 5 25 µ µsoic- Full C Specs, Dual Supply, Pwr-On-eset D V 3-ire,, 5, 25 5 µ SO-8 Full C specs D524* ± 3 V, +5.5 V 2-ire,, 25 5 µ SO-4, TSSOP-4 I 2 C-Compatible, TC < 5 ppm/ C D523* ± 3 V, +5.5 V 3-ire, 5, 24 µ TSSOP- Nonvolatile Memory, Direct Program, I/D, ± d Settability D ± 3 V, +5.5 V Up/Down, 5,, 28 8 µ SO-4, TSSOP-4 No ollover, Stereo, Pwr-On- eset, TC < 5 ppm/ C D V 3-ire,, 5, 25 5 µ PDIP, SO-4, Full C Specs, n TSSOP-4 Shutdown Current D5232* 2 ± 3 V, +5.5 V 3-ire, 5, 25 µ TSSOP- Nonvolatile Memory, Direct Program, I/D, ± d Settability D5242* 2 ± 3 V, +5.5 V 2-ire,, 25 5 µ SO-, TSSOP- I 2 C-Compatible, TC < 5 ppm/ C D522* 2 ± 5 V, +2 V 3-ire, 5, 25 µ TSSOP- Medium Voltage Operation, TC < 5 ppm/ C D V 3-ire, 4 5 µ PDIP, SOL-24, Full C specs, n TSSOP-24 Shutdown Current D5233* 4 ± 3 V, +5.5 V 3-ire, 5, 4 µ TSSOP- Nonvolatile Memory, Direct Program, I/D, ± d Settability D524 4 ± 3 V, +5.5 V 3-ire, 5, 25 5 µ PDIP, SOL-24, Full C Specs, Dual Supply, TSSOP-24 Pwr-On-eset D V 3-ire,, 5, 25 5 µ PDIP, SOL-24, Full C Specs, n TSSOP-24 Shutdown Current D52 ± 3 V, +5.5 V 3-ire, 5, 25 5 µ PDIP, SOL-24, Full C Specs, Dual Supply, TSSOP-24 Pwr-On-eset *Future product, consult factory for latest status. 5

16 D52/D52 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead SOIC (M-).24 (3.5).2 (2.84).24 (3.5).2 (2.84) 5.99 (5.5).87 (4.75) C288 8/().38 (.97).3 (.7) PIN.97 (.5) SC.22 (3.). (2.79). (.5). (.4).2 (.5). (.5).43 (.9).37 (.94) SETING PLNE. (.28).3 (.8).2 (3.5).2 (2.84).22 (.5).2 (.53) evision History Location Page Data Sheet changed from EV. to. Edits to ODEING GUIDE / Data Sheet changed from EV. O to EV.. Edits to ODEING GUIDE Edits to SOLUTE MXIMUM TINGS TPCs 3 and 32 added PINTED IN U.S..