Features INVERTING. 0.6mA OUTA INA NONINVERTING INVERTING. 0.6mA NONINVERTING

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1 MIC//8 MIC//8 Dual 1.-Peak Low-Side MOSFET Driver Final Information General Description The MIC//8 family are highly-reliable dual lowside MOSFET drivers fabricated on a icmos/dmos process for low power consumption and high efficiency. These drivers translate TTL or CMOS input logic levels to output voltage levels that swing within mv of the positive supply or ground. Comparable bipolar devices are capable of swinging only to within 1V of the supply. The MIC//8 is available in three configurations: dual inverting, dual noninverting, and one inverting plus one noninverting output. The MIC//8 are pin-compatible replacements for the MIC//8 and MIC1/1/18 with improved electrical performance and rugged design (Refer to the Device Replacement lists on the following page). They can withstand up to m of reverse current (either polarity) without latching and up to V noise spikes (either polarity) on ground pins. Primarily intended for driving power MOSFETs, MIC//8 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak current, and fast switching time. Other applications include driving heavily loaded clock lines, coaxial cables, or piezoelectric transducers. The only load limitation is that total driver power dissipation must not exceed the limits of the package. Features ipolar/cmos/dmos construction Latch-up protection to >m reverse current 1.-peak output current.v to 18V operating range Low quiescent supply current m at logic 1 input µ at logic input Switches 1pF in ns Matched rise and rall times Ω output impedance < ns typical delay Logic-input threshold independent of supply voltage Logic-input protection to V pf typical equivalent input capacitance mv max. output offset from supply or ground Replaces MIC//8 and MIC1/1/18 Dual inverting, dual noninverting, and inverting/ noninverting configurations ESD protection pplications MOSFET driver Clock line driver Coax cable driver Piezoelectic transducer driver Functional Diagram.1m.m INVERTING OUT IN kω NONINVERTING.1m.m INVERTING kω NONINVERTING GND, Inc. 189 Fortune Drive San Jose, C 9131 US tel + 1 (8) 9-8 fax + 1 (8) September MIC//8

2 MIC//8 Ordering Information Part Number Temperature Range Package Configuration MICM C to +1 C 8-lead SOIC Dual Inverting MICM C to +8 C 8-lead SOIC Dual Inverting MICMM C to +8 C 8-lead MSOP Dual Inverting MICN C to +8 C 8-lead Plastic DIP Dual Inverting MICM C to +1 C 8-lead SOIC Dual Noninverting MICM C to +8 C 8-lead SOIC Dual Noninverting MICMM C to +8 C 8-lead MSOP Dual Noninverting MICN C to +8 C 8-pin Plastic DIP Dual Noninverting MIC8M C to +1 C 8-lead SOIC Inverting + Noninverting MIC8M C to +8 C 8-lead SOIC Inverting + Noninverting MIC8MM C to +8 C 8-lead MSOP Inverting + Noninverting MIC8N C to +8 C 8-lead Plastic DIP Inverting + Noninverting MIC//8 Device Replacement Discontinued Number Replacement MICCM MICM MICM MICM MICCN MICN MICN MICN MICCM MICM MICM MICM MICCN MICN MICN MICN MIC8CM MIC8M MIC8M MIC8M MIC8CN MIC8N MIC8N MIC8N MIC1/1/18 Device Replacement Discontinued Number Replacement MIC1CM MICM MIC1M MICM MIC1CN MICN MIC1N MICN MIC1CM MICM MIC1M MICM MIC1CN MICN MIC1N MICN MIC18CM MIC8M MIC18M MIC8M MIC18CN MIC8N MIC18N MIC8N Pin Configuration MIC MIC MIC MIC MIC8 MIC8 IN 1 8 OUT IN 1 8 OUT IN 1 8 OUT GND 3 GND 3 GND 3 Dual Inverting Dual Noninverting Inverting + Noninverting Pin Description Pin Number Pin Name Pin Function 1, 8 not internally connected IN Control Input : TTL/CMOS compatible logic input. 3 GND Ground Control Input : TTL/CMOS compatible logic input. Output : CMOS totem-pole output. Supply Input: +.V to +18V OUT Output : CMOS totem-pole output. MIC//8 September 1999

3 MIC//8 bsolute Maximum Ratings (Note 1) Supply Voltage ( )...+V Input Voltage (V IN ) V to GND V Junction Temperature (T J )... 1 C Storage Temperature... C to +1 C Lead Temperature (1 sec.)... 3 C ESD Rating, Note 3 Operating Ratings (Note ) Supply Voltage ( )... +.V to +18V Temperature Range (T ) ()... C to +1 C ()... C to +8 C Package Thermal Resistance PDIP θ J C/W PDIP θ JC... C/W SOIC θ J... 1 C/W SOIC θ JC... C/W MSOP θ JC... C/W Electrical Characteristics.V V s 18V; T = C, bold values indicate full specified temperature range; unless noted. Symbol Parameter Condition Min Typ Max Units Input V IH Logic 1 Input Voltage. 1. V. 1. V V IL Logic Input Voltage V 1..8 V I IN Input Current V IN 1 1 µ Output V OH High Output Voltage. V V OL Low Output Voltage. V R O Outpuesistance I OUT = 1m, 1 Ω 8 1 Ω I PK Peak Output Current 1. I Latch-Up Protection withstand reverse current > m Switching Time Rise Time test Figure ns ns t F Fall Time test Figure 1 1 ns 9 ns t D1 Delay Tlme test Flgure ns 19 ns t D Delay Time test Figure 1 3 ns ns t PW Pulse Width test Figure 1 ns Power Supply I S Power Supply Current V IN = V = 3.V 1.. m 1. 8 m I S Power Supply Current V IN = V =.V.18. m.19. m Note 1. Note. Note 3. Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Devices are ESD sensitive. Handling precautions recommended. September MIC//8

4 MIC//8 Test Circuits.1µF.µF.1µF.µF IN MIC OUT 1pF IN MIC OUT 1pF 1pF 1pF Figure 1a. Inverting Configuration Figure a. Noninverting Configuration V INPUT 9% 1% V t PW.V V INPUT 9% 1% V t PW.V 9% t D1 t F t D 9% t D1 t D t F OUTPUT OUTPUT 1% V 1% V Figure 1b. Inverting Timing Figure b. Noninverting Timing MIC//8 September 1999

5 MIC//8 Electrical Characteristics Rise and Fall Time vs. Supply Voltage C L = 1pF T = C 3 3 Delay Time vs. Supply Voltage C L = 1pF T = C Rise and Fall Time vs. Temperature C L = 1pF 3 t 1 F 1 1 SUPPLY VOLTGE (V) Delay Time vs. Temperature 3 C L = 1pF 3 t D t D TEMPERTURE ( C) SUPPLY CURRENT (m) SUPPLY VOLTGE (V) Supply Current vs. Capacitive Load 8 T = C 3 1 t D1 t D khz khz khz CPCITIVE LOD (pf) TEMPERTURE ( C) 1k 1 1 Rise and Fall Time vs. Capacitive Load T = C CPCITIVE LOD (pf) t F t F SUPPLY CURRENT (m) Supply Current vs. Frequency High Output vs. Current Low Output vs. Current T = C T = C V C = V T = C = V C L = 1pF V 1 V V V (V) S OUT V 1 V OUTPUT VOLTGE (V) V 1 V FREQUEY (khz) CURRENT SOURCED (m) CURRENT SUNK (m). Quiescent Power Supply Current vs. Supply Voltage Quiescent Power Supply Current vs. Supply Voltage 1 Package Power Dissipation SUPPLY CURRENT (m) NO LOD OTH INPUTS LOGIC "1" T = C SUPPLY CURRENT (µ) NO LOD OTH INPUTS LOGIC "" T = C MXIMUM PCKGE POWER DISSIPTION (mw) 1 SOIC PDIP 1 1 SUPPLY VOLTGE (V) 1 1 SUPPLY VOLTGE (V) MIENT TEMPERTURE ( C) September 1999 MIC//8

6 MIC//8 pplications Information Supply ypassing Large currents are required to charge and discharge large capacitive loads quickly. For example, changing a 1pF load by 1V in ns requires.8 from the supply input. To guarantee low supply impedance over a wide frequency range, parallel capacitors are recommended for power supply bypassing. Low-inductance ceramic MLC capacitors with short lead lengths (<.") should be used. 1.µF film capacitor in parallel with one or two.1µf ceramic MLC capacitors normally provides adequate bypassing. Grounding When using the inverting drivers in the MIC or MIC8, individual ground returns for the input and output circuits or a ground plane are recommended for optimum switching speed. The voltage drop that occurs between the driver s ground and the input signal ground, during normal high-current switching, will behave as negative feedback and degrade switching speed. Control Input Unused driver inputs must be connected to logic high (which can be ) or ground. For the lowest quiescent current (< µ), connect unused inputs to ground. logic-high signal will cause the driver to draw up to 9m. The drivers are designed with 1mV of control input hysteresis. This provides clean transitions and minimizes output stage current spikes when changing states. The control input voltage threshold is approximately 1.V. The control input recognizes 1.V up to as a logic high and draws less than 1µ within this range. The MIC//8 drives the TL9, SG1/, MIC38C, TSC1 and similar switch-mode power supply integrated circuits. Power Dissipation Power dissipation should be calculated to make sure that the driver is not operated beyond its thermal ratings. Quiescent power dissipation is negligible. practical value for total power dissipation is the sum of the dissipation caused by the load and the transition power dissipation (P L + P T ). Load Dissipation Power dissipation caused by continuous load current (when driving a resistive load) through the driver s output resistance is: P L = I L R O For capacitive loads, the dissipation in the driver is: P L = f C L V S Transition Dissipation In applications switching at a high frequency, transition power dissipation can be significant. This occurs during switching transitions when the P-channel and N-channel output FETs are both conducting for the brief moment when one is turning on and the other is turning off. P T = f Q Charge (Q) is read from the following graph: CHRGE (Q) SUPPLY VOLTGE (V) Crossover Energy Loss per Transition MIC//8 September 1999

7 MIC//8 Package Information. (.) MX) PIN 1.1 (3.99).1 (3.81) DIMENSIONS: IHES (MM). (1.) TYP. (.1).13 (.33).98 (.9). (.1).1 (.). (.18). (1.3). (1.1).19 (.) (.8) SETING PLNE 8-lead SOP (M). (1.).1 (.). (.).8 (.9).1 (3.1).11 (.8).199 (.).18 (.) DIMENSIONS: IH (MM).1 (3.).11 (.9).3 (.9).3 (.81).3 (1.9).38 (.9).1 (.3) R. (.18). (.13).1 (.3). (.) TYP.8 (.). (.1) MX MIN 8-lead MM8 MSOP (MM).1 (.3) R.39 (.99).3 (.89).1 (.3) PIN 1 DIMENSIONS: IH (MM).38 (9.).3 (9.).13 (3.3).1 (3.18). (.8). (.).3 (.).13 (.33).1 (.).18 (.).1 (.).13 (3.3).3 (.9).38 (9.).3 (8.13) 8-lead Plastic DIP (N) September 1999 MIC//8

8 MIC//8 MICREL I. 189 FORTUNE DRIVE SN JOSE, C 9131 US TEL + 1 (8) 9-8 FX + 1 (8) 9-9 WE This information is believed to be accurate and reliable, however no responsibility is assumed by for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Inc Incorporated MIC//8 8 September 1999