Introduction to CMOS. Dr. Lynn Fuller

Transcription

1 MICROELECTRONIC ENINEERIN ROCHETER INTITUTE OF TECHNOLOY Itroductio to CMO Dr. Ly Fuller Webage: htt://eole.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY Tel (585) Fax (585) Deartmet webage: htt:// LEC_CMO.t Page 1

2 OUTLINE Trasistor Termiology -Tye MOFETs -Tye MOFETs Trasistor Characteristics ub Threshold Characteristics Chael Legth Modulatio Effective Chael Legth hort Chael Effect o Vt CMO Digital Buildig Blocks -well CMO N-well CMO Dual Well / Quad Well Latch-U Page 2

3 TRANITOR TERMINOLOY FET - Field Effect Trasistor IFET - Isulated ate FET MOFET - Metal Oxide emicoductor FET MNOFET - Metal Nitride Oxide emicoductor AFET - elf Aliged ate FET JFET - Juctio FET MEFET - Metal Eitaxy emicoductor FET (chottky Barrier Juctio FET) FET - -tye MOFET FET - -tye MOFET ENHANCEMENT MODE MOFET DEPLETION MODE MOFET Page 3

4 TRANITOR TERMINOLOY (CONTINUED) MOFET Device Parameters: THREHLD VOLTAE, Vt TRANCONDUCTANCE, gm MOFET ATURATION REION - larger values of Vds NON ATURATION REION - low values of Vds UBTHREHOLD REION - Vgs lower tha Vt CMO - Comlemetary MO P-WELL CMO N-WELL CMO Dual Well, Quad Well Page 4

5 TYPE OF -tye MOFET ate Drai ub ource Ehacemet ate Drai ub ource Deletio ource is the source of electros, Drai is the drai of electros. Poly ate, Ehacemet - elf Aliged ate Techology - Poly ate, Deletio- elf Aliged ate Techology D -well -substrate D -well CMO Metal ate, Ehacemet - Overlaig ate Techology - Metal ate, Deletio - Overlaig ate Techology Page 5

6 TYPE OF -tye MOFET ate Drai ub ource Ehacemet ate Drai ub ource Deletio ource is the source of holes, Drai is the drai of holes. Poly ate, Ehacemet - elf Aliged ate Techology - Poly ate, Deletio- elf Aliged ate Techology D -well -substrate D -well CMO Metal ate, Ehacemet - Overlaig ate Techology - Metal ate, Deletio - Overlaig ate Techology Page 6

7 MOFET ID-VD CHARACTERITIC FAMILY OF CURVE +I +I +5 g ate Ehacemet ate Deletio Drai ub ource Drai ub ource -I -I -5 -Vg V ate Ehacemet V ate Deletio Drai ub ource Drai ub ource Page 7

8 NON ATURATION REION CHARACTERITIC + Vgs - +Id D Id Vto Vsub Vd = 0.1 Volt Vsub = volts g Body Effect +Ids No aturatio Regio Vsub MOFET with Vt=1, sice the Drai is at 0.1 volts ad the source is at zero. Both drai ad source will be o at gate voltages greater tha 1.1 volt. the trasistor will be i the o saturatio regio. D gs ds Page 8

9 ATURATION REION CHARACTERITIC +Id D Id Vto + Vgs=Vds - Vsub Vsub = 0 I Dsat = µw Cox (Vg-Vt) 2 2L volts g Body Effect +Ids aturatio Regio gs Vsub ds D MOFET with Vt=1, Drai ed is ever o because Voltage ate to Drai is Zero. Therefore this trasistor is always i aturatio Regio if the gate voltage is above the threshold voltage. Page 9

10 UB-THREHOLD CHARACTERITIC D Id + Vgs=Vds - The sub-threshold characteristics are imortat i VLI circuits because whe the trasistors are off they should ot carry much curret sice there are so may trasistors. (tyical ub Vt loe value about 100 mv/decade, tyical ub Vt wig about 6 to 12 decades of curret) ub Vt wig (Ams) Id (Ams) Lights O Vt ub Vt loe (mv/dec) Vgs Page 10

11 UBTHREHOLD CHARACTERITIC The major arameter that affects the sub-threshold characteristics is the distace betwee the gate ad the carriers i the chael. The ate oxide thickess is oe art of this distace. The other art is the locatio of the carriers i the silico. I some devices they are at the surface (called surface chael devices) makig the distace equal to the oxide thickess oly ad givig the best sub-threshold characteristics. I devices that have received a io imlated Vt adjust with a doat of the oosite tye from the substrate doat the resultig chael has a eergy miimum away from the surface where the carriers move, givig oorer sub-threshold characteristics. Reducig gate oxide thickess imroves sub-threshold characteristics. Page 11

12 URFACE CHANNEL / BURIED CHANNEL FET Whether a MOFET requires a threshold adjust imlat deeds o the details of the threshold voltage calculatio, icludig the oxide thickess, substrate doig, gate material work fuctio, surface state desity, etc. A buried chael device will result if the threshold adjust imlat is the oosite tye from the substrate. The carriers will flow from source to drai at a low eergy regio some small distace away from the surface. The buried chael trasistor erformace is oorer. The referece is to desig the trasistors to be surface chael devices. Oe techique is to egieer the gate material work fuctio by usig + oly gates o trasistors ad + oly gates o trasistors. Page 12

13 HORT/LON CHANNEL MOFET Log-chael MOFET is defied as devices with width ad legth log eough so that edge effects from the four sides ca be eglected Chael legth L must be much greater tha the sum of the drai ad source deletio widths L L L Log Chael Device hort Log Page 13

14 Built i Voltage: WIDTH OF PACE CHARE LAYER Width of ace Charge Layer, W o lightly doed side: Maximum Electric Field: Examle: Y o = l (3E16/1.45E10) = Wsc = [ (2(11.7)(8.85E-14)/1.6E-19) (0.928) (1/3E16 )] 1/2 = 0.20 µm or V R =3V Eo = - [(2(8.85E-14(11.7))( )(3E16)] 1/2 =-1.92E5 V/cm ε = Rochester ε o ε r Istitute = 8.85E-12 of Techology(11.7) F/m 8.85E-14 (11.7) F/cm Ψ ο = KT/q l (N /i) Wsc= [ (2ε/q) (Ψ ο R ) (1/N )] 1/2 Ε ο = - [(2q/ε) (Ψ ο R ) (N )] 1/2 L Leff Wsc Log Chael Behavior Note: Eomax = 3E5 V/cm Page 14

15 TERADA-MUTA METHOD FOR EXTRACTIN Leff ad Rds Terada-Muta Method for Leff ad Rds I the liear regio (V D is small): I D = µw Cox (Vgs-Vt-V d /2) V D Leff 1/Rm Leff = Lm - DL where DL is correctio due to rocessig Lm is the mask legth Rm = V D /I D = measured resistace = Rds + (Lm - DL)/ µw Cox (Vgs-Vt) 0 I D = 1/R m V D Masured Resistace, Rm Rds Vg = -6 Vg = -8 Vg = -10 Lm (mask legth) DL so measure Rm for differet chael legth trasistors ad lot Rm vs Lm where Rm = itersect fid value for DL ad Rds The Leff ca be calculated for each differet legth trasistor from Leff = Lm - DL Page 15

16 TERADA-MUTA METHOD FOR EXTRACTIN Leff ad Rds V VD RD R Rsd (Ohms) R D = 530 W? L ~ 0.3 µm V-VT=0.5V V-VT=1.0V V-VT=1.5V L eff = L mask?l L eff = 0.5 µm 0.3 µm L eff = 0.2 µm V Lmask (µm) L eff & R D extractio for Trasistors Liear Regio: V D = 0.1V V -V T >> I D R D At low I D, V RD small Rm = Vd = R D + (L mask -? L) Id µcox W(V -V t ) Plot R m vs. L mask for differet (V -V t ) Page 16

17 CHANNEL LENTH MODULATION Chael Legth Modulatio Parameter l l = loe/ Idsat Vg L - DL L Vd2 Vd1 Vd loe +Ids Idsat Vd1 aturatio Regio gs Vd2 ds I Dsat = µw Cox (Vg-Vt) 2 (1+ lvds) 2L Trasistor i aturatio Regio DC Model, l is the chael legth modulatio arameter ad is differet for each chael legth, L. Tyical value might be 0.02 Page 17

18 UBTRATE (WELL) DOPIN The drai ad source form juctios with the substrate. The size of the sace charge layer associated with the juctio deeds o the doig of the substrate. The lighter the doig the bigger the sace charge layer. I sub-micro MOFETs the sace charge layer must be small so the substrate doig must be higher. There are tradeoffs that make the choice of substrate doig difficult to ick for all desirable coditios. This leads to the selectio of twi well or quad well CMO techologies where the substrate doig ca be otimized for each tye of trasistor. (,, NPN, PNP) Page 18

19 HORT CHANNEL EFFECT ON Vt A Test Chi is used that icludes MO ad MO trasistors of various legths from 0.1 µm to 5.0 µm ad the threshold voltage is lotted versus chael legth. The threshold voltage eeds to be high eough so that whe the iut is zero or suly the trasistor curret is may decades lower tha whe it is o. Vt, sub-vt sloe, sub-vt swig ad ower suly voltages determie erformace of MOFETs i CMO circuits. THREHOLD VOLTAE VOLT ATE LENTH, µm ource ace Charge ate Drai ace Charge Page 19

20 PUNCH THROUH AND HALLOW JUNCTION Puch-through is a coditio where the sace charge layers associated with the drai ad source juctios touch. The size of the sace charge layer deeds o substrate doig ad the value for juctio bias. To icrease the drai voltage at which uch through occurs for a MOFET we ca icrease the substrate doig. I additio submicro MOFETs have better uch-through characteristics whe the drai ad source juctios are shallow. ource ubstrate or Well ate V D = 3, 5 volts ace Charge Layer at 3 ad 5 volts Page 20

21 PUNCHTHROUH Page 21

22 HOT CARRIER, LOW DOPED DRAIN (LDD), IDE WALL PACER For submicro chael legth devices the electric field (drai source voltage divided by the chael legth) aroaches 10 millio V/m. At these high electric fields the carriers have lots of eergy (called hot ) ad at these eergies they ca eetrate ito the gate oxide where they ca cause shifts i threshold voltage. By reducig the doig i the drai of a trasistor a series drai resistace ca be created to realize a voltage dro ad rovide for a lower electric field across the chael. This structure is called a low doed drai ad is ofte created usig self aliged side wall sacers ad a two ste io imlat for the drai ad source. Low Doed ilicide ide wall acer Drai ate Field Oxide ource Drai to P-tye well P-tye Puch Through Imlat Page 22

23 CMO INVERTER Vi Idd Vout Vout Voh Vi Vout Imax Idd CMO TRUTH TABLE VIN VOUT VoL 0 0 ViL Vih Vi D 0 oise margi = ViL - Voh D 1 oise margi = Voh - Vih Page 23

24 OTHER INVERTER REALIZATION -V V 0 VOUT VERU VIN -V 0 0 VIN VO VIN VO VIN VO VIN VO VIN VO WITCH CMO ENHANCEMENT LOAD ENHANCEMENT LOAD DEPLETION LOAD Page 24

25 NOR ATE VA VB YMBOL VOUT V V TRUTH TABLE VA VB VOUT R R VOUT VOUT VOUT VA VB VA VB VA VB VOUT WITCH REITOR LOAD LOAD VA VB CMO Page 25

26 NAND ATE VA R VA VB WITCH YMBOL VOUT VB VA VOUT R V VOUT VB REITOR LOAD VA V LOAD VOUT VB TRUTH TABLE VA VB VOUT VA CMO VOUT VB Page 26

27 P-WELL CMO Drai Drai ate ub ource D YMBOL ate D ub ource + CROECTION + +I g -I -Vg CHARACTERITIC -V Page 27

28 P-WELL CMO CROECTION 6000Å + Poly 6000Å CVD Ox 1 µm Alumium -well 10,000Å Field Ox D/ 4e15, 100KeV P31 thru gate Oxide -well 4e12, 50 kev, B11, 1123 C, 20 hr field Vt adj 8e13 B11, 100KeV Bare + D/ 4e15, 120 KeV BF2 ito bare silico Vt adj mos 2e12, 60 KeV B11, 1000Å Kooi Vt adj mos 5e11, 60 kev Blaket, 1000Å Kooi Page 28

29 N-WELL CMO Drai Drai ate ub ource D YMBOL ate D ub ource + CROECTION + +I g -I -Vg CHARACTERITIC -V Page 29

30 DUAL WELL CMO D D ei substrate CROECTION Page 30

31 BICMO Biolar D D B E C substrate - ei CROECTION Page 31

32 QUAD WELL CMO D + substrate D - ei Biolar B E C Biolar C E B + + P + CROECTION Page 32

33 LATCH-UP Vss D D R-well vertical Lateral Vdd -ubstrate R-ub ub CROECTION Page 33

34 LATCH-UP MODEL / PROTECTION Lateral R-well Vdd R-ub vertical Biolar Beta oilig Icrease lateral base width decreasig beta large well to active distace desig rules* dee trech icreases base width Retrograde well reduces vertical trasort decreasig vertical beta Biolar Decoulig Reduce substrate resistace by usig - o + ei Reduce well resistace by usig buried layer ilico o isulator techology uard rigs reduce substrate or well resistace Vss * used for RIT CMO ic s Page 34

35 REFERENCE 1. Itroductio to VLI ystems, Carver Mead ad Ly Coway, Addiso-Wesley Publishig Comay, Aalog VLI Desig - MO ad CMO Malcomb R. Haskard ad Ia C. May, Pretice Hall Publishig Comay. 3. Priciles of CMO VLI Desig - A ystems Persective, Neil Weste, ad Kama Eshraghia, Addiso-Wesley Publishig Comay, CMO Aalog Circuit Desig, Philli E. Alle ad Douglas R. Holberg, Holt, Riehart ad Wisto Publishers, Page 35

36 HOMEWORK - INTRO TO CMO 1. What is the mai advatage of MO techology over Biolar techology? 2. What is the mai advatage of CMO techology? 3. What is the sigificace of the sub threshold sloe? 4. What hysical arameters cotrol the sub threshold sloe? 5. What is the differece betwee chael legth ad effective chael legth? 6. ive a brief exlaatio for latch-u. How is latch-u avoided i RIT s -well CMO circuits? 7. ive some reasos for the selectio of the followig techologies: a) -well, b) -well, c) dual well, d) quad well. Page 36