0.5 V Supply Voltage Reference Based on the MOSFET ZTC Condition

Transcription

1 0.5 V Supply Voltage eference Based on the MOSFET ZTC Condition David Cordova NSCAD Microeltrônica david@nscad.org.br Sergio Bampi bampi@inf.ufrgs.br Pedro Toledo NSCAD Microeltrônica toledo@nscad.org.br Eric Fabris NSCAD Microeltrônica fabris@inf.ufrgs.br Hamilton Klimach hamilton.klimach@ufrgs.br ABSTACT The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and F circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-toabsolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-v T, low-v T, and zero-v T ), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mv. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 ua of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/ C in a temperature range from -55 to 125 C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses mm 2 of silicon area. Categories and Subject Descriptors B.4 [Very Large Scale Integration Design]: Analog and Mixed-Signal Circuits Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. equest permissions from Permissions@acm.org. SBCCI 15, August 31 - September 04, 2015, Salvador, Brazil 2015 ACM. ISBN /15/08 $15.00 DOI: General Terms Design Keywords Voltage reference, Schottky diode, Zero temperature coefficient. 1. INTODUCTION As the dimensions of thin-oxide transistors scale, the supply voltage for these most aggressively scaled devices needs to be reduced below 1 V in order to limit the electrical fields and guarantee sufficient device reliability. These effects of technology and power supply scaling still provide significant density and cost improvements for digital circuits. The design of analog and F CMOS circuits wich can take advantage of highly scaled devices is an open area of research [1]. That is the case of the voltage references operating with ultra-low voltage supplies, which have been the subject of much research in CMOS design in the recent years [2]. Many strategies have been explored to allow the reduction of the voltage references supply voltage, like the use of Schottky diodes instead of PN junction diodes [3, 4], since the former ones present lower forward bias voltage (0.2 to 0.4 V) than the last ones (0.5 to 0.6 V) for the same current density, being both diodes compatible with current CMOS processes. The mutual compensation of the mobility and the threshold voltage temperature dependencies, known as the MOS- FET zero-temperature coefficient (ZTC), has also been used to design voltage references [5], [6, 7]. This paper proposes a 0.5 V supply voltage reference based on the MOSFET ZTC condition, where a proportional-toabsolute-temperature (PTAT) current is used to bias a diodeconnected MOS transistor in the vicinity of and below the ZTC bias point for the gate-to-bulk voltage. The PTAT current reference is implemented using Schottky diodes aiming at low voltage supply operation. The paper is organized as follows: Section II presents and analyses the MOSFET ZTC condition. In Section III, the design of the reference circuit is presented and simulation results are shown in Section IV. Section V draws the main conclusions from this work.

2 2. MOSFET ZTC CONDITION MODELING The drain current MOSFET ZTC condition derives from the mutual cancellation of the mobility and threshold voltage dependencies on temperature, which happens at a particular gate-to-bulk voltage bias of the MOSFET. The drain current ZTC operating bias point was first defined in [5] and later in other publications, always based on the strong inversion quadratic MOSFET model, which is simplified. From [5], the ZTC operating point is given by Eqs. (1) and (2). V GZ = V T 0(T 0) + nv SB α VT 0 T 0 (1) Drain Current (ua) ( a) 10 I D / W =15μ A /μ m V GZ,SVT =420 mv 125 C C 55 C Gate Voltage (V) L=1μ m IDZ J DZ = (W/L) = µn(t0)t 0 2 C ox αv 2 2n T 0 (2) where T 0 is the room temperature, V T 0(T 0) is the threshold voltage at room temperature, n is the slope factor, V SB is the source-bulk voltage, α VT 0 is the thermal coefficient of the threshold voltage (stressing that V T decreases with T ), µ n(t 0) is the low field mobility at room temperature, C ox is the oxide capacitance per unit of area and W is the L transistor aspect ratio. J DZ can be defined as ZTC normalized drain-current and one can readily conclude that V GZ and J DZ are only dependent on device fabrication processes. Fig. 1 (a) shows the drain current (in a log scale) as a function of the gate-bulk voltage (V GB) of a saturated longchannel NMOSFET, simulated under temperatures ranging from 55 o C to +155 o C, for a standard-v T nmos transistor transistor in a commercial 130nm CMOS process. The ZTC operation point can be seen around V GB 420mV for a transistor with V T = 160mV and L = 1um, resulting that the ZTC point occurs for an overdrive voltage around 260 mv, meaning the transistor operates in moderate to strong inversion. In a more general analysis we can suppose that the ZTC condition can also occur in moderate inversion, such as the one presented in [8], where a more complete MOSFET model was used [9]. From this MOSFET model, the ZTC operation condition was investigated from this set of Eqs. (3), (4), (5), (6), (7) and (8). I D = I F I = I S(i f i r) (3) I S = µ nc oxn φ2 t 2 W L = W ISQ L V P V S(D) = φ tf(i f(r) ) (4) f(i f(r) ) = [ 1 + i f(r) 2 + ln ( 1 + i f(r) 1 )] (5) V P = VG VT 0(T ) n V T 0(T ) = V F B + 2φ F + γ 2φ F (6) V T 0(T ) = V T 0(T 0) α VT 0 (T T 0) (7) ( T µ n(t ) = µ n(t 0) T 0 ) αµ (8) where I F () is the forward (reverse) current, i f(r) is the forward (reverse) inversion coefficient, I S is the normalization current, φ t is the thermal voltage, V P is called the pinch- Gate Voltage (mv) ( b) α VT = 0.45mV / C β Z = 3.33μ V / C Δ I D >0 Δ I D =0 Δ I D <0 300 Figure 1: (a) ZTC condition for an NMOS transistor in a 130 nm process, and (b) V GB(T ) for I d > 0, I d = 0 and I d < 0. off voltage, γ is the body effect coefficient, V F B is the flat band voltage, and φ F is the Fermi potential at the bulk of the semiconductor under the transistor channel. Eqs. (5) and 6) relate the source and drain inversion coefficients (forward and reverse), i f,r, with external voltages applied, V G, V S and V D, using the bulk terminal as the reference. egarding the first order temperature dependence of V T 0 and µ n, α VT 0 presents a dependence for wide ranges of doping concentration (N a) and oxide thickness (t ox) and α µ is the temperature dependence power coefficient for the mobility model. From [8], if one derives the drain current expression for temperature in the saturation region (i r << i f ), the condition for which its temperature dependence is negligible can be found, i.e., ( I D)/( T ) T =T1 = 0. Using the Eqs. (3) to (8) and after some analytical work, we can derive that: ( ) ( ) α VT 0 q αµ + 2 i fz = + nk ifz 1 [ ( 1 + ifz 2 + ln 1 + ifz 1)] where k is the Boltzmann constant, q is the elementary electric charge, and i fz is defined as the ZTC forward inversion level. Eq. (9) interpretation is such that if the transistor is biased such that the inversion level at the source is i fz, the drain current is insensitive to temperature. Now using the assumption α µ 2 [5] along with Eq. (9) and (5), a simple expression for the ZTC gate-bulk voltage (V GZ - (9)

3 related to i fz ) is found. V GZ = V T 0(T 0) + nv S α VT 0 T 0 (10) Eq. (10) presents the same result already derived from the strong inversion quadratic model in Eq. (1). The ZTC drain-current, related to i fz, can be found using Eq. (3) under the saturation condition i f >> i r : I DZ (W/L) = JDZ = ISQ(T0)i fz (11) Finally, the ZTC vicinity condition can be analyzed using Eqs. (5) and (6), V GB(i f ) = nφ tf(i f ) + V T 0(T ) + nv S (12) Eq. (12) can be expanded in Taylor s series around the ZTC forward inversion level (i fz ). Therefore, the first order approximation is given by where V GB(i f ) V GZ + VGB i f V GB nφ t = i f 2( 1 + i f 1) (i f i fz ) (13) if =i fz (14) For the α µ 2 [5], combining Eq. (13), (14), and the term nφ t extracted from Eq. (9), we get α VT V GB(T ) V GZ 0 i f 2f(i fz )( 1 + i fz 1) T = VGZ βz i f T (15) where i f = i f i fz indicates how far the transistor is biased from ZTC operating point and β z is defined as the ZTC slope. As the if = I d /I S from the Eq. (3), the dependency of V GB(T ) on the temperature can be be found such that: V GB(T ) = V GZ βz I d T (16) W I SQ L Eq. (16) shows that V GB presents a linear temperature dependence in the vicinity of V GZ, and that this dependence can be positive or negative, depending on the I d chosen, as shown in Fig. 1 (b). Finally, we can readily conclude that a MOSFET transistor biased on ZTC vicinity can be easily compensated with a PTAT or CTAT current reference, the option depending only if it is operating below or above ZTC point. This fundamental concept is used the design of our proposed very-low voltage reference, to operate down to 0.5 V supply. 3. VOLTAGE EFEENCE ANALYSIS AND DESIGN 3.1 Schottky-diode based P T AT Current eference Schottky diodes can be fabricated in almost any current CMOS mixed-signal fabrication process, while silicon junction diodes are omnipresent in bulk MOSFETs. Since our proposed circuit was designed in a commercial 130 nm IBM CMOS process, the data presented here refers to the devices available in this process. In this CMOS process the Schottky diode is formed with a cobalt silicide region (anode) formed over the lightly doped n-type region (cathode) near the surface, that is created by a deep n-type implant. The work function of the cobalt silicide is such that the diode has a low forward voltage when compared to a silicon junction diode under the same junction current density, making the schottky diode a good replacement for their bipolar counterpart in the design of voltage references with ultra-low voltage supplies. The simulated I-V characteristics for two Schottky diodes with different junction areas are shown in Fig. 2 in the temperature range of -55 to 125 C, presenting forward voltages in the range from 0.2 to 0.4 V at room temperature. The Temperature Coefficient (TC) and the forward voltage at -55 C of the these diodes are shown in Fig. 3 as a function of the bias current, where the top Fig. 3 (a) indicates the TC dependence on the consumption, and the bottom Fig. 3 (b) shows the maximum voltage across the diode as a function of the diode bias current. Since our voltage reference is designed for a 0.5 V supply voltage with low power consumption, and the design should target lower fabrication mismatch spread, we chose the 5x5 µm 2 diode biased at 1 µa. Fig. 4 shows the forward voltage across the 5x5 µm 2 Schottky diode biased at 1 µa, presenting a voltage drop from 390 to 140 mv in the temperature range from -55 to 125 C, and around 280 mv at room temperature with and average CTAT temperature sensitivity of mv/ C. Diode Current (A) 1E-4 1E-5 1E-6 1E-7 A 1 =5x5 μ m 2 A 2 =2x2 μ m 2 A 125 C A C A 27 C A 27 C 1E Voltage (V) A 55 C A 55 C V 27 C=[ ] mv Figure 2: Simulated I-V characteristics of a Schottky diode [2x2 µm 2 and 5x5 µm 2 ] at [-55, 27 and, 125] C. For our low-voltage reference design, a low power PTAT current reference is required. This PTAT current reference is generated using the difference of the forward voltage of two schottky diodes operating with different junction current densities, obtained with identical current sources applied in Schottky diodes with different total areas. Fig. 5 shows the schematic diagram of the PTAT current reference where the operational amplifier was implemented with two stages for power supply rejection (PS) improvement. The PTAT current analysis was derived in [10], and it is shown below, where U T is the thermal potential, proportional to the absolute temperature.

4 TC (mv/ C) A 2 =2x2μ m 2 A 1 =5x5μ m V X V Y I PTAT ( a) Bias Current (ua) 1 : K VFB at -55 C (mv) (b) A 2 =2x2μ m 2 A 1 =5x5μ m Bias Current (ua) Figure 3: (a) Temperature Coefficient vs Bias Current, and (b) Forward Voltage at -55 C vs Bias Current. Forward Voltage, Vf (mv) mv / C 100 V C=280mV Figure 4: Forward Voltage vs temperature of a Schottky diode with cathode area 5x5 µm 2 biased at 1µA. I P T AT = T C P T AT = nut ln (K) IP T AT T, where = 1 + T C1(T T0) (T 0) (17) 1 I P T AT (T = 1 0) T 0 [1 + T C 1(T T 0)] Complete Circuit Analysis and Design (18) Figure 5: Low-voltage supply PTAT current reference. The schematic of the voltage reference circuit, depicted in Fig. 7, consists of a low supply PTAT current reference biasing diode-connected NMOS transistors in the vicinity of the ZTC point condition. The PTAT current reference counterbalance the complementary-to-absolute-temperature (CTAT) behavior of the ZTC vicinity resulting the temperature sensitivity compensation. The necessary (W/L) aspect ratio of the diode-connected NMOS transistors, for a given PTAT current reference (T C P T AT ), may be found simply combining Eq. (19) with Eqs. (5) and (6) and making ( V GB)/( T ) T =T0 = 0. Therefore, we get I P T AT = I 0(1 + T C P T AT (T T 0)) (19) ( ) ( W = 2nI0 T CP T AT L C ox 2 α VT 0 ) 2 αµ (20) T 0 Fig. 6 shows the diode-connected current-voltage behavior of the standard, low and zero threshold voltage (V T ) transistors available in the 130-µm CMOS technology, with W/L = 3µm/0.42µm, presenting nominal V T values of 340, 245 and 5 mv, respectively. The drain current I D as a function of the drain-to-source voltage V DS indicates that zero- V T transistors of the same dimensions present, as expected, current levels three orders of magnitude higher than that of the standard-v T transistor, under the same biasing conditions, making it very attractive for low-voltage applications. The reference voltage V EF is obtained from from the diode-connected NMOS transistor voltage drop, as shown in Fig. 7. Three different voltage references (V) were designed with a different nmos transistor. The design in Fig. 7 has the standard-v T (SV T ), the low-v T (LV T ) and the zero-v T (ZV T ) transistors, all supported in this technology. 4. SIMULATION ESULTS Using a nominal supply voltage of 0.5 V the proposed voltage reference shown in Fig. 7 was validated with Cadence simulations, using the models provided by the foundry and inside the temperature range from -55 to 125 C. DC and AC simulations were run to estimate the following performance parameters: PTAT current (I P T AT ) and reference voltages

5 V DD =0.5V 156μ m M A3 M A4 M A5 M 1 M 2 M I 3 PTAT M I 4 PTAT M I 5 PTAT MSVT, MLVT, MZVT M1,2,3,4,5 Cc MA1, MA2, MA3, MA4 V X V M Y A1 M A2 C C Two stage Amplifer M A6 V X D 1 D 2 V Y 1:8 I PTAT Core V EF SVT V EF LVT V EF ZVT M SVT M LVT M C ZVT C1,C2,C3 1 C 2 C 3 D1, D2 Voltage eferences CMOS 130nm 92μ m Figure 7: Proposed 0.5-V CMOS voltage reference schematic circuit and layout. ID (A) 1E-5 1E-6 1E-7 1E-8 1E-9 1E VDS (V) Zero V T Low V T Standard Figure 6: I D vs. V DS for the standard-v T, low-v T and zero-v T with (W/L = 3µm/0.42µm). (V EF ), temperature coefficient (T C), line regulation (L), power supply rejection ratio (P S) and power consumption. Fig. 8 shows the temperature dependence of the PTAT current reference, that was designed for a nominal value of 1 µa under 27 C and a temperature coefficient T C of 4000 ppm/ C. The PTAT TC is not constant, and decreases at high temperatures, above 90 C, as can be deduced from Fig. 8. Current eference(ua) TC=4000 ppm/ C I 27 C=1μ A 0.5 Figure 8: PTAT current reference variation over temperature. The temperature sensitivity of the voltage reference is shown in Figs. 9, 10 and 11 for the three threshold MOS- FETs, standard-v T (SV T ), low-v T (LV T ) and zero-v T (ZV T ) shown in Fig. 7. The simulated nominal reference voltages obtained were, respectively, of 312 mv, 237 mv and 51 mv with TCs of 214 ppm/ C, 372 ppm/ C and 953 ppm/ C, respectively. Voltage eference (mv) Standard V T TC=214 ppm / C V 27 C=312 mv 311 Figure 9: Voltage reference (standard-v T ) variation over temperature. Voltage eference (mv) Low V T TC=372 ppm/ C V 27 C=237 mv 233 Figure 10: Voltage reference (low-v T ) variation over temperature. Fig. 12 exhibits the simulated power supply rejection (PS) of the reference voltage at room temperature. The impact of the fabrication process variations on the reference performance was estimated using Monte Carlo analysis. Table 1 summarizes the performance variations (mean and standard deviation) for I P T AT, V EF, T C, L NF, and

6 Voltage eference (mv) Zero V T TC=953 ppm/ C V 27 C=51 mv 50 Figure 11: Voltage reference (zero-v T ) variation over temperature. Power Supply ejection atio (db) 0-30 SVT, LVT = 28 db ZVT = 37dB -60 1E+0 1E+3 1E+6 1E+9 Frequency (Hz) Figure 12: Power supply rejection ratio of the proposed voltage reference. Table 1: Simulated Performance of the SUB-1V V DD Schottky based reference. Process CMOS 0.13-μm Unit Temp. age C VDD, NOM 0.5 V VDD ange V VEF mv IP T AT 1 ua L (VEF ) mv/v L (IP T AT ) 466 na/v VEF μ= 312 ; σ = 17.8 μ= 237 ; σ = 23.2 μ= 51 ; σ = 11.7 mv VEF μ/σ % TC (VEF ) μ= 214; σ = 133 μ= 372; σ = 268 μ= 953; σ = % Samples < 440 < 810 < 2300 ppm/ C PS@ DC μ= -28; σ = 1.3 μ= -27.5; σ = 1.45 μ= -36.8; σ = % Samples < -26 < -24 < -33 db PS@100 khz μ= -20; σ = 2 μ= -19; σ = 2 μ= -27; σ = % Samples < -18 < -15 < -20 db PS@1 MHz μ= -14; σ = 1.2 μ= -13.3; σ = 1.2 μ= -11; σ = % Samples < -10 < -11 < -8 db Power 5.9 uw Area mm 27C, VDD, NOM ); Simulation results; Process and Mismatch (1000 runs ) Table 2: Performance comparison for SUB-1V V DD Schottky based reference This Work [11] [4] CMOS Process 0.13 μm 90 nm 0.5 μm Unit Temp. age C V DD, NOM V V DD, MIM V V EF mv V EF / V DD mv/100mv TC (V EF ) ppm/ C Power uw Area N/A mm 27C, VDD, NOM ); Simulation results; Process and Mismatch (1000 runs ) P S, as shown in the second, third, and fourth columms in Table 1 for the herein considered SV T, LV T, and ZV T transistor cases, respectively. No experimental measured data is available at the moment for the voltage references, as the circuits are undergoing fabrication. Measured data will be provided in the future for these Vs at the time of paper presentation. Table 2 shows a comparison between other Schottky-diode-based voltage references reported. Our proposed topology was designed to optimize power consumption in a wider temperature range, while maintaining a comparable T C to the other implementations. Our design used at least 10 times lower current than the previous works in Table CONCLUSIONS In this paper a voltage reference operating with 0.5 V power supply voltage and based on the MOSFET ZTC condition is presented. It was demonstrated that the use of Schottky diodes instead of the bipolar junction diodes helps the supply voltage reduction of a PTAT current source, that is used to bias a diode-connected MOS transistor in the vicinity of the ZTC point, resulting a low temperature sensitivity voltage reference. Our design is demonstrated to be capable of operating with a supply voltage as low as 0.45 V. The proposed voltage reference circuit was designed for the three threshold voltage MOSFETs available in the IBM 130 nm CMOS process ( standard-v T, low-v T and zero- V T ), resulting nominal reference voltages of 312 mv, 237 mv and 51 mv with TCs of 214 ppm/ C, 372 ppm/ C and 953 ppm/ C, respectively, in the temperature range from - 55 to +125 C. The total power consumption of our design is just 5.9 µw. This is at least 10 times lower when compared to the other Schottky-diode implementations. Therefore, the proposed voltage reference could be a good option for low-voltage and low-power applications. The proposed topology shows that Schottky-diode-based voltage references in CMOS offer a promising alternative for the design of ultra-low voltage references. Acknowledgments The authors acknowledge the Brazilian funding agencies CNPq and CAPES, and the IC-Brazil Program for financial support and MOSIS for access to chip fabrication services. 6. EFEENCES [1] P. Kinget, Designing analog and rf circuits for ultra-low supply voltages, in Solid State Circuits Conference, ESSCIC rd European, Sept 2007, pp [2] D. M. Colombo, G. Wirth, and S. Bampi, Sub-1 v band-gap based and mos threshold-voltage based

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