Switching Response Modeling of the CMOS Inverter for Sub-micron Devices

Transcription

1 Switchig Respose odelig of the COS Iverter for Sb-micro Devices Bisdois S Nikolaidis O Kofopavlo C Gotis VSI Desig aboratory Departmet of Electrical & Compter Egieerig Uiversity of Patras 6500 Patras Greece Electroics & Compters Divisio Departmet of Physics ristotle Uiversity of Thessaloiki Thessaloiki Greece bstract I this paper a accrate aalytical model for the evalatio of the COS iverter delay i the sb-micro regime is preseted detailed aalysis of the iverter operatio is provided which reslts to accrate expressios describig the otpt waveform These aalytical expressios are valid for all the iverter operatio regios ad ipt waveform slopes They take ito accot the ifleces of the short-circit crret drig switchig ad the gate-to-drai coplig capacitace The preseted model shows clearly the iflece of the iverter desig characteristics the load capacitace ad the slope of the ipt waveform drivig the iverter o the propagatio delay The reslts are i excellet agreemet with SPICE simlatios Itrodctio ch effort has to be devoted for the extractio of accrate aalytical expressios for timig models of basic circits which ca be icorporated i switch ad logic simlators optimizig the desig verificatio procedre Usig trasistor level simlators with cotios-time modelig of the devices like SPICE is very expesive i terms of CPU time Hece mch of past research has addressed the developmet of delay models for COS circits The emphasis of this paper is o the aalytical evalatio of the propagatio delay i a COS iverter alytical expressios of the otpt waveform are derived from the differetial eqatio describig the temporal evoltio of the iverter otpt It is importat to model accrately the COS iverter operatio sice several fast methods for redcig a COS gate to a eqivalet iverter have bee proposed [][] The first closed-form delay expressio based o the otpt respose which was obtaied directly from the differetial eqatio describig the COS iverter operatio was derived i [3] for a step ipt alytical expressios for the otpt waveform ad the propagatio delay icldig the effect of the ipt waveform slope was preseted i [4] ad [5] I these the iflece of the short-circit crret was eglected These works are based o the Shichma-Hodges sqare-law OS model [6] that igores the carriers velocity satratio effect which becomes promiet i short-chael devices I [7] the differetial eqatio describig the discharge of the load capacitor was solved for a risig ipt ramp cosiderig the crret throgh both trasistors ad the gate-to-drai coplig capacitace However merical ad fittig methods are sed resltig i a semi-aalytical model which is still based o the sqare-law OS model Nabavi-ishi ad Rmi [8] preseted a method for the calclatio of the COS iverter delay They se a liear approximatio of the otpt waveform based o empirical factors prodced from SPICE simlatios oreover the method is based o a approximated versio of the SPICE level-3 OS model the velocity satratio effect is eglected Sakrai ad Newto [9][0] preseted closed-form delay expressios for the COS iverter based o the á- power (-power i [0]) law OS model which icldes the carriers velocity satratio effect However these models reqire the extractio of the empirical velocity satratio idex ( or ) from the static device characteristics for each trasistor width For the derivatio of the otpt expressio i [9] the short-circit crret is eglected ad the delay expressio is valid oly for fast ipt ramps I order to approximate the COS iverter by a NOS circit i [0] a fictitios ipt ramp is sed which is clamped to grod for ramp voltages less tha the switchig voltage extesio i the delay expressio of [9] for the case of very lightly loaded iverter ad/or slow ipt sigals is preseted i [] table of coefficiets prodced from SPICE simlatios is sed bt still for egligible short-circit crret The delay model preseted i [] ses the -power OS model takig ito accot the short-circit crret of the COS iverter bt the otpt voltage ad the crrets throgh the trasistors are assmed to be piecewise liear 79

2 I this paper aalytical expressios for the COS iverter otpt respose to a ipt voltage ramp which overcome the weakesses of previos works are derived Based o these expressios accrate aalytical formlae for the evalatio of the propagatio delay for all the cases of ipt ramps are prodced The derived timig model takes ito accot the ifleces of the crret throgh both trasistors ad the gate-to-drai coplig capacitace It avoids merical methods ad empirical approaches based o pre-simlatio data simple OS model [3] which cosiders the carriers velocity satratio effects of short-chael devices has bee chose Iverter switchig respose aalysis The derivatios preseted i the followig are for a risig ipt ramp: Vi VDD ( t ) for 0 t V i 0 for t 0 ad Vi VDD for t ô is the ipt rise time The aalysis for a fallig ipt is symmetric ad similar reslts are obtaied by appropriate sbstittios i the derived eqatios The differetial eqatio which describes the discharge of the load capacitace C for the COS iverter (Fig) takig ito accot the gate-drai capacitive coplig (C ) is derived from the applicatio of the Kirchoff s crret law to the otpt ode C dv dt IC IC Ip I 0 dv dt dv dt ot C i ot Ip I () For the ipt oted above the eqatio () becomes dv dt ot c m Ip I C C c V I I DD C C m p C C C t 0 or t 0 t () The otpt load cosists of the iverter drai jctio capacitaces the gate capacitaces of faot gates ad the itercoect capacitace The eqivalet gate-to-drai capacitace C is the sm of the gate-to-drai overlap capacitace ad a part of the gate-to-chael capacitace of the trasistors [4] The overlap capacitace is voltage idepedet ad is give by C W Cgdo gd overlap W is the effective width of the trasistor C gdo is the gate-to-drai overlap capacitace per micro which is V i P OS N OS V D D I p C I C I C I Fig: The COS iverter V ot determied by the process techology I the ctoff regio of the trasistor there is o codctig chael ad i the satratio regio the chael does ot exted to the drai Therefore the gate-to-drai capacitace de to the chael charge is eqal to zero I the liear regio the distribted gate-to-chael capacitace may be viewed as beig shared eqally betwee the sorce ad the drai Ths i this case Cgdchael Cox W C ox is the gate-oxide capacitace per it area ad is the effective legth of the trasistor Depedig o the regio of operatio the drai crret of the devices is give by the followig eqatios of the sed OS model [3] C ID 0 V GS V TH Ctoff (3) I D VO VGS VT H V DS V DST Satratio (4) I D V DS V VT V GS H DS (5) V V O DS V DS V DST iear is the device gai factor ad V TH is the device threshold voltage V O is the voltage which specifies the effects of carriers velocity satratio ad is extracted from the device static characteristics V DST is the device satratio voltage ad is give by V V V V V V DST O O GS T H O I the followig ormalized voltages with respect to V DD ie i = V i / V DD ot = V ot / V DD = V THN / V DD p = V THP / V DD v o = V ON / V DD v op = V OP / V DD ad the variable x = t / are sed Sice the ipt ramp will reach its fial vale with the NOS device either i satratio or i the liear regio two mai cases of ipt ramps mst be cosidered i order to give a complete aalysis of the otpt waveform For fast ipt ramps the NOS device is still 730

3 p G vop y G x p pvdd p C C y p G 0 Fig: Operatio regios of the iverter satrated while for slow ipt ramps the NOS is i its liear regio whe the ipt voltage ramp reaches its fial vale Case - Fast ipt ramps: I the followig we aalyze each regio of the iverter operatio for the case of fast ipt ramps (Fig) Regio 0 x : The NOS trasistor is off ad the POS trasistor is i the liear regio The first term of the right part i eqatio () (for 0 t ô) correspods to the chargig crret throgh the gate-to-drai coplig capacitace (C ) This cases the major iflece o the otpt voltage waveform i this regio Part of the charge from the ipt which ijected throgh this capacitace cases a overshoot at the early part of the otpt voltage waveform (Fig) Drig the overshoot the POS device operates i a reversed liear mode becase the otpt voltage is greater tha the spply voltage Ths the POS device iitially helps to dischargig the load capacitace towards the spply voltage The differetial eqatio () sig the crret eqatios (3) (5) becomes a o-liear Riccati eqatio [5] which caot be solved aalytically if a particlar soltio is ot kow However the qadratic term of the POS crret ca be eglected becase the charge cotribted by this term is egligible de to the small vales of the drai-sorce voltage of the POS device i this regio [7] lso i order to give a soltio of the differetial eqatio a average vale of ot ie = + (c m / ) is sed at the deomiator of the POS crret expressio fter that the soltio of eqatio () is cm ot e y erf [ y] erf [ y0 ] G (6) ad erf [y ] erf [y 0 ] are the error fctios of y y 0 respectively Stadard ways of evalatig the error fctio ca be fod i ay mathematical hadbook Regio x x satp : The NOS device is satrated ad the POS device is i the liear regio Drig the otpt voltage overshoot the POS device still operates i a reversed liear mode Note that the right limit of this regio (Fig) is the ormalized time vale x satp the POS device eters satratio ie V DD - V ot = V DSTP It is determied by the POS satratio coditio satp v v op op x satp p satp is the ormalized otpt voltage vale whe POS device satrates s i regio we eglect the qadratic crret term of the POS device lso istead of ot at the deomiator of the POS crret expressio we se a average vale of the ormalized otpt voltage [ ] satp satp is the vale of the ( ) ie ormalized otpt voltage at the ed of regio if egligible POS crret is assmed ad is calclated below by eqatio (0) [] is the vale of the ormalized otpt voltage at the begiig of regio ad is calclated from eqatio (6) for x = fter the above approximatios the soltio of the eqatio () is v v e y o o ot [] G G e y y y v o e c m erf[y ] erf[y ] G G (7) VDD C C y G / x p G v op p y G / p The above eqatios (6) (7) give waveforms very close to those derived from SPICE simlatios (as show i the sectio 4) which idicates the validity of the above approximatios I order to cotie the aalysis for the ext regio the calclatio of the vales x satp satp is reqired s metioed above these vales satisfy the POS satratio coditio ot v op v op x p (8) 73

4 Fig3: Evalatio of the ormalized time x satp They ca be fod by solvig the system of eqatios (7) ad (8) De to the error fctios of eqatio (7) the system caot be solved aalytically Hece i the followig a efficiet method for the calclatio of x satp satp is sed (Fig3) The aalytical soltio of the differetial eqatio () if egligible POS crret is assmed i regio is v o ot cm x x (9) = [] c m is the itegratio costat which is iserted to esre cotiity with respect to regio By eqatig (8) ad (9) the ormalized time vale x satp i which the iverter leaves regio with the assmptio of egligible POS crret is derived fter the sbstittio of x satp i eqatio (9) the vale of the ormalized voltage satp is derived v o satp cm xsatp xsatp (0) The ext step of or method is to determie the taget of the otpt waveform expressed by (7) at the poit which correspods to x satp (Fig3) This taget is expressed by the eqatio ot a x b () d ot a x dx xsatp ad b ot x a x xsatp satp By eqatig (8) ad () x satp becomes the root of a simple qadratic eqatio The by sbstittig x satp i (7) the ormalized otpt voltage satp is evalated The error which is itrodced i the calclatio of x satp de to the above method is p to 05% I the special case of very fast ipt ramps (Fig) the POS device is tred off after its liear regio withot eters satratio This occrs becase the otpt voltage overshoot fiishes whe the POS is already off Hece the iverter does ot eter i regio 3 ad the calclatio of x satp ad satp is ot reqired Regio 3 x satp x -p: Both trasistors are satrated The aalytical soltio of eqatio () i this regio is v o ot 3 cm x x p v op x p () the itegratio costat which is iserted to esre cotiity with respect to regio is give by v o 3 satp cm xsatp xsatp p v op xsatp p Regio 4 -p x : The NOS trasistor is satrated ad the POS trasistor is off The aalytical soltio of the differetial eqatio () is v ot 3 cm x o x (3) s metioed above for very fast ipt ramps the iverter does ot pass from the regio 3 becase the POS device is ot satrated I this case the itegratio costat 3 is sbstitted by the followig costat 4 v o 4 [ p] cm p p [-p] is the vale of the ormalized otpt voltage i which the POS device is tred off It is calclated from eqatio (7) for x = p Regio 5 x x sat : The ipt ramp has reached its fial vale with the NOS device still i satratio ad the POS device off x sat is the ormalized time vale the V ot = V DSTN I this regio the aalytical soltio of the differetial eqatio () (for t ô) becomes v o ot 3 cm x vo (4) the costat 3 is sbstitted by 4 for very fast ipt ramps Regio 6 x x sat : The NOS device eters i its liear regio ad the POS is off The soltio of the eqatio () is v o x xsat ot max ot (5) max 73

5 max o o v v from eqatio (4) for ot = max x sat is calclated Case B - Slow ipt ramps: I the secod case slow ipt ramps are stdied The NOS device leaves satratio while the ipt voltage is still a ramp This occrs if the vale of the ormalized otpt voltage whe the ipt ramp reaches its fial vale is lower tha max (Fig) The otpt expressios for the regios 3 ad 4 are the same with those of the previos case The ormalized time x sat is calclated from eqatio (3) for ot v o v ox which correspods to the NOS satratio lie (Fig) I the case of slower ipt ramps the iverter does t eter i regio 4 This occrs i the case the POS trasistor is tred off whe the NOS trasistor is already i the liear regio I this case x sat is calclated from eqatio () Regio 5B x sat x : The NOS trasistor is i the liear regio ad the POS trasistor is either off or so poorly codctig that its iflece ca be eglected Neglectig the chargig crret throgh the gate-to-drai coplig capacitace ad sig at the deomiator of the NOS crret a average vale for the otpt voltage ( sat / ) a approximated soltio of () is ot e y 3 y sat e sat [ ] [ ] (6) erf y erf y 3 sat satvo 4 y x y sat 3 sat v o sat v o xsat ad sat v o v oxsat Regio 6 x : The ipt ramp has reached its fial vale the NOS device is still i the liear regio ad the POS device is off The otpt waveform is expressed as v o x ot [ ] ot [ ] (7) [] is the vale of the ormalized otpt voltage whe the ipt ramp has its fial vale It is calclated if we set x = i eqatio (6) 3 Propagatio delay aalysis The fall propagatio delay at the 50% voltage level may be writte as T D t 05 x05 (8) x 05 is the ormalized time vale whe ot = 05 Ths for the evalatio of the propagatio delay the ormalized time vale x 05 mst be determied for both cases of ipt ramps critical parameter i order to fid i which regio occrs the 50% level of the otpt voltage ( ot = 05) is the maximm drai satratio voltage of the NOS device ( max - see Fig) Hece it is ecessary to cosider two possibilities i the delay calclatio: max 05 ad max 05 max v o vo max 05: I the case of fast ipt ramps the otpt voltage reaches the 50% level whe the iverter operates i regio 5 if [] 05 ad i regio 4 if [] 05 [] is the vale of the ormalized otpt voltage whe the ipt ramp reaches its fial vale ad is calclated from eqatio (3) for x = Whe ot = 05 occrs i regio 5 x 05 is calclated from eqatio (4) 3 cm 0 5 x0 5 (9) v o I the case ot = 05 occrs i regio 4 x 05 is calclated from eqatio (3) v o cm cm v o cm 3 x0 5 (0) v o For slow ipt ramps the coditio ot = 05 occrs i regio 4 if [-p] 05 ad i regio 3 if [-p] 05 [-p] is the vale of the ormalized otpt voltage whe the POS device eters the ctoff regio I the first case the ormalized time vale x 05 is give by eqatio (0) ad i the secod oe is calclated from eqatio () x0 5 D 4D E K () E 733

6 D pv op p v o cm E v o pv op ad K 3 pvop p vo max 05: For fast ipt ramps ot = 05 occrs i regio 6 ad x 05 is calclated from (5) v o x0 5 xsat 05 max 05 () max I the case of slow ipt ramps the otpt voltage reaches the 50% level whe the iverter operates i regio 6 if [] 05 If [] 05 there are two possibilities for the regio i which ot = 05 Either sat 05 the otpt voltage reaches the 50% level i regio 5B or sat 05 i regio 3 I regio 6 x 05 is calclated from (7) v o x [ ] 0 5 (3) [ ] ad i regio 3 x 05 is give by eqatio () Sice the expressio of the otpt waveform i regio 5B caot be solved aalytically ot ca be approximated by a ramp i the viciity of the 50% level i this regio The x0 5 xsat 05 sat (4) d d ot d x is the otpt waveform slope i dx xsat regio 5B ad is calclated sig eqatio (6) I real COS datapaths the ipt sigal of a gate is ot a ramp bt the otpt waveform of the precedig gate I order the derived ramp delay model to be applicable to iverter chais the real ipt waveform mst be approximated by a ramp waveform to obtai a effective trasitio time Some efficiet approximatios for the evalatio of the effective otpt trasitio time of the iverter ca be fod i [4] [9] 4 Reslts ad discssio I Fig4 some typical otpt waveforms prodced from the above expressios are show sb-micro COS process techology of 05 m has bee sed to validate the accracy of the preseted iverter otpt Fig4: Iverter otpt waveforms Parameter NOS POS ( m) W ( m) V O (Volts) 05 V TH (Volts) C ox (ff/ m ) C gdo (ff/ m) Table : odel parameters sed i calclatios waveform expressios The model parameters ad the dimesios of both trasistors are listed i Table The trasistor widths have bee selected i order to achieve eqal drai crrets at V GS = V DS = V DD The otpt waveforms prodced by SPICE simlatios are added for compariso spply voltage of 5Volts ad a otpt load of 0pF was sed It ca be observed that the aalytical waveforms are very close to those prodced by SPICE simlatios I order to give otpt waveforms for several ipt rise times i the same diagram the ormalized otpt voltage is plotted as a fctio of the ormalized time (x = t / ) The otpt waveforms for ipt times 0s ad 05s correspod to case while those for ipt times 08s ad 5s to case B s we ca see the slope of the otpt waveforms i case is smaller tha the ipt slope while i case B is greater tha the ipt slope I Fig5 the iverter propagatio delay for a risig ipt ramp is plotted as a fctio of o = ( V DD )/C Sice o is a sigle lmped parameter which takes ito accot the ipt waveform slope the drivability of the switchig trasistor ad the load capacitace determies the relatio betwee the ipt ad the otpt waveform The reslts for o < 5 correspod to fast ipts (case ) compared to the otpt waveforms ad those for o > 5 734

7 sb-micro devices has bee preseted I order to achieve that aalytical expressios of the iverter otpt ramp respose for all the cases of ipt ramps have bee derived These expressios take ito accot the ifleces of the short-circit crret ad the gate-to-drai coplig capacitace i all operatio regios withot sig empirical approaches based o pre-simlatio reslts Refereces Fig5: Iverter propagatio delay correspod to slow ipts (case B) Reslts sig the approaches for the evalatio of the propagatio delay preseted i [4][8][9] ad [] are also give It ca be observed that the preseted model gives reslts closer to those derived from SPICE simlatios tha the other methods The error is less tha 35% This occrs becase or model icldes the ifleces of the short-circit crret ad the gate-to-drai coplig capacitace o the expressios of the iverter otpt waveform other advatage of the previos aalysis is the se of a simple OS model which takes ito accot the velocity satratio effects of short-chael devices withot eed of parameters extractio whe the trasistor width is chaged The preseted timig model ca be sed for more complex COS gates sice several fast methods [][] have bee proposed for redcig a COS gate to a eqivalet iverter The most critical isse i gate modelig is the redctio of serial coected OSFETs i order to redce the drivability of the serial array to the drivability of a eqivalet OSFET Usig redctio techiqes the propagatio delay of a gate ca be compted qickly ad accrately sig the timig model of the COS iverter ad withot the complicatios associated with tryig to geeralize the iverter model to complex gates 5 Coclsio I this paper a accrate aalytical method for the evalatio of the COS iverter propagatio delay for [] Nabavi-ishi NC Rmi Iverter models of COS gates for spply crret ad delay evalatio IEEE Tras Compter-ided Desig vol 3 pp 7-79 Oct 994 [] J-T Kog D Overhaser ethods to improve digital OS macromodel accracy IEEE Tras Compter- ided Desig vol 4 pp Jly 995 [3] JR Brs Switchig respose of complemetary symmetry OS trasistor logic circits RC Review vol 5 pp Dec 964 [4] N Hedestiera KO Jeppso COS circit speed ad bffer optimizatio IEEE Tras Compter-ided Desig vol CD-6 pp 70-8 arch 987 [5] I Kayssi K Sakallah T Brks alytical trasiet respose of COS iverters IEEE Tras Circits ad Systems - I vol 39 pp 4-45 Ja 99 [6] H Shichma D Hodges odelig ad simlatio of islated-gate field-effect trasistor switchig circits IEEE J Solid-State Circits vol SC-3 pp Sept 968 [7] KO Jeppso odelig the iflece of the trasistor gai ratio ad the ipt-to-otpt coplig capacitace o the COS iverter delay IEEE J Solid-State Circits vol 9 pp Je 994 [8] Nabavi-ishi NC Rmi Simltaeos delay ad maximm crret calclatio i COS gates IEE Electroics etters vol 8 pp arch 99 [9] T Sakrai R Newto lpha-power law OSFET model ad its applicatios to COS iverter delay ad other formlas IEEE J Solid-State Circits vol 5 pp pril 990 [0] T Sakrai R Newto simple OSFET model for circit aalysis IEEE Tras Electro Devices vol 38 pp pril 99 [] S Dtta SS ahat Shetti S sky comprehesive delay model for COS iverters IEEE J Solid-State Circits vol 30 pp gst 995 [] SHK Embabi R Damodara Delay models for COS BiCOS BiNOS circits ad their applicatios for timig simlatios IEEE Tras Compter-ided Desig vol 3 pp 3-4 Sept 994 [3] Shoji COS Digital Circit Techology NJ: Pretice-Hall 988 [4] NHE Weste K Eshraghia Priciples of COS VSI Desig: Systems Perspective NY: cgraw-hill 993 [5] ED Raiville PE Bediet Elemetary Differetial Eqatios NY: cgraw-hill