An Area Efficient Low Power TG Full Adder Design using CMOS Nano Technology

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2 An Area Efficien Low Power TG Full Adder Design using CMOS Nano Technology 1 Shivani Singh 1 M.ech, Digial Communicaion, RTU, KOTA 2 Buddhi Prakash Sharma 2 ME Scholor, Elecronics & Comm., NITTTR, Chandigarh, India 3 Sanjay Kumar Singhal 3 Assisan Professor, Elec. & Commu. RIET, Jaiur Absrac: Full adders are he basic building block of ALU and ALU is an essenial uni of he microrocessors and DSP. In he world of echnology i has become necessary o develo various new design mehodologies o reduce he ower and area consumion. In his aer ransmission gaes have been used o develo he roosed full adder using 4 ransisors XOR and XNOR gaes. The carry logic has been efficienly imlemened using 2:l MUX o reduce ransisor coun. The reducion in Transisor coun resuls in imroved area and ower consumion. The roosed full adder has been designed using 10 ransisors using 32 nm CMOS echnologies. The develoed adder wih 10 ransisors XOR/XNOR have shown an imrovemen of 65.63%/44.08% in ower and % in area so as o imlemen adder efficienly in digial signal rocessors. Keywords- DSCH, full adder, ransmission gae (TG), Mux, XOR/XNOR. I. INTRODUCTION In VLSI design mehodologies ower reducion is one of he rimary asecs because a long baery life is required for cell hones and orable devices, Power dissiaion is increasing as number of ransisors increases on a single chi. The elecronics indusry has achieved a henomenal growh over he las coule of decades, mainly due o he raid advances in inegraion echnologies (IC) and large scale sysems design. The level of inegraion as measured by he number of logic gaes in a monolihic chi. Adder is one of he mos criical comonens of a rocessor, as i is used in he arihmeic logic uni (ALU), in he floaing oin uni, and for address generaion in case of cache or memory access [1]. Digial CMOS (Comlemenary Meal Oxide Semiconducor) inegraed circuis (ICs) have been he driving force behind Very Large Scale Inegraion (VLSI) for high erformance comuing and oher scienific and engineering alicaion CMOS logic families are an obvious choice for lowower logic due o heir simliciy and he fac ha simly scaling he suly volage can allow he same circui o be used under a wide erformance range in erms of seed and ower consumion. Increasing demand for mobile elecronic devices such as mobile hones, PDA's, and lao comuers requires he use of ower efficien VLSI circuis. The Full Adder is a combinaional circui wih hree inus, i.e. Bil (X),Bi2 (Y), and Carry in (Z) and wo ouus i.e. Sum and Cou (Carry). The Boolean exressions for some and carry is given bellow: Sum X Y Z Carry XY YZ ZX Where X, Y, Z are he inus. In any CMOS VLSI circui design dynamic ower lays mos imoran role. Thus, for analyzing Full Adder cell only dynamic ower is of ineres. During a ransiion from eiher low o high ( 0 o 1 ) or alernaively from high o low ( 1 o 0 ) boh PMOS and NMOS ransisors are ON for a shor san of ime. This resuls in shor curren ulse from o GND. Curren is also required in charging and discharging he ouu caaciive load. The curren ulse from o GND resuls in a shor circui dissiaion ha is deenden on he inu eiher rise ime or fall ime as well as he load caaciance and he gae design. Condiion having no load caaciance, he shor circui curren is noiceable. As he caaciive load is increased, he charging or discharging curren sars o dominae he curren drawn from he ower sulies. The dynamic ower dissiaion can be modeled by assuming ha he rise ime and fall ime of he uni se inu is much less han he reeiion eriod. The average dynamic ower (P dynamic ), dissiaed during swiching for a square wave inu (V in ), having a reeiion frequency of f =1/, is given by P dynamic in ( ) Voud in ( )( (1) 2 V OUT ) d For uni se inu & wih i n =C L (dv OUT /d), where C L is load caaciance. Now we obain he following exression for dynamic ower P dynamic : P dynamic L 0 0 CL CL 2 OUT. dvout ( VOUT ) d( VOUT ) C V wih f =1/ resuls P dynamic =C L V 2 DD.f (3) or reeiive se inu, he average ower dissiaion is roorional o he energy required in charging and discharging he circui caaciance. The imoran facor is ha eq. (3) shows ower o be direcly roorional o swiching frequency bu (2)

3 indeenden of he device arameers [2]. A ransmission gae has hree inus called source, n-gae and -gae. I also has one ouu called drain. A CMOS ransmission gae [3] can be consruced by arallel combinaion of NMOS and PMOS ransisors, wih comlemenary gae signals like X, Xbar as shown below. As such, he CMOS TG oeraes as a bidirecional swich beween he nodes IN and OUT which is conrolled by signal X. If he conrol signal X is equal o, hen boh ransisors are urned on and rovide a low-resisance curren ah beween he nodes IN and OUT. If, on he oher hand, he conrol signal X is low, hen boh ransisors will be off, and he ah beween he IN and OUT will be an oen circui. The main advanage of he CMOS ransmission gae comared o NMOS ransmission gae is o allow he inu signal o be ransmied o he ouu wihou aenuaion in he hreshold volage. The schemaic diagram and symbol of ransmission gae is shown in Fig 1 shown below. This full adder consiss less ransisors coun as comared o convenional one. Figure 3: TG Full Adder by 26 ransisors Figure 1 Schemaic diagram & Symbol of Transmission gae 20 ransisors full adder by using ass ransisor logic is shown in Fig-4 [6]. Alhough he ransisor coun is less as comared o revious one bu he circui consume more ower and give he slower seed due o hreshold loss roblem. When he volage on node X is a Logic 1, he comlemenary Logic 0 is alied o node acive low X, allowing boh ransisors o conduc and ass he signal a IN o OUT. When he volage on node acive-low X is Logic 0, he comlemenary Logic 1 is alied o node X, urning boh ransisors off and forcing a highimedance condiion on boh he IN and OUT nodes. II. PREVIOUS WORKS Various full adder circuis have been resened in lieraure [4] - [7]. 28 ransisors convenional full adder is given in Fig.2 [4].In his adder design PMOS nework is same as NMOS nework. Due o high number of ransisors, is ower consumion is high. Large PMOS ransisor in ull u nework resuls in high inu caaciances, which cause high delay and dynamic ower. One of he mos significan advanages of his full adder was is high noise margins and hus reliable oeraion a low volages. Figure 4: Pass ransisor based Full Adder by 20 ransisors III. PROPOSED FULL ADDER The roosed full adder uses ass ransisor logic and ransmission gae. Which follows he Boolean equaion as shown below where X, Y, Z are he inus and SUM and CARRY are he ouus of full adder. Figure 2: The convenional design of CMOS Full Adder wih 28 Transisor [1] 26 ransisors ransmission gae full adder is shown in Fig-3 [5].Schemaic of his circui is simle as comared o revious one. This full adder consiss less ransisors coun as comared o convenional one. 26 ransisors ransmission gae full adder is shown in Fig-3 [5].Schemaic of his circui is simle as comared o revious one. SUM XYZ XY Z XY Z XYZ CARRY XYZ XYZ XY Z XYZ (4) The exclusive OR (XOR) and exclusive NOR (XNOR) gaes are he basic building blocks of a full adder circui. The XOR/ XNOR gaes can be imlemened using AND, OR, and NOT gaes wih high redundancy [8]. Oimized design of hese logic gaes increases he erformance of VLSI sysems as hese gaes are uilized as sub blocks in larger circuis. XNOR/XOR design wih less number of ransisors, lesser ower dissiaion and delay are highly desirable for efficien imlemenaion of he large VLSI sysem

4 Figure 5: Srucure of single bi Full Adder Figure 8: Proosed 4-Transisor XOR cell Srucured aroach for imlemenaion of single bi full adder using XOR/XNOR has been reored [9] as shown in Figure5. Wih decomosiion of full adder cell ino smaller cells wih he hel of modules. Module-1 reresen he XOR gae, which erform XOR oeraion on wo bi X, Y can also be known as half sum. Module-2 again reresen XOR gae bu having inus bi Z and ouu of module-1. I gives he ouu which is known as sum of full adder. Module-3 works as a 2:1 mulilexer, having inus bi X, Z and gives ouu which is known as carry of full adder. CMOS ransmission gae Figure 6 shows an eighransisor imlemenaion of he logic XOR funcion, using wo CMOS TGs and wo CMOS inverers. Figure 6: Eigh-ransisor CMOS TG imlemenaion of he XOR funcion [10]. Figure 9: Proosed 4-Transisor XNOR cell Comarisons of area and ower of his design fig. 6,7,8,9 is shown below in able below. Table 1: Comarison of differen XOR/XNOR cell XOR/XNOR CELL AREA um 2 POWER uw 8 ransisor TG ransisor TG The same funcion can also be imlemened using only six ransisors, as shown in fig. 7 4 ransisor xnor ransisor xor IV SCHEMATIC DESIGN OF TG FULL ADDER A. TG full adder circui wih 2:1 mux Figure 7: Six-ransisor CMOS TG imlemenaion of he XOR funcion [10]. We furher reduced he number of ransisors in roosed XOR/XNOR cell as shown in fig. 8. Figure 10: Proosed FA cell wih 2:1 mux Figure 10 indicaes a full adder design using 2 XOR cells and one 2:1 mux which are shown below in fig

Figure 14: Layou design of Proosed 10TG XOR FA Figure 11: Proosed 2:1 mulilexer B.

The simulaion is erformed using schemaic enry and is funcionaliy is verified in DSCH 3.5. Afer verificaion VERILOG file is generaed. VERILOG is comiled o ge hysical layou of schemaic designs.

Area and ower consumed by his circui is less as comared o full adder circui made by XOR circui in fig -6, 7 and having same area as 4 ransisor xnor cell bu consumes less ower han xnor cell based full

Layou and analog simulaion of various designs are shown in figs 14,15,16,17. Layou shows he various meal layers and heir inerconnecion hrough via. Fig.

5 Figure 14: Layou design of Proosed 10TG XOR FA Figure 11: Proosed 2:1 mulilexer B.TG full adder block diagram by using roosed 4T XOR/XNOR This secion resens he layou and analog simulaion of various designs. These designs are simulaed using Microwind 3.l ool. The simulaion is erformed using schemaic enry and is funcionaliy is verified in DSCH 3.5. Afer verificaion VERILOG file is generaed. VERILOG is comiled o ge hysical layou of schemaic designs. TG Full adder design of full adder by using 10 ransisors is shown in fig. 12. This full adder circui is made by using 4 ransisor XOR circui shown in fig-8. Area and ower consumed by his circui is less as comared o full adder circui made by XOR circui in fig -6, 7 and having same area as 4 ransisor xnor cell bu consumes less ower han xnor cell based full adder shown in fig. 13. Figure 15: Layou design of Proosed 10TG XNOR FA Using layou of circui values like ower, resisance, Caaciance, node volage and curren can be esimaed. Layou and analog simulaion of various designs are shown in figs 14,15,16,17. Layou shows he various meal layers and heir inerconnecion hrough via. Fig. 14 and 15 shows he layou and 16 and 17 shows he analog simulaion of various designs. Figure 12: Proosed 10TG FA design based on XOR cell Figure 16: Analog simulaion resul of roosed 10TG XOR FA Figure 13: Proosed 10TG FA design based on XNOR cell IV. SIMULATION AND LAYOUT Reducion of ower consumion rovides a grea imrovemen o an adder circui. Power consumion issues can lead o over consumion of resources when devices are added serially. This reducion in ower would come a he exense of overall seed and increased delay. Figure 17: Analog simulaion resul of roosed 10TG XNOR FA On he basis of MICROWIND designing ool we make he erformance comarison beween of area and ower of CMOS

6 full adder, TG full adder by 27T, TG full adder design wih 2xl MUX which consis 18 ransisors and TG roosed full adder. Differen full adder srucure comarison is shown in able2 below. Table 2: COMPARATIVE STUDY OF AREA AND POWER OF VARIOUS TG FULL ADDER DESIGNS Design Power Area Transisor Coun 18 TG FA 3.68uw 58.4um TG FA 2.45uw 41.2um TG XNOR FA 1.371uw 25.5um TG XOR FA 0.842uw 25.5um 2 10 Power consumed by each design is 3.68uw, 2.45uw, 1.371uw, 0.842uw resecively. Power consumed by 10TG XOR full adder is less hen 10TG XNOR full adder. V. CONCLUSION This aer resens an area and ower efficien echnique o design a full adder, using ransmission gae and 2:1 mux in order o reduce ransisor coun. Mos of he convenional CMOS adders have been designed using 28 ransisors which are very high. As number of ransisors increases resuls in high ower consumion. To overcome his roblem, he roosed full adder has been designed using less number of ransisors (10T) o imrove he ower and area simulaneously. Two full adders have been designed using 10 ransisors wih XOR and XNOR cell. The full adder using 10 TG XOR/XNOR consumes ower and area resecively 1.371uw/0.842uw and 25.5um 2 each. All he resuls are simulaed using MICROWIND3.1. REFERENCES [1] R. Shalem, E. John, L. K. John, "A Novel Low Power Energy Recovery Full Adder Cell," in Proc. IEEE Grea Lakes VLSI Sym., Feb. 1999, [2] A. M. Shams and M. A. Bayoumi, A framework for fair erformance evaluaion of 1-bi full adder cells, In Proceedings of he 42nd Midwes Symosium on Circuis and Sysems, vol. 1,. 6-9, IEEE Comuer Sociey Press, Augus [3] D. Markovic, B. Nikolic, V.G. Oklobdz, A general mehod in synhesis of ass-ransisor circuis, Microelecronics Journal 31 (2000). [4] N. Wese and K. Eshraghian, "Princiles of CMOSVLSI Design", A Sysem Persecive. Reading, MA: Addison-Wesley, [5] N. Zhuang and H. Wu, A new design of he CMOS full adder," IEEE Journal of Solid-Sae Circuis, vo1. 27, No. 5, , May [6] K.-H. Cheng and c.-s. Huang, "The novel efficien design of XORlXNOR funcion for adder alicaions," in Proc. of he 6h IEEE Inernaional Conference on Elecronics. Circuis and Sysem, vo1. 1,.29-32, [7] Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo- ShingHuang," A Low -Power High-seed Hybrid CMOS Full Adder For Embedded Sysem," IEEE ransacions on Design and Diagnosics of Elecronic Circuis and Sysems,vo1. 13, No.6,.-1-4, 2007 [8] Y. Leblebici, S.M. Kang, CMOS Digial Inegraed Circuis, Singaore: Mc Graw Hill, 2nd ediion, [9] Ahmed M. Shams and Magdy A, A srucured aroach for designing low ower adders, Conference Record of he Thiry- Firs Asilomar Conference on Signals, Sysems & Comuers, vol.1, , Nov [10] Anjali Sharma, Richa Singh, Rajesh Mehra, Low Power TG Full Adder Design Using CMOS Nano Technology, 2nd IEEE Inernaional Conference on Parallel, Disribued and Grid Comuing, ,

Comparator Design Analysis using Efficient Low Power Full Adder Meena Aggarwal 1, Rajesh Mehra 2 1 ME student (ECE), 2 Associate Professor

International Journal of Engineering Trends and Technology (IJETT) olume 26 Number 1- August 2015 Comparator Design Analysis using Efficient Low Power Full Adder Meena Aggarwal 1, Rajesh Mehra 2 1 ME student