Methods for Manufacturing Improvement IEOR 130. Prof. Robert C. Leachman University of California at Berkeley. August, 2017

Transcription

1 Methods for Manufacturing Improvement IEOR 130 Prof. Robert C. Leachman University of California at Berkeley August, 2017

2 IEOR 130 Purpose of course: instill cross-disciplinary, industrial engineering perspective and skills in future engineers, managers or researchers for technologyintensive manufacturing Course prerequisites: calculus, linear algebra, statistics and probability. Physics recommended. Course assignments: ~ 9 homework exercises, midterm exam, final exam Course grade: Max { F, 0.67F M}

3 Instructors and readings Prof. Rob Leachman, 4127 Etcheverry Hall Office hours TuTh (class days only) or by appt, GSI Dean Grosbard Office hours TBA, 8/17 Course web site: Course outline, presentation slides, required readings, HW and HW solutions are all posted on the course web site

4 Topics What matters in high-tech manufacturing: 8/17 Process control We need a stable manufacturing process. We need to consistently make good product. Yield analysis We need to identify root causes of quality losses and eliminate them. Equipment efficiency We need to achieve good return on very expensive equipment assets. We need to understand capacity and plan investments wisely. On-time delivery We need to promise delivery dates we can achieve, and we need to achieve them. Speed (AKA cycle time) For competitive reasons and economic reasons, we need manufacturing to be fast.

5 Technical Topics and Relationship to Other IEOR Courses Statistical Process Control (IEOR 165), Process Controllability and Six Sigma Analysis Statistical Yield Analysis Maintenance Scheduling Under Uncertainty (renewal models, IEOR 172) Equipment Efficiency Measurement Production Planning (IEOR 150 & 162) and Delivery Quotation Factory Floor Scheduling (IEOR 150) and Management of Work-in-Process Economics of Speed (Continuous-time discounting of cash flows, E120) Cycle Time Analysis (Queuing analysis, IEOR 161 & 151) Capacity Planning

6 Course Outline Introduction to Semiconductor technology and manufacturing (today and 8/29) Statistical process control (8/31, 9/5, 9/7) Yield analysis (9/12, 9/19) Equip maintenance & efficiency analysis (9/21, 9/26) Production Planning, On-time delivery (next) Cycle time analysis (after midterm) Line Scheduling (after midterm) Benchmarking best manufacturing performance and practices (course wrap-up)

7 Introduction to Semiconductor Technology Semi-conducting materials (Germanium, Silicon, Gallium Arsenide) - insulator if pure, conductor if doped with particular impurities Crystalline structure allows relatively large gains in current and generates current from applied voltage Transistors were made out of Germanium beginning in the 1950s

8 Semiconductor Technology (cont.) Integrated circuits were made out of Silicon beginning in the 1960s, a much more suitable material (wider semiconductor band gap, higher melting point) Jack Kilby of Texas Instruments proposed complete circuits (resistors, capacitors, diodes, transistors) made out of silicon; prototype was fabricated out of Germanium, with connecting wires attached to mesas

9 Semiconductor Technology (cont.) Robert Noyce and others at Fairchild invent the planar fabrication process: Photolithography isolate patterned areas of silicon wafer Diffusion using a furnace, dopants are diffused into the silicon to define the circuit elements Apply film of SiO 2 (an insulator as well as a protective coating) also done with diffusion furnaces Etch holes or vias through the SiO 2 to expose the circuit elements Evaporate aluminum into the vias to connect up circuit elements

10 Microelectronics: Scale of Integration Scale Number of Logic First Use Elements Per Chip Small (SSI) Medium (MSI) Large (LSI) , Very Large (VLSI) 10K - 1M 1975 Ultra Large (ULSI) > 1M 1985 > 100M 1998 > 1B 2005 > 1G 2010

11 Process Technologies 8/17 BiPolar - Areas of silicon are doped to be either poor or rich in electrons. Both polarities are used ( p-type and n-type ) to define individual circuit elements. MOS (Metal Oxide Semiconductor) - Doping to define each circuit element is entirely of one polarity, simplifying the manufacturing process. NMOS is faster than PMOS, because electrons are more mobile than holes. CMOS (Complementary MOS) - Both p-type and n- type transistors are fabricated; the same signal that turns on one turns off the other, thereby affording substantial power savings and more dense circuitry.

12 Device Technologies 8/17 Technology Primary Period of Applications Use Silicon BiPolar Computers, consumer products PMOS Early microprocessors NMOS Memory, microprocessors CMOS Battery-powered equipment CMOS (high-speed) Most new designs Gallium Arsenide Microwave radio, radar (GaAs) Optoelectronics Power controllers 1990-

13 Product Categories Standard products - many customers commodity memory microprocessors and microcontrollers Programmable devices - many customers user programs the device Application-specific integrated circuit ( ASIC ) - one customer, one supplier Gate Array (metalize customer-selected options on generic semi-finished wafer) Standard Cell (custom product right from blank wafer start) Full custom

14 Types of Companies Integrated Device Manufacturer (product design, process technology development, manufacturing, marketing) e.g., Intel, Samsung, Micron Fabless (product design and marketing only) e.g., Qualcomm, Nvidia, SanDisk, Apple Foundry (development of process technology and contract manufacturing only) e.g., TSMC, UMC, GlobalFoundries

15 Semiconductor Milestones transistor invented at Bell Labs silicon transistor perfected at Texas Instruments Bi-Polar fab process for integrated circuits perfected at Fairchild Semiconductor Fairchild captures TV electronics market mass exodus from Fairchild to start-up companies; Silicon Valley is born

16 Milestones (cont.) 8/ to MOS process perfected by Gordon Moore and Andrew Grove, Intel develops DRAM, Intel develops EPROM, Intel develops MPU Early 1980s - Japanese companies perfect CMOS, capture most of memory market over the decade Late 1980s - Americans catch up in CMOS, dominate logic markets Early 1990s - Koreans take the lead in memory Late 1990s - Taiwan firms dominate foundry business

17 Global Semiconductor Sales 1985: $27.8 billion (48.9% US cos., 41.2% Japan cos.) 1995: $144.4 billion (40.9% US, 38.9% Japan) 2005: $227.4 billion (48.3% US, 22.6% Japan) 2014: $335.8 billion (memory $79.2 billion, µpus and µcus $62.1 billion, other logic $91.6 billion, analog $44.4 billion, discretes $20.2 billion, power $11.9 billion, all other $26.4 billion)

18 8/ Revenues by Company 1. Intel $48.0 billion (15.2%) 2. Samsung Electronics $29.6 billion (9.4%) 3. Qualcomm $17.3 billion 4. SK Hynix $12.8 billion 5. Micron Technology $11.8 billion 6. Toshiba $11.5 billion 7. Texas Instruments $10.6 billion 8. ST Microelectronics $8.1 billion 9. Broadcom $8.0 billion 10. Renesas $7.8 billion All other $149.9 billion Total $315.4 billion

19 8/17 Process Grow ingots of pure Si and slice into wafers about 300 microns thick Many identical integrated circuits are fabricated on the wafer in the wafer fabrication process Each integrated circuit on the wafer is termed a die or a chip Dice up the completed wafer and package the chips in plastic or ceramic housings with electrical leads (the assembly process)

20 Manufacturing Process (cont.) Fabrication Plant - carries out wafer fabrication process and wafer probe ( die sort ); fabrication plant sometimes called wafer fab for short Back End Plant - carries out assembly process (including wafer dicing) and device testing State-of-the-art 300mm 50 nm wafer fab (with capy of 30K wafer starts per month) ~ $5 B US State-of-the-art back end plant ~ $400 M US

21 Device Feature Sizes Generations of the same device type are differentiated by the minimum feature size, measured in nanometers (billionths of a meter) Each new generation of a device type requires more sophisticated and expensive processing equipment The equipment set in a semiconductor fabrication plant has a capability as to the minimum feature size of the devices that can be produced

22 Feature Sizes 8/17 Minimum Logic Memory Feature Size Device Device 1.2 micron K DRAM 1.0 micron 386 1M DRAM 0.7 micron 486 4M DRAM 0.5 micron Pentium 16M DRAM 0.35 micron Pentium Pro 64M DRAM 0.25 micron P III 256M DRAM 0.18 micron P IV 1G DRAM 0.13 micron 4G DRAM 90 nanometer 16G DRAM 65 nanometer 64G DRAM

23 Process and Product Structure Fabrication Plant Back End Plant Wafer Fab Wafer Bank Wafer Fab Probe Die Bank Assembly Bin Inventory Finished Goods Base Wafer Wafer Die Packaged Device Bins Finished Goods

24 8/17 Wafer Fabrication Processes Photolithography - transferring an image of a pattern onto the surface of the wafer Apply layer of light-sensitive plastic called photoresist, capable of withstanding etching Using a pattern mask, expose the resist to UV light Develop the image, leaving portions of the substrate exposed and the remainder protected by a coating of resist

25 Photolithography Equipment Resist coating and developing tracks Optical equipment ( photo machines ): Contact aligners (features down to 3 microns in size) Projection aligners (1.2 micron) 1X Step-and-repeat ( Steppers ) (1 micron) 5X Steppers (G Line micron, I Line micron) Scanners (latest down to 0.02 micron, i.e., 20 nm) In most cases, coat/develop track and photo machine are linked as one machine

26 Fabrication Processes (cont.) Etching - cutting trenches into the exposed areas of SiO 2 corresponding to the mask pattern Wet Etch - HF or Phosphoric Acid is used; isotropic, so not precise Dry Etch - Gas energized with electric discharge, with reactive ions and radicals present; plasma etching is anisotropic and permits more precise etching

27 8/17 Fabrication Processes (cont.) Oxidation - grow SiO 2 film on the wafers by exposing them to oxygen in a furnace SiO 2 is put down as insulation and as a protective coating between layers of circuitry Diffusion diffuse impurity into exposed silicon by blowing gas containing desired dopant over the wafers Common impurities include boron, phosphorous, nitrogen, polysilicon

28 Diffusion equipment Diffusion furnace - expose batch of wafers to a gas flow. Low cost, but limited accuracy. Same kind of equipment is used for oxidation or for diffusing an impurity a vertical furnace accommodating up to 150 wafers (6 lots). Process time ranges from 2 to 18 hours.

29 8/17 Fabrication Processes (cont.) Ion Implant Vaporize impurity atoms, disassociate the ions in an electric discharge, accelerate a beam of ions in a strong electric field and focus ions on the wafer. High cost, but much better accuracy than diffusion furnaces. Implant dopants species Boron, BF2, Phosphorous, Arsenic, Antominy Implant Equipment Types - High Current, Medium Current and High Energy Ion Implanters

30 8/17 Fabrication Processes (cont.) Metalization - coating wafer surface with metal or metal compounds by various methods: Evaporation - by means of filament contact or electron beam bombardment of metal source, metal vapor is released which settles on to wafers Sputtering - a heavy atom such as Argon is excited by electric discharge and collides with metal target, releasing metal shower on exposed wafers CVD - thermal decomposition of an organometallic compound onto the heated wafer

31 Fabrication Processes (cont.) Chemical Mechanical Polish (CMP) - dielectric insulation deposited between metal layers is ground to precise thickness. (Only used in fabs making logic devices with feature sizes of 0.35 microns or smaller or memory devices with feature sizes of 0.25 microns or smaller.)

32 8/17 Fabrication Processes (cont.) Stripping or ashing - resist removal by wet or dry means, respectively - one wafer at a time Cleaning wafers are rinsed in ultrapure, de-ionized water, followed by a spin-dry - usually 50 wafers at a time Sorting re-shuffle wafers in a given lot into a different order

33 Fabrication Equipment Equipment for metalization, etching, cleaning and ashing may consist of single-chamber tools, or several chambers may be collected into a cluster tool with a shared robot for load/unload One wafer at a time in each chamber Wet operations (etch and clean) are collected into wet benches which comprise a series of tanks served by a robot arm Batch of 50 wafers proceeds through the tanks

34 Overall Fab Process 8/17 A process flow (or process technology) is the complete series of wafer fabrication steps needed to fabricate a particular family of products. Various products produced in the same process flow typically have identical equipment settings ( recipes ) at each step The only difference between products in the same flow is the masks used at the lithography steps.

35 Fab Process Flows (cont.) A fab may have as few as one or as many as 90 different process flows Products in different process flows experience different machine recipes A process flow may have as few as one or as many as 200 different products (wafer types)

36 8/17 Fab Process Characteristics Typically, wafers move from step to step in a cassette holding 25 identical wafers called a lot Great variety of load sizes for equipment: Dry Etch, Ash, Strip, CVD, Metalization, CMP, Sort, Inspect process one wafer at a time. Process times per wafer range minutes. Implant processes 13 wafers at a time (depends on wafer size). Process times per run range 5 75 minutes. Wet cleaning and etching steps process up to 2 lots at a time through a series of tanks. Process times per run range mins. Diffusion furnaces process up to 4 or 5 lots at a time. Process times pre run range 2 16 hours. Photolithography processes one chip at a time. (!) Process times per wafer range 2 10 minutes. Because of the many layers, lots re-visit the same equipment for performance of different steps requiring different process times ( re-entrant flow ).

37 8/17 Typical Wafer Fab Construction Today Three Floors Top floor - airflow equipment Middle floor - fabrication equipment, operators Bottom floor - utilities, water and chemicals distribution Middle floor supported independently to minimize vibration Air flow from ceiling through floor to minimize turbulence (a large fab circulates 7M cu. ft. of air per minute)

38 Typical Fab Layout 8/17 Equipment arranged into bays of like equipment ( farm layout ) Etch Bay Lithography Bay Implant Bay, etc. Automated material handling system such as monorail with lot carriers powered by linearinduction motors connects stockers serving each bay; in most fabs, operators hand-carry wafer lots from stocker to processing machine

39 Typical Fab Operation Wafers move from step to step in a lot of 25 identical wafers. Entire processing sequence in a process flow may include 500 individual steps to define layers of circuitry; average lot may take days to pass through the whole flow. Bar codes on the lots are used for automatic downloading of proper recipe into processing equipment. Computers collect substantial amounts of data about process, wafer and equipment.

40 Scale of Operation 8/17 50,000 wafer starts per month 50 steppers/scanners plus coat/develop tracks 10 high current ion implanters, 8 medium current implanters 40 dry etch machines, 30 CVD machines, 20 metallization machines, 50 diffusion furnace tubes, 50 wafer probe test CPU s 400 operators and technicians, 100 engineers 24 hours per day, 365 days per year

41 Traditional Fab Organization Manufacturing Operators and Supervisors Equipment Technicians Equipment Engineers Process Engineers Device Engineers & Integration Engineers Managers Other engineering and MIS support

42 Die Sort Process Special electrical structures fabricated on the wafer are tested to verify proper electrical characteristics ( sample probe or parametric test or acceptance test ) Next, each chip on each wafer (each die ) is given a full functional test, and bad die are inked ( wafer probe or electrical die sort )

43 Back End Process Wafer dicing, die attach, wire bond, package molding and sealing (the assembly process ) Full functional test of the packaged device at various temperatures ( device test ), branding device ID, high-temperature operation ( burn-in ) followed by re-test, packing for shipment Lot sizes in the back end are ,000 units Testing machines are basically computers with one or more test stations connected

44 Manufacturing Challenges Develop new process flows and ramp up production volume as quickly as possible Insure stable process and product quality Invest in capacity wisely Determine causes of lost yield and lost equipment productivity, and eliminate losses as quickly as possible Reduce total elapsed time ( cycle time ) Improve on-time delivery Load factories to maximum possible revenue

45 Manufacturing Yield Line Yield is the fraction of wafers surviving the fab process flow. Typical line yields: 70-98% Die Yield is the fraction of chips on a completed wafer that function at wafer probe. Typical die yields: 20-95% Causes of line yield loss: Wafer mis-handling Wafer mis-processing Causes of die yield loss: Process out of control (over-etch, under-deposit, etc.) Contamination (particles causing short or open in the circuit)

46 Equipment Productivity Availability is the fraction of time machine is production-worthy (i.e., not under maintenance and not waiting for maintenance) Utilization is the fraction of time machine is engaged in production activity Overall equipment efficiency (OEE) is the should-take time for the work actually completed divided by the total time Typical OEE of fab equipment: 20-80%

47 On-Time Delivery On-time delivery ( LIPAS ) is the fraction of products whose output quantity in the given time period is at least as much as was scheduled. Typical LIPAS for a fab (based on weekly schedules): 60-95% Typical LIPAS to external customers (based on daily schedules): 85-98%

48 Cycle Time Cycle time is what the semiconductor industry calls flow time, i.e., the time it takes manufacturing lots to pass through the entire production process. Typical average cycle times for wafer fabs range from 3 days per mask layer down to (world-class) 1 day per mask layer.

49 Why Cycle Time is Important Facilitates yield improvement Reduces working capital Increases revenue (because of rapid erosion of selling prices for technology goods, especially commodity chips and consumer goods) In short, TIME IS MONEY

50 Summary: The Grand Challenges How do we: Maintain tight control of the manufacturing process to successfully fabricate the circuits Achieve high yield and high productivity Provide excellent on-time delivery Wisely invest in expensive process equipment Rapidly develop, deploy and ramp up new manufacturing technology and new products Compress the time to manufacture

51 IE Job Opportunities Integrated Device Manufacturers In China: many 8/17 In Bay Area: Analog Devices, Maxim, Western Digital, Seagate, Headway Technologies, various Solar companies In Portland: Intel, Analog Devices, Microchip, Maxim In Phoenix: Intel, Microchip In Dallas: Texas Instruments In Korea: Samsung, Hynix In Singapore: Micron, ST Microelectronics, many others Foundries In Albany, NY: Global Foundries In Portland: Wafer Tech (TSMC) In Orange County: Tower Jazz In Dresden, Germany: Global Foundries In Taiwan: TSMC, UMC, other foundries In Singapore: Global Foundries, TSMC, others

52 IE Job Opportunities (cont.) Fabless companies In Bay Area: Western Digital, NVIDIA, Cypress, others In Southern California: Qualcomm, Broadcomm, others Many other locations Equipment companies In Bay Area: Applied Materials, Lam Research, KLA Tencor, Form Factor, others