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1 IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978) Linx Consulting, PO Box 384, Mendon, MA Ph: (617) A Strategic Forecast of the Semiconductor Industry Slide List This report is now complete and available for purchase as a complete report or chapter by chapter. The report is delivered as Power Point presentations with all of the graphs as embedded spreadsheets so that the user can click on the graphs and see the underlying data. The following is a list of the chapters and slides: 1. Chapter 1 The Semiconductor Market 1.1. Chapter Title Slide 1.2. Semiconductor Forecast Methodology 1.3. Worldwide Gross Domestic Product (GDP) Trend (1980 to 2029) 1.4. Worldwide GDP Growth Rate (1980 to 2029) 1.5. GDP Forecast by Region (2009 to 2013) 1.6. GDP Forecast Comments 1.7. Electronics Systems Sales Versus GDP (1980 to 2029) 1.8. Worldwide Electronics Systems Sale Trend (1980 to 2029) 1.9. Electronics Systems Growth Rate (1980 to 2029) Worldwide Electronics Systems Sales Breakout PC and Mobile Device Units Trends (1985 to 2017) Semiconductor Content Semiconductor Versus Electronic Systems (1980 to 2029) Worldwide Semiconductor Sales Trend (1980 to 2029) Semiconductor Sales Growth Rate (1980 to 2029) GDP Versus Electronics Versus Semiconductors (1980 to 2029) Semiconductor Units and Bit Growth (1980 to 2029) NAND Prospects Versus Hard Disc Drives Memory Consolidation ASP Trend (1995 to 2029) Semiconductor Sales by Region (Headquarters) (1982 to 2012) Semiconductor Sales by Where Wafer Fabbed (2000 to 2012) Integrated Circuit Sales by Region (Sold) (1980 to 2012) Projected Semiconductor Sales by End Use Semiconductor Sales by Product (2000 to 2029) Sales by Product Comments Sourcing Comments
2 Worldwide Top Ten Semiconductor Companies Projecting the Future Conclusions 2. Chapter 2 Foundry Versus IDM 2.1. Chapter Title Slide 2.2. Definitions 2.3. Internal Versus Foundry Fab Foundry Gross Margin and R&D Spending 2.5. Internal Versus Foundry Fab Fabless Versus Semiconductor Sales (1998 to 2029) Top 10 Foundries 2.8. Internal Fab Versus Foundry Fab Wafer Cost Versus Country Other Foundry Versus IDM Considerations Foundry Gross Margin % Versus Utilization (TSMC, UMC, SMIC, some Chartered) Foundry Versus IDM Utilization Trends (TSMC, UMC, SMIC, some Chartered) Fab Lite Commentary on Foundry Versus IDM Utilization Foundry ASP Trends (TSMC 90nm, 65nm, 40nm, 28nm, 20nm and 16nm 2010 to 2020) Foundry Node Sales Trends (TSMC by elapsed quarters since introduction for 350nm/250nm, 180nm/150nm, 130nm/110nm, 90nm, 65nm, 40nm, 28nm) Technology Development Costs Versus Node Wafer Cost Versus Fab Size Leading Edge Foundry Outlook Specialty Foundry Conclusion 3. Chapter 3 Logic Device Technology 3.1. Chapter Title Slide 3.2. Logic Device Types 3.3. MOSFET Scaling (Constant Electric Field) 3.4. MOSFET Scaling MOSFET Saturation Drive Current 3.6. Scaling Limitations Velocity Saturation 3.7. Scaling Limitations DIBL 3.8. Scaling Limitations Off State Leakage 3.9. Scaling Limitations Gate Oxide Leakage On State Power Consumption Strain Engineering Compressive Strain Techniques (PMOS) Tensile Strain Techniques (NMOS) Strain Usage (Intel) Strain Usage (Foundries) High k Gate Oxide High k Gate Oxide Selection Issues High k Gate Material Selection Interfacial Layers
3 3.20. High k Gate Oxide Usage by Company High k Metal Gates Dual Metal Gates Why? Metal Gate Candidate Metals Gate First High k Metal Gate (HKMG) Gate Last High k Metal Gate (HKMG) Fully Depleted Devices Full Depleted Silicon on Insulator (FDSOI) FDSOI Substrate Fabrication FDSOI Comments FDSOI Comments FDSOI Roadmap SiGe PMOS by Ge Condensation ssoi Fabrication Process FinFET TriGate Silicon Thickness Comparison (FDSOI versus FinFET versus TriGate) Multi Gate Channel Doping Tri Gates (PMOS shown) Fin Fabrication on Bulk Multi Gate on SOI Multi Gate Device Comments nm Score card High Mobility Channels Aspect Ratio Trapping Germanium Fin Formation High Mobility Channel Integration High Mobility Channel Integration Roadmap Cost Considerations Other Options Conclusion 4. Chapter 4 Memory Device Technology 4.1. Chapter Title Slide 4.2. Memory Hierarchy in Logic Systems 4.3. Memory Taxonomy 4.4. Production Memory Comparison (DRAM, NAND, NOR, SRAM) 4.5. Embedded Memory Comparison (DRAM, NOR, SRAM) 4.6. Prototypical Memory Comparison (FeRAM, MRAM, PCRAM, RRAM) 4.7. Volatile Memory SRAM 4.8. SRAM 4T Versus 6T Cell 4.9. Volatile Memory DRAM DRAM Architecture Folded Bit Line DRAM Architecture Open Bit Line DRAM Capacitor Scaling DRAM Capacitor Scaling DRAM Capacitor Scaling 3
4 4.15. DRAM Capacitor Scaling Capacitor Materials Cylinder Capacitors Cylinder Capacitor MESH Formation DRAM Access Transistor RCAT DRAM Access Transistor Saddle Fin DRAM Access Transistor VCT DRAM Scaling Table Samsung DRAM Scaling Issues Non Volatile Memory Flash NAND Versus NOR Flash NOR Interconnect NAND Versus NOR Flash NAND Versus NOR Flash NAND Scaling table Flash Scaling Challenges Planar Flash Structure D Flash ITRS 3D Flash Layer Forecast D to 3D NAND Transition and Cost Emerging Memory FeRAM MRAM PCRAM RRAM Memory Roadmap Memory Density by Year Conclusion 5. Chapter 5 Analog and Discrete Devices 5.1. Title Slide 5.2. Analog Technology 5.3. Analog Market Size 5.4. Analog Applications Analog Applications Analog Applications Communications Systems 5.7. Analog Modulation 5.8. Interfacing Digital and Analog 5.9. Analog Applications Audio ADC Circuit Requirements Bipolar Versus MOS for Analog Bipolar Versus MOS for Analog Capacitor Quality Resistor Quality Analog Manufacturing Vertical NPN Bipolar Vertical NPN Bipolar BiCMOS
5 5.19. Simple BiCMOS Standard Buried Collector BiCMOS Twin Well BiCMOS Bipolar CMOS DMOS (BCD) Analog CMOS Silicon On Insulator (SOI) Gallium Arsenide (GaAs) SiGe HBT Cut Off Frequency IBM SiGe Processes SiGe HBT SiGe HBT Implementation Communications Process Adders Cell Phone Standards Cell Phone Block Diagram (iphone 4) Discrete Devices Common Power Devices Breakdown Voltage Edge Termination Power MOSFET Optimization Low Voltage Power MOSFET High Voltage Power MOSFET IGBT Thyristor Silicon Carbide (SiC) and Gallium Nitride (GaN) SiC and GaN On Resistance SiC and GaN Substrates SiC and GaN Devices SiC and GaN Status and Outlook 6. Chapter 6 Silicon Forecast 6.1. Title Slide 6.2. Introduction 6.3. Standard Silicon Wafer Sizes 6.4. Silicon Wafer Types 6.5. Worldwide Silicon Demand Versus Semiconductor Revenue (1960 to 2012) 6.6. Revenue Versus Silicon Area (1960 to 2029) 6.7. Silicon Wafer Size Life Cycle 6.8. Silicon Wafer Life Cycle Comments 6.9. New Wafer Size Ramp Silicon Demand Forecast Comments Worldwide Silicon Demand By Wafer Size (logarithmic plot) (1960 to 2029) Worldwide Silicon Demand By Wafer Size (linear plot) (1960 to 2029) Worldwide Silicon Demand By Wafer Size (percentage plot) (1960 to 2029) Silicon Demand by Wafer Size Profiles (2020 and 2030) mm Capacity By Country (linear plot) (2000 to 2020) mm Capacity By Country (area plot) (2000 to 2020) Silicon Demand by Products Comments
6 mm Silicon Demand By Product and Year (Line Chart) (2000 to 2029) mm Silicon Demand By Product and Year (Area Chart) (2000 to 2029) mm Silicon Demand By Product and Year (Line Chart) (2000 to 2029) mm Silicon Demand By Product and Year (Area Chart) (2000 to 2029) Conclusion 7. Chapter 7 Lithography Forecast 7.1. Title Slide 7.2. Lithography Description 7.3. Linewidth Trends 7.4. Basic Process 7.5. Surface Prime 7.6. Coating 7.7. Soft Bake 7.8. Exposure Exposure Exposure Step and Repeat Step and Repeat Die Size Limits Exposure Step and Scan Exposure Step and Scan Step and Scan Die Size Limits Exposure System Stage Control Post Exposure Bake Develop Hard Bake Pellicles Interference Diffraction Resolution Limits Exposing Wavelengths Photoresist Chemistry Photoresist Chemistry Photoresist Chemistry Excimer Lasers Numerical Aperture Immersion Lithography k 1 Trends k 1 Limits (approximate) D Versus 2D Layouts Optical Proximity Correction (OPC) Off Axis Illumination (OAI) Off Axis Illumination (OAI) Source Mask Optimization Phase Shift Masks (PSM) Phase Shift Masks (PSM) Anti Reflective Coatings (ARC) 1
7 7.41. Anti Reflective Coatings (ARC) Chemical Shrink Trim Lithography Stack Complexity Lithography Stack Complexity Image Quality Lith Freeze Litho Etch (LFLE) Litho Etch Litho Etch (LELE) Self Aligned Double Patterning (SADP) CVD Self Aligned Double Patterning (SADP) Spin On Cut Masks Cut Masks Self Aligned Quadruple Patterning (SAQP) Directed Self Assembly (DSA) Polymers Directed Self Assembly (DSA) Techniques Directed Self Assembly (DSA) Issues Extreme Ultraviolet (EUV) EUV System EUV Photoresist Chemistry EUV Masks EUV Roadmap (ASML) EUV Throughput Challenge Lithography Cost With and Without EUV nm Cost Versus EUV Throughput Lithography Roadmap Lithography Roadmap 2 8. Chapter 8 300mm 8.1. Title Slide 8.2. Previous Wafer Size Transitions 8.3. Wafer Area Transitions 8.4. Consortia 8.5. Joint Venture Fabs 8.6. Equipment Development 8.7. Equipment Development Cost 8.8. Equipment Configuration 8.9. Cycle Time mm Versus 200mm Equipment Fab Changes Automation Fab Changes Equipment Size First 300mm Fabs Initial Ramp Fab Capacity Trends Average Fab Size by Product (2013) Wafer Cost Versus Fab Size Starting Substrate Cost Cost Savings Versus 200mm Revenue Required to Support a 300mm Fab
8 mm Capital Efficiency Technology Cross Over Cleanroom Size Capacity by Product Capacity by Country Number of Companies With Fabs Wafer Fab Cost Capacity Leaders Capacity Leaders Capacity Leaders Capacity Leaders Number of Fabs Emerging Applications mm Impact 9. Chapter 9 450mm 9.1. Title Slide 9.2. Introduction 9.3. History 9.4. G450C 9.5. G450C Current Status 9.6. EEMI Development Forecast mm Whats New 9.9. Starting Material Cost Starting Material Suppliers Materials and Utilities Usage Tool Throughput Projected Tool Characteristics Wafer Cost Comparison Equipment Cost Sensitivity Equipment Footprint Sensitivity Consumables Sensitivity mm Fab Scale mm Fab Scale mm Fab Costs Wafer Cost mm Production Timing Early Adopters Fast Followers Number of Companies with Fabs mm Ramp mm Ramp mm Ramp Impact 10. Chapter 10 Packaging Title Slide Introduction
9 10.3. Assembly and Test Market (2002 to 2012) Top 10 OSATs Packaging Options Packaging Volume by Major Category (1995 to 2012) Market by Packaging Type Leadframe Fabrication Process Multilayer Ceramic Fabrication Plastic Laminant Fabrication Process Built Up Substrates Wafer Thinning Wafer Mount for Saw Wafer Sawing Leadframe Assembly Process Leadframe Die Attach Leadframe Die Attach Leadframe Wirebond Leadframe Wirebond Leadframe Molding Leadframe Molding Leadframe Molding Leadframe Singulation Leadframe Singulation Leadframe Package Cut Away Substrate Die Attach Substrate Wirebond Substrate Encapsulation and Singulation Flip Chip Mounting Process Green Packages Stacked Die Interposer Fabrication Interposer Package Through Silicon Via (TSV) Via First Process Through Silicon Via (TSV) Via Middle Process Through Silicon Via (TSV) Via Last Process Comparison of TSV Options TSV Challenges Vertical 3D IC Package 11. Chapter 11 Equipment Market Title Slide Introduction Forecast Methodology ALD and CVD ALD ALD Process ALD System ALD Applications CVD
10 CVD Processes CVD Systems CVD Applications ALD/CVD Market Leaders ALD and CVD Forecast (300mm) (2011 to 2016) CMP CMP Process CMP Process CMP Systems CMP Applications CMP Market Leaders CMP Forecast (300mm) (2011 to 2016) Dry Etching and Ashing Dry Etch Process Dry Etch Process Dry Etch Systems Dry Etch Applications Ashing Process and Systems Dry Etch Market Share Dry Etch and Ashing Forecast (300mm) (2011 to 2016) Exposure Tools Exposure Process Exposure Systems Stage Control Exposure Applications Exposure Equipment Price Trend Exposure Equipment Market Leaders Exposure System Forecast (300mm) (2011 to 2016) Ion Implant Ion Implant Process Ion Implant Systems Ion Implant Applications Ion Implant Applications Ion Implant Market Leaders Ion Implant Forecast (300mm) (2011 to 2016) Metrology and Inspection Metrology and Inspection Applications Metrology and Inspection Applications Metrology and Inspection Applications Metrology and Inspection Applications Metrology and Inspection Market Leaders Metrology and Inspection Forecast (300mm) (2011 to 2016) Plating Plating Process Plating Process Plating Systems Plating Applications Plating Market Leaders
11 Plating Forecast (300mm) (2011 to 2016) PVD PVD Processes PVD Processes PVD Systems PVD Applications PVD Market Leaders PVD Forecast (300mm) (2011 to 2016) Spin On Spin On Market Leaders Spin On Forecast (300mm) (2011 to 2016) Tracks Track Processes Track Processes Track Systems Track Systems Track Applications Track Market Leaders Track Forecast (300mm) (2011 to 2016) Thermal Thermal Processes Thermal Systems Thermal Applications Thermal Market Leaders Thermal Forecast (300mm) (2011 to 2016) Wet Clean and Etch Wet Clean and Etch Processes Wet Clean and Etch System Elements Wet Clean and Etch Systems Wet Clean and Etch Market Leaders Wet Clean and Etch Forecast (300mm) (2011 to 2016) mm Equipment Market by Year Units (2000 to 2029) mm Equipment Market by Year Dollars (2000 to 2029) mm Equipment Market by Year Units (2000 to 2029) mm Equipment Market by Year Dollars (2000 to 2029) Equipment Breakout (2013 and 2023) Equipment Versus Semiconductor Revenue (1990 to 2029) Conclusion 12. Chapter 12 Materials Market Title Introduction Substrates Czochralski Process Substrates Process Substrates Orientation Substrates Market Segmentation
12 12.9. Segment Trends Devices Greater than 100nm Patterning Patterning Materials for >100nm Patterning Materials for >100nm Patterning Materials for >100nm Patterning Materials for >100nm Dielectrics Doping Photoresist Strip Predeposition Cleaaning PMD and ILD Metals Etching Wet Etch Etching Dry Etch Materials Market >100nm Advanced Devices Cost Per Function Trends (Moore s Law) Patterning <100nm Advanced Patterning Materials <100nm Masks and Reticles Advanced Binary Reticles Phase Shift Reticles EUV Reticles Advanced Dielectrics STI and PMD Strain ILD and Low k Dielectrics Implant Metal Deposition ALD PVD CVD Electroplating CMP Total Materials Market Packaging for Advanced Devices Advanced Packaging Materials TSV Conclusions Conclusions Chapter 13 Wafer Cost Title Slide Introduction Profit and Loss Statement Cost of Goods Sold (Fabrication) Wafer Fabrication Cost Map
13 13.6. Starting Wafer Cost Trends Starting Wafer Cost Trends Starting Wafer Prices Direct Labor Hours Per Mask Layer Direct Labor Rate Trends Direct Labor Rates Direct Labor Calculations Amortization and Depreciation Depreciation Capital Cost Trends Capital Investment Depreciation Calculation 28nm Foundry Logic Depreciation Per Wafer 28nm Foundry Logic Equipment Maintenance Indirect Labor Hour Ratios Engineer Salaries Estimating Indirect Labor Rates Indirect Labor Calculation Facilities Cost Categories Facilities Cost Categories Electric Rate Trends Natural Gas Rate Trends Utility Rates Facilities Cost Versus Country Facilities Cost Calculation Monitor Wafers Consumables Consumables Reticle Costs Reticle Amortization Reticle Cost Per Wafer Trends Consumables Summary Wafer Yield Yielded Wafer Cost Example 28nm Wafer Cost Fixed Versus Variable Cost Wafer Cost Versus Utilization Scaling and Cost Real Scaling Intel Scaling Example Cost Versus Time Cost Versus Time Wafer Costs 20nm and 14nm Options Wafer Cost Trends Wafer Cost Trends Wafer Cost Trends Die Cost Effect of a Shrink Pause Conclusion
14 14. Chapter 14 Facilities Title Introduction Cleanliness Requirements Yield Yield Models Cleanroom Concept Cleanroom Filters ISO Cleanroom Standard Multilevel Cleanroom Design Mini Environment Pre 300mm Minienvironment 300mm Cleanroom Requirements Ultrapure Water Systems Ultrapure Gas Distribution Ultrapure Chemical Distribution Exhaust Systems and Abatement Waste Water Treatment Fab Changes Automation Fab Changes Equipment Size Cleanroom Size Versus Output Utilities Trends Cost Trends Cost Trends Conclusion
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