RF LDMOS Wideband Integrated Power Amplifiers

Transcription

1 Technical Data Document Number: A3I35D025WN Rev. 0, 06/2018 RF LDMOS Wideband Integrated ower Amplifiers The A3I35D025WN wideband integrated circuit is designed for cellular base station applications requiring very wide instantaneous bandwidth capability. This circuit includes on--chip matching that makes it usable from 3200 to 4000 MHz. Its multi--stage structure is rated for 20 to 32 V operation and covers all typical cellular base station modulation formats MHz Typical Single--Carrier W--CDMA Characterization erformance: V DD =28Vdc,I DQ1(A+B) =72mA,I DQ2(A+B) = 260 ma, out = 3.4 W Avg., Input Signal AR = % robability on CCDF. (1) Frequency G ps (db) A (%) ACR (dbc) 3400 MHz MHz MHz MHz MHz A3I35D025WNR1 A3I35D025WGNR MHz, 3.4 W AVG., 28 V AIRFAST RF LDMOS WIDBAND INTGRATD OWR AMLIFIRS TO -270WB -17 LASTIC A3I35D025WN TO -270WBG -17 LASTIC A3I35D025WGN Features Designed for wide instantaneous bandwidth applications On--chip matching (50 ohm input, DC blocked) Integrated quiescent current temperature compensation with enable/disable function (2) Designed for digital predistortion error correction systems Optimized for Doherty applications 1. All data measured in fixture with device soldered to heatsink. 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Gotohttp:// and search for AN1977 or AN NX B.V. 1

2 V DS1A RF ina V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation (1) Quiescent Current Temperature Compensation (1) VBW A RF out1 /V DS2A V DS1A V GS2A 1 2 V GS1A 3 RF ina N.C. 4 5 N.C. 6 N.C. 7 N.C. 8 RF inb V GS1B 10 V GS2B 11 V DS1B 12 (2) (3) VBW (4) A RF out1 /V DS2A N.C. RF out2 /V DS2B VBW (4) B RF inb V DS1B RF out2 /V DS2B VBW B (Top View) Note: xposed backside of the package is the source terminal for the transistor. Figure 1. Functional Block Diagram 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Gotohttp:// and search for AN1977 or AN1987. Figure 2. in Connections 2. in connections 1 and 12 are DC coupled and RF independent. 3. in connections 14 and 16 are DC coupled and RF independent. 4. Device can operate with V DD current supplied through pin 13 and pin 17. Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS 0.5, +65 Vdc Gate--Source Voltage V GS 0.5, +10 Vdc Operating Voltage V DD 32, +0 Vdc Storage Temperature Range T stg 65 to +150 C Case Operating Temperature Range T C 40 to +150 C Operating Junction Temperature Range (5,6) T J 40 to +225 C Input ower in 28 dbm Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 70 C, 3.4 W, 3600 MHz Stage 1, 28 Vdc, I DQ1(A+B) =64mA Stage 2, 28 Vdc, I DQ2(A+B) = 260 ma Table 3. SD rotection Characteristics Human Body Model (per JS ) Characteristic Symbol Value (6,7) Unit Test Methodology Charge Device Model (per JS ) Table 4. Moisture Sensitivity Level R JC Class Test Methodology Rating ackage eak Temperature Unit er JSD22--A113, IC/JDC J--STD C 5. Continuous use at maximum temperature will affect MTTF. 6. MTTF calculator available at 7. Refer to AN1955, Thermal Measurement Methodology of RF ower Amplifiers. Go to and search for AN A C1 C/W 2

3 Table 5. lectrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Stage 1 - Off Characteristics Zero Gate Voltage Drain Leakage Current (1) (V DS =65Vdc,V GS =0Vdc) I DSS 10 Adc Zero Gate Voltage Drain Leakage Current (1) (V DS =32Vdc,V GS =0Vdc) Gate--Source Leakage Current (2) (V GS =1.5Vdc,V DS =0Vdc) Stage 1 - On Characteristics Gate Threshold Voltage (2) (V DS =10Vdc,I D =3 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1(A+B) =72mAdc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1(A+B) = 72 madc, Measured in Functional Test) Stage 2 - Off Characteristics Zero Gate Voltage Drain Leakage Current (1) (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (1) (V DS =32Vdc,V GS =0Vdc) Gate--Source Leakage Current (2) (V GS =1.5Vdc,V DS =0Vdc) Stage 2 - On Characteristics Gate Threshold Voltage (2) (V DS =10Vdc,I D =18 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ2(A+B) = 260 madc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2(A+B) = 260 madc, Measured in Functional Test) Drain--Source On--Voltage (1) (V GS =10Vdc,I D = 360 madc) 1. Side A and Side B are tied together for these measurements. 2. ach side of device measured separately. I DSS 5 Adc I GSS 1 Adc V GS(th) Vdc V GS(Q) 3.6 Vdc V GG(Q) Vdc I DSS 10 Adc I DSS 5 Adc I GSS 1 Adc V GS(th) Vdc V GS(Q) 2.8 Vdc V GG(Q) Vdc V DS(on) Vdc (continued) 3

4 Table 5. lectrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Functional Tests (1,2,3) (In NX roduction Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =72mA,I DQ2(A+B) = 260 ma, out = 3.4 W Avg., f = 3600 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal AR = % robability on CCDF. ACR measured in 3.84 MHz Channel 5 MHzOffset. ower Gain G ps db ower Added fficiency A % Adjacent Channel ower Ratio ACR dbc 3 db Compression oint, CW 3dB W Load Mismatch (In NX roduction Test Fixture, 50 ohm system) I DQ1(A+B) =72mA,I DQ2(A+B) = 260 ma, f = 3600 MHz VSWR 10:1 at 32 Vdc, 34 W CW Output ower No Device Degradation (3 db Input Overdrive from 24 W CW Rated ower) Typical erformance (4) (In NX Characterization Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =72mA,I DQ2(A+B) = 260 ma, MHz Bandwidth 3 db Compression oint (5) 3dB 35 W AM/M (Maximum value measured at the 3dB compression point across the MHz frequency range.) 11 VBW Resonance oint (IMD Third Order Intermodulation Inflection oint) Quiescent Current Accuracy over Temperature (6) with 2.2 k Gate Feed Resistors ( 30 to 85 C) Stage 1 with 2.2 k Gate Feed Resistors ( 30 to 85 C) Stage 2 VBW res > 300 MHz I QT Gain Flatness in 400 MHz out =3.4WAvg. G F 0.3 db Gain Variation over Temperature G db/ C ( 40 C to+85 C) Output ower Variation over Temperature ( 40 C to+85 C) Table 6. Ordering Information dB db/ C Device Tape and Reel Information ackage A3I35D025WNR1 TO--270WB--17 R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel A3I35D025WGNR1 TO--270WBG The first stage drains (V DD1A and V DD1B ) and second stage drains (V DD2A and V DD2B ) must be tied together and powered by a single DC power supply. 2. art internally input and output matched. 3. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull wing (GN) parts. 4. All data measured in fixture with device soldered to heatsink. 5. 3dB = avg db where avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output AR is compressed to % probability on CCDF. 6. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Gotohttp:// and search for AN1977 or AN1987. % 4

5 V GG1A V GG2A R1 V DD1A A3I35D025WN V DD2A R2 C7 C8 R5 Z1 C12 C17 C24 C25 C18 C14 C11 C15 C23 CUT OUT ARA C26 C16 C13 C21 C1 C2 C3 C19 C27 C22 C28 C20 C4 C5 C6 Z2 R6 Rev. 6 R4 C9 C10 V GG1B V DD1B R3 V GG2B V DD2B Note: The first stage drains (V DD1A and V DD1B ) and second stage drains (V DD2A and V DD2B )mustbetied together and powered by a single DC power supply. Figure 3. A3I35D025WNR1 roduction Test Circuit Component Layout Table 7. A3I35D025WNR1 roduction Test Circuit Component Designations and Values art Description art Number Manufacturer C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, 10 F Chip Capacitor C3225X7S1H106M250AB TDK C11, C12, C13, C14 C15, C16, C17, C18 10 nf Chip Capacitor C0805C103K5RAC Kemet C19, C20, C21, C22, C23, C24, C25, C pf Chip Capacitor ATC600S3R3BT250XT ATC C27, C pf Chip Capacitor ATC600S0R2BT250XT ATC R1, R2, R3, R4 2.2 k 1/8 W Chip Resistor CRCW08052K20JNA Vishay R5, R6 50, 8 W Termination Chip Resistor C8A50Z4B Anaren Z1, Z MHz Band, 90, 3 db Hybrid Coupler X3C35F1-03S Anaren CB Taconic RF35A2, 0.020, r =3.66 MTL 5

6 V GG2A A3I35D025WN V DD2A D97408 V GG1A R1 V DD1A R2 C7 C8 R5 Z1 C11 C12 C17 C24 C29 C30 C15 C23 C19 Q1 C1 C2 C3 C21 C27 Z2 Rev. 6 C25 C18 C14 C20 C26 C16 C13 C22 C4 C5 C6 C28 R6 R4 C9 C10 V GG1B V DD1B R3 V GG2B V DD2B Note 1: All data measured in fixture with device soldered to heatsink. Note 2: The first stage drains (V DD1A and V DD1B ) and second stage drains (V DD2A and V DD2B )mustbetied together and powered by a single DC power supply. Figure 4. A3I35D025WNR1 Characterization Test Circuit Component Layout MHz Table 8. A3I35D025WNR1 Characterization Test Circuit Component Designations and Values MHz art Description art Number Manufacturer C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, 10 F Chip Capacitor C3225X7S1H106M250AB TDK C11, C12, C13, C14 C15, C16, C17, C18 10 nf Chip Capacitor C0805C103K5RAC Kemet C19, C20, C21, C22, C23, C24, C25, C pf Chip Capacitor ATC600S3R3BT250XT ATC C27, C pf Chip Capacitor ATC600S0R2BT250XT ATC C29, C pf Chip Capacitor ATC600S0R5BT250XT ATC Q1 RF ower LDMOS Transistor A3I35D025WN NX R1, R2, R3, R4 2.2 k 1/8 W Chip Resistor CRCW08052K20JNA Vishay R5, R6 50, 8 W Termination Chip Resistor C8A50Z4B Anaren Z1, Z MHz Band, 90, 3 db Hybrid Coupler X3C35F1-03S Anaren CB Taconic RF35A2, 0.020, r =3.66 D97408 MTL 6

7 Table 9. Load ull erformance Maximum ower Tuning V DD =28Vdc,I DQ1(A) =36mA,I DQ2(A) = 130 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j j j j j j j D (%) AM/M f (MHz) Z source Z in Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j j j j j j j (1) Load impedance for optimum 1dB power. (2) Load impedance for optimum 3dB power. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. D (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load 7

8 Table 10. Load ull erformance Maximum fficiency Tuning V DD =28Vdc,I DQ1(A) =36mA,I DQ2(A) = 130 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max Drain fficiency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j j j j j j j D (%) AM/M f (MHz) Z source Z in Max Drain fficiency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j j j j j j j (1) Load impedance for optimum 1dB efficiency. (2) Load impedance for optimum 3dB efficiency. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. D (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load 8

9 1dB TYICAL LOAD ULL CONTOURS 3600 MHz IMAGINARY RAL RAL Figure 5. 1dB Load ull Output ower Contours (dbm) Figure 6. 1dB Load ull fficiency Contours (%) IMAGINARY IMAGINARY IMAGINARY RAL Figure 7. 1dB Load ull Gain Contours (db) RAL Figure 8. 1dB Load ull AM/M Contours 35 NOT: = Maximum Output ower Gain Drain fficiency Linearity Output ower = Maximum Drain fficiency 9

10 3dB TYICAL LOAD ULL CONTOURS 3600 MHz IMAGINARY IMAGINARY RAL RAL Figure 9. 3dB Load ull Output ower Contours (dbm) Figure 10. 3dB Load ull fficiency Contours (%) IMAGINARY IMAGINARY RAL RAL Figure 11. 3dB Load ull Gain Contours (db) Figure 12. 3dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain fficiency Linearity Output ower = Maximum Drain fficiency 10

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17 RODUCT DOCUMNTATION, SOFTWAR AND TOOLS Refer to the following resources to aid your design process. Application Notes AN1907: Solder Reflow Attach Method for High ower RF Devices in lastic ackages AN1955: Thermal Measurement Methodology of RF ower Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family ngineering Bulletins B212: Using Data Sheet Impedances for RF LDMOS Devices Software lectromigration MTTF Calculator RF High ower Model.s2p File Development Tools rinted Circuit Boards To Download Resources Specific to a Given art Number: 1. Go to 2. Search by part number 3. Click part number link 4. Choose the desired resource from the drop down menu The following table summarizes revisions to this document. RVISION HISTORY Revision Date Description 0 June 2018 Initial release of data sheet 17

18 How to Reach Us: Home age: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NX products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NX reserves the right to make changes without further notice to any products herein. NX makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NX assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in NX data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. NX does not convey any license under its patent rights nor the rights of others. NX sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. NX, the NX logo and Airfast are trademarks of NX B.V. All other product or service names are the property of their respective owners NX B.V. Document Number: A3I35D025WN 18 Rev. 0, 06/2018