RF LDMOS Wideband Integrated Power Amplifiers

Transcription

1 Freescale Semiconductor Technical Data RF LDMOS Wideband Integrated ower Amplifiers The A2I22D050N wideband integrated circuit is designed with on--chip matching that makes it usable from 1800 to 2200 MHz. This multi--stage structure is rated for 24 to 32 V operation and covers all typical cellular base station modulation formats MHz Typical Single--Carrier W--CDMA Characterization erformance: V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, out = 5.3 W Avg., Input Signal AR = % robability on CCDF. (1) Frequency G ps (db) A (%) ACR (dbc) 2110 MHz MHz MHz MHz Typical Single--Carrier W--CDMA erformance: V DD =28Vdc, I DQ1(A+B) =70mA,I DQ2(A+B) = 470 ma, out = 5.3 W Avg., Input Signal AR = % robability on CCDF. (1) Frequency G ps (db) A (%) ACR (dbc) 1805 MHz MHz MHz Document Number: A2I22D050N Rev. 1, 3/2015 A2I22D050NR1 A2I22D050GNR MHz, 5.3 W AVG., 28 V AIRFAST RF LDMOS WIDBAND INTGRATD OWR AMLIFIRS TO -270WB -15 LASTIC A2I22D050NR1 TO -270WBG -15 LASTIC A2I22D050GNR1 1. All data measured in fixture with device soldered to heatsink. Features On--Chip Matching (50 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with nable/disable Function (2) Designed for Digital redistortion rror Correction Systems Optimized for Doherty Applications V DS1A RF ina V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation (2) Quiescent Current Temperature Compensation (2) RF out1 /V DS2A V DS1A V GS2A 1 2 V GS1A 3 RF ina N.C. 4 5 GND 6 GND 7 N.C. 8 RF inb V GS1B 10 V GS2B 11 V DS1B RF out1 /V DS2A 14 GND 13 RF out2 /V DS2B RF inb V DS1B Figure 1. Functional Block Diagram RF out2 /V DS2B (Top View) Note: xposed backside of the package is the source terminal for the transistors. Figure 2. in Connections 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes AN1977 or AN1987., All rights reserved. 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS 0.5, +65 Vdc Gate Source Voltage V GS 0.5, +10 Vdc Operating Voltage V DD 32, +0 Vdc Storage Temperature Range T stg 5 to +150 C Case Operating Temperature Range T C 40 to +150 C Operating Junction Temperature Range (1,2) T J 40 to +225 C Input ower in 28 dbm Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 80 C, 5.3 W CW, 2140 MHz Stage 1, 28 Vdc, I DQ1(A+B) =80mA Stage 2, 28 Vdc, I DQ2(A+B) = 520 ma Table 3. SD rotection Characteristics Human Body Model (per JSD22--A114) Machine Model (per IA/JSD22--A115) Characteristic Symbol Value (2,3) Unit Test Methodology Charge Device Model (per JSD22--C101) Table 4. Moisture Sensitivity Level R JC Class Test Methodology Rating ackage eak Temperature Unit er JSD22--A113, IC/JDC J--STD C Table 5. lectrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 1B A II C/W Stage 1 - Off Characteristics Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =32Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) I DSS 10 Adc I DSS 1 Adc I GSS 1 Adc Stage 1 - On Characteristics Gate Threshold Voltage (V DS =10Vdc,I D =12 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1(A+B) =80mAdc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1(A+B) = 80 madc, Measured in Functional Test) V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF ower Amplifiers. Go to Select Documentation/Application Notes AN1955. (continued) 2

3 Table 5. lectrical Characteristics (T A =25 C unless otherwise noted) (continued) Stage 2 - Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =32Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 2 - On Characteristics Gate Threshold Voltage (1) (V DS =10Vdc,I D =46 Adc) Characteristic Symbol Min Typ Max Unit Gate Quiescent Voltage (V DS =28Vdc,I DQ2(A+B) = 520 madc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2(A+B) = 520 madc, Measured in Functional Test) Drain--Source On--Voltage (1) (V GS =10Vdc,I D =1Adc) I DSS 10 Adc I DSS 1 Adc I GSS 1 Adc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc V DS(on) Vdc Functional Tests (2,3) (In Freescale roduction Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, out = 5.3 W Avg., f = 2140, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal AR = % robability on CCDF. ACR measured in 3.84 MHz Channel 5 MHzOffset. ower Gain G ps db ower Added fficiency A % Input Return Loss IRL db 1 db Compression oint, CW 1dB W Load Mismatch (4) (In Freescale Characterization Test Fixture, 50 ohm system) I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, f = 2140 MHz VSWR 10:1 at 32 Vdc, 63 W CW Output ower No Device Degradation (3 db Input Overdrive from 45 W CW Rated ower) Typical erformance (4) (In Freescale Characterization Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, MHz Bandwidth 3 db Compression oint, CW (5) 3dB 56 W AM/M.8 (Maximum value measured at the 3dB compression point across the MHz frequency range.) VBW Resonance oint (IMD Third Order Intermodulation Inflection oint) VBW res 70 MHz Quiescent Current Accuracy over Temperature (6) with 4.7 k Gate Feed Resistors ( 30 to 85 C) Stage 1 with 4.7 k Gate Feed Resistors ( 30 to 85 C) Stage 2 I QT Gain Flatness in 60 MHz out =5.3WAvg. G F 0.4 db Gain Variation over Temperature G db/ C ( 30 C to+85 C) Output ower Variation over Temperature ( 30 C to+85 C) Table 6. Ordering Information dB db/ C Device Tape and Reel Information ackage A2I22D050NR1 TO--270WB--15 R1 Suffix = 500 Units, 44 mm Tape Width, 13--Reel A2I22D050GNR1 TO--270WBG ach side of device measured separately. 2. art internally input matched. 3. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull wing (GN) parts. 4. All data measured in fixture with device soldered to heatsink. 5. 3dB = avg db where avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output AR is compressed to % probability on CCDF. 6. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Documentation/Application Notes AN1977 or AN1987. % 3

4 C1 C9 C5 C7 C3 V DD1A V GG2A C13 C11 V DD2A D59213 C25* R1 C21* C23* V GG1A R2 C14 C27* C18 C29* C17 C19 Q1 C20 C30* C26* R3 C22* C24* V R4 GG1B V GG2B V DD1B C2 C15 C16 C6 C8 C10 C12 C28* V DD2B C4 A2I22D050N Rev. 1 *C21, C22, C23, C24, C25, C26, C27, C28, C29 and C30 are mounted vertically. Note: All data measured in fixture with device soldered to heatsink. roduction fixture does not include device soldered to heatsink. Figure 3. A2I22D050NR1 Characterization Test Circuit Component Layout MHz Table 7. A2I22D050NR1 Characterization Test Circuit Component Designations and Values MHz art Description art Number Manufacturer C1, C2, C3, C4 10 F Chip Capacitors GRM55DR61H106KA88L Murata C5, C6 5.6 pf Chip Capacitors ATC600F5R6BT250XT ATC C7, C8 6.2 pf Chip Capacitors ATC600F6R2BT250XT ATC C9, C10 1 F Chip Capacitors GRM31MR71H105KA88L Murata C11, C12, C13, C14, C15, C F Chip Capacitors GRM31CR71H475KA12L Murata C17, C18, C19, C20 33 pf Chip Capacitors ATC600F330JT250XT ATC C21, C pf Chip Capacitors ATC600F0R3BT250XT ATC C23, C24, C25, C26, C27, C pf Chip Capacitors ATC600F0R2BT250XT ATC C29, C pf Chip Capacitors ATC600F1R1BT250XT ATC Q1 RF LDMOS ower Amplifier A2I22D050NR1 Freescale R1, R2, R3, R4 4.7 k, 1/4 W Chip Resistors CRCW12064K70FKA Vishay CB Rogers RO4350B, 0.020, r =3.66 D59213 MTL 4

5 TYICAL CHARACTRISTICS MHz V DD =28Vdc, out =5.3W(Avg.) I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth A Input Signal AR = % robability on CCDF ARC IRL G ps ACR f, FRQUNCY (MHz) Figure 4. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 5.3 Watts Avg. G ps, OWR GAIN (db) A, OWR ADDD FFICINCY (%) ACR (dbc) IRL, INUT RTURN LOSS (db) ARC (db) IMD, INTRMODULATION DISTORTION (dbc) V DD =28Vdc, out = 17 W (), I DQ1(A+B) =80mA I DQ2(A+B) = 520 ma, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 2140 MHz IM5 U IM3 U IM5 L IM7 L IM3 L IM7 U TWO TON SACING (MHz) Figure 5. Intermodulation Distortion roducts versus Two -Tone Spacing G ps, OWR GAIN (db) OUTUT COMRSSION AT 0.01% ROBABILITY ON CCDF (db) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma f = 2140 MHz, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth ACR 1 db = 10 W A 3 2 db = 15.4 W G ps db = 20.7 W Input Signal AR = % 10 5 robability on CCDF ARC A, OWR ADDD FFICINCY (%) ACR (dbc) out, OUTUT OWR (WATTS) Figure 6. Output eak -to -Average Ratio Compression (ARC) versus Output ower 5

6 TYICAL CHARACTRISTICS MHz G ps, OWR GAIN (db) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma Single--Carrier W--CDMA, 3.84 MHz Channel 2170 MHz Bandwidth, Input Signal AR = % 2140 MHz robability on CCDF 2110 MHz 2110 MHz 2170 MHz 2140 MHz MHz 2110 MHz ACR G 2170 MHz ps A out, OUTUT OWR (WATTS) AVG. Figure 7. Single -Carrier W -CDMA ower Gain, ower Added fficiency and ACR versus Output ower A, OWR ADDD FFICINCY (%) ACR (dbc) Gain 3 GAIN (db) 25 9 IRL (db) 20 IRL V DD =28Vdc 15 in =0dBm 15 I DQ1(A+B) =80mA I 10 DQ2(A+B) = 520 ma f, FRQUNCY (MHz) Figure 8. Broadband Frequency Response 6

7 Table 8. Load ull erformance Maximum ower Tuning V DD =28Vdc,I DQ1A =40mA, I DQ2A = 260 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j A (%) AM/M f (MHz) Z source Z in Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB power. (2) Load impedance for optimum 3dB power. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 9. Load ull erformance Maximum ower Added fficiency Tuning V DD =28Vdc,I DQ1A =40mA, I DQ2A = 260 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max ower Added fficiency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j A (%) A (%) AM/M AM/M f (MHz) Z source Z in Max ower Added fficiency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB efficiency. (2) Load impedance for optimum 3dB efficiency. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. A (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load 7

8 1dB TYICAL LOAD ULL CONTOURS 2140 MHz IMAGINARY RAL Figure 9. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 10. 1dB Load ull fficiency Contours (%) IMAGINARY RAL Figure 11. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 12. 1dB Load ull AM/M Contours Gain ower Added fficiency Linearity Output ower NOT: = Maximum Output ower = Maximum ower Added fficiency 8

9 3dB TYICAL LOAD ULL CONTOURS 2140 MHz IMAGINARY RAL Figure 13. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 14. 3dB Load ull fficiency Contours (%) IMAGINARY RAL Figure 15. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 16. 3dB Load ull AM/M Contours Gain ower Added fficiency Linearity Output ower NOT: = Maximum Output ower = Maximum ower Added fficiency 9

10 C1 C7 C5 C3 V DD1A V GG2A C11 C9 V DD2A D59213 R1 V GG1A C12 C27* C21* C19* C23* C24* C20* C22* R4 C15 C17 R2 R3 V GG1B Q1 C13 C25 C26 C16 C18 C28* V GG2B V DD1B C14 C8 C6 C10 V DD2B A2I22D050N Rev. 1 C2 C4 *C19, C20, C21, C22, C23, C24, C27 and C28 are mounted vertically. Note: All data measured in fixture with device soldered to heatsink. Figure 17. A2I22D050NR1 Test Circuit Component Layout MHz Table 10. A2I22D050NR1 Test Circuit Component Designations and Values MHz art Description art Number Manufacturer C1, C2, C3, C4 10 F Chip Capacitors GRM55DR61H106KA88L Murata C5, C6 6.8 pf Chip Capacitors ATC600F6R8BT250XT ATC C7, C8 1 F Chip Capacitors GRM31MR71H105KA88L Murata C9, C10, C11, C12, C13, C F Chip Capacitors GRM31CR71H475KA12L Murata C15, C16, C17, C18 47 pf Chip Capacitors ATC600F470JT250XT ATC C19, C pf Chip Capacitors ATC600F0R2BT250XT ATC C21, C pf Chip Capacitors ATC600F0R3BT250XT ATC C23, C pf Chip Capacitors ATC600F0R9BT250XT ATC C25, C pf Chip Capacitors ATC600F0R1BT250XT ATC C27, C pf Chip Capacitors ATC600F1R2BT250XT ATC Q1 RF LDMOS ower Amplifier A2I22D050NR1 Freescale R1, R2, R3, R4 4.7 k Chip Resistors CRCW12064K70FKA Vishay CB Rogers RO4350B, 0.020, r =3.66 D59213 MTL 10

11 TYICAL CHARACTRISTICS MHz G ps, OWR GAIN (db) 32.6 V DD =28Vdc, out =5.3W(Avg.),I DQ1(A+B) =70mA I DQ2(A+B) = 470 ma, Single--Carrier W--CDMA MHz Channel Bandwidth Input Signal AR = % robability on CCDF A IRL G ps ACR ARC f, FRQUNCY (MHz) A, OWR ADDD FFICINCY (%) Figure 18. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 5.3 Watts Avg. ACR (dbc) 4 IRL, INUT RTURN LOSS (db) ARC (db) G ps, OWR GAIN (db) V DD =28Vdc,I DQ1(A+B) =70mA I DQ2(A+B) = 470 ma, Single--Carrier W--CDMA 1805 MHz 1840 MHz 1880 MHz G ps 3.84 MHz Channel Bandwidth, Input Signal AR = % robability on CCDF 1880 MHz 1840 MHz 1805 MHz ACR MHz 10 A 1840 MHz 1805 MHz out, OUTUT OWR (WATTS) AVG. Figure 19. Single -Carrier W -CDMA ower Gain, ower Added fficiency and ACR versus Output ower A, OWR ADDD FFICINCY (%) ACR (dbc) Gain 4 GAIN (db) 30 IRL (db) 29 V DD =28Vdc 28 IRL in =0dBm I DQ1(A+B) =70mA 27 I DQ2(A+B) = 470 ma f, FRQUNCY (MHz) Figure 20. Broadband Frequency Response 11

12 Table 11. Load ull erformance Maximum ower Tuning V DD =28Vdc,I DQ1A =40mA, I DQ2A = 260 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j A (%) AM/M f (MHz) Z source Z in Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB power. (2) Load impedance for optimum 3dB power. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 12. Load ull erformance Maximum ower Added fficiency Tuning V DD =28Vdc,I DQ1A =40mA, I DQ2A = 260 ma, ulsed CW, 10 sec(on), 10% Duty Cycle f (MHz) Z source Z in Max ower Added fficiency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j A (%) A (%) AM/M AM/M f (MHz) Z source Z in Max ower Added fficiency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB efficiency. (2) Load impedance for optimum 3dB efficiency. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. A (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load 12

13 1dB TYICAL LOAD ULL CONTOURS 1840 MHz IMAGINARY RAL Figure 21. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 22. 1dB Load ull fficiency Contours (%) 34 IMAGINARY IMAGINARY RAL Figure 23. 1dB Load ull Gain Contours (db) RAL Figure 24. 1dB Load ull AM/M Contours NOT: = Maximum Output ower Gain ower Added fficiency Linearity Output ower = Maximum ower Added fficiency 13

14 IMAGINARY dB TYICAL LOAD ULL CONTOURS 1840 MHz RAL RAL Figure 25. 3dB Load ull Output ower Contours (dbm) Figure 26. 3dB Load ull fficiency Contours (%) IMAGINARY IMAGINARY RAL Figure 27. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 28. 3dB Load ull AM/M Contours Gain ower Added fficiency Linearity Output ower NOT: = Maximum Output ower = Maximum ower Added fficiency 14

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21 RODUCT DOCUMNTATION, SOFTWAR AND TOOLS Refer to the following resources to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF ower Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family ngineering Bulletins B212: Using Data Sheet Impedances for RF LDMOS Devices Software lectromigration MTTF Calculator RF High ower Model.s2p File Development Tools rinted Circuit Boards For Software and Tools, do a art Number search at and select the art Number link. Go to Software & Tools on the part s roduct Summary page to download the respective tool. The following table summarizes revisions to this document. RVISION HISTORY Revision Date Description 0 Nov Initial release of data sheet 1 Mar Figs. 4, 6--7 and : changed drain efficiency to power added efficiency for plots and axes labels, pp. 5--6, 11 Tables 7--8 and : changed drain efficiency to power added efficiency, pp. 7, 12 21

22 How to Reach Us: Home age: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. Freescale and the Freescale logo are trademarks of, Reg. U.S. at. & Tm. Off. Airfast is a trademark of All other product or service names are the property of their respective owners Document Number: A2I22D050N 22 Rev. 1, 3/2015