RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET

Transcription

1 Freescale Semiconductor Technical Data RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET Designed for Class A or Class AB power amplifier applications with frequencies up to 2000 MHz. Suitable for analog and digital modulation and multicarrier amplifier applications. Typical Two--Tone 1960 MHz, 28 Vdc, I DQ =50mA, P out = 4 W PEP Power Gain 18 db Drain Efficiency 33% IMD --34 dbc Typical Two--Tone 900 MHz, 28 Vdc, I DQ =50mA, P out = 4 W PEP Power Gain 19 db Drain Efficiency 33% IMD --39 dbc Capable of Handling 5:1 28 Vdc, 1960 MHz, 4 W CW Output Power Features Characterized with Series Equivalent Large--Signal Impedance Parameters On--Chip RF Feedback for Broadband Stability Integrated ESD Protection In Tape and Reel. T1 Suffix = 1,000 Units,16 mm Tape Width, 7--inch Reel. Document Number: MMRF1014N Rev. 0, 7/ MHz, 4 W, 28 V CLASS A/AB RF POWER MOSFET PLD -1.5 PLASTIC Gate Drain Note: The center pad on the backside of the package is the source terminal for the transistor. Figure 1. Pin Connections Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --0.5, +68 Vdc Gate--Source Voltage V GS --0.5, +12 Vdc Storage Temperature Range T stg to +150 C Operating Junction Temperature T J 150 C Table 2. Thermal Characteristics Characteristic Symbol Value (1,2) Unit Thermal Resistance, Junction to Case Case Temperature 76 C, 4 W PEP, Two--Tone Case Temperature 79 C, 4 W CW Table 3. ESD Protection Characteristics Human Body Model (per JESD22--A114) Machine Model (per EIA/JESD22--A115) Test Methodology Charge Device Model (per JESD22--C101) R JC Class 1C A IV C/W 1. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 2. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN1955., All rights reserved. 1

2 Table 4. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD22--A113, IPC/JEDEC J--STD C Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics Zero Gate Voltage Drain Leakage Current (V DS =68Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =5Vdc,V DS =0Vdc) On Characteristics Gate Threshold Voltage (V DS =10Vdc,I D =50mAdc) Gate Quiescent Voltage (V DS =28Vdc,I D =50mAdc) Fixture Gate Quiescent Voltage (1) (V DD =28Vdc,I D = 50 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =10Vdc,I D =50mAdc) Dynamic Characteristics Reverse Transfer Capacitance (V DS =28Vdc 30 1 MHz, V GS =0Vdc) Output Capacitance (V DS =28Vdc 30 1 MHz, V GS =0Vdc) Input Capacitance (V DS =28Vdc,V GS =0Vdc 30 1 MHz) I DSS 10 Adc I DSS 10 Adc I GSS 500 nadc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc V DS(on) Vdc C rss 21 pf C oss 25 pf C iss 30 pf Functional Tests (In Freescale Test Fixture, 50 ohm system) V DD =28Vdc,I DQ =50mA,P out = 4 W PEP, f1 = 1960 MHz, f2 = MHz, Two--Tone Test Power Gain G ps db Drain Efficiency D % Intermodulation Distortion IMD dbc Input Return Loss IRL db Typical Performance (In Freescale 900 MHz Demo Board, 50 ohm system) V DD =28Vdc,I DQ =50mA,P out = 4 W PEP, f = 900 MHz, Two--Tone Test, 100 khz Tone Spacing Power Gain G ps 19 db Drain Efficiency D 33 % Intermodulation Distortion IMD dbc Input Return Loss IRL db 1. V GG = 11 / 10 xv GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit Schematic. 2

3 V BIAS R1 V SUPPLY + C8 R2 C1 C7 Z5 C3 C4 C5 RF INPUT Z1 R3 Z2 Z3 Z4 Z6 Z10 Z7 Z8 C6 Z9 RF OUTPUT C2 DUT Z1 Z2 Z3 Z4 Z5 Z x Microstrip x Microstrip x Microstrip x Microstrip x Microstrip x Microstrip Z x Microstrip Z x Microstrip Z x Microstrip Z x Microstrip PCB Arlon CuClad 250GX , 0.020, r =2.5 Figure 2. Test Circuit Schematic Table 6. Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1 100 nf Chip Capacitor CDR33BX104AKYS Kemet C2, C3, C6, C7 9.1 pf Chip Capacitors ATC100B9R1CT500XT ATC C4, C5 10 F, 50 V Chip Capacitors GRM55DR61H106KA88B Murata C8 10 F, 35 V Tantalum Chip Capacitor T490D106K035AT Kemet R1 1k, 1/4 W Chip Resistor CRCW FKEA Vishay R2 10 k, 1/4 W Chip Resistor CRCW FKEA Vishay R3 10, 1/4 W Chip Resistor CRCW120610R0FKEA Vishay 3

4 25 C8 R1 R2 C1 C7 C3 C4 C5 C2 R3 C6 Figure 3. Test Circuit Component Layout 4

5 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =28Vdc,P out =2W(Avg.) I DQ = 50 ma, 100 khz Tone Spacing IM3 f, FREQUENCY (MHz) 1970 IRL 1980 D G ps Figure 4. Two -Tone Wideband out = 2 Watts Avg D, DRAIN EFFICIENCY (%) IM3 (dbc) IRL, INPUT RETURN LOSS (db) G ps, POWER GAIN (db) I DQ =75mA 62.5 ma 50 ma 37.5 ma 25 ma 0.1 V DD =28Vdc f1 = 1960 MHz, f2 = MHz Two--Tone Measurements IMD, INTERMODULATION DISTORTION (dbc) V DD =28Vdc,I DQ =50mA f1 = 1960 MHz, f2 = MHz Two--Tone Measurements 3rd Order 5th Order 0.1 7th Order 1 10 P out, OUTPUT POWER (WATTS) PEP Figure 5. Two -Tone Power Gain versus Output Power P out, OUTPUT POWER (WATTS) PEP Figure 6. Intermodulation Distortion Products versus Output Power IMD, INTERMODULATION DISTORTION (dbc) V DD =28Vdc,P out =2W(Avg.),I DQ =50mA (f1 + f2)/2 = Center Frequency of 1960 MHz 45 3rd Order 5th Order 7th Order TWO--TONE SPACING (MHz) Figure 7. Intermodulation Distortion Products versus Tone Spacing P out, OUTPUT POWER (dbm) P3dB = dbm (6.637 W) P1dB = dbm (5.768 W) P6dB = dbm (7.465 W) V DD =28Vdc,I DQ =50mA Pulsed CW, 8 sec(on), 1 msec(off) f = 1960 MHz P in, INPUT POWER (dbm) 24 Ideal Actual Figure 8. Pulsed CW Output Power versus Input Power 26 5

6 TYPICAL CHARACTERISTICS D, DRAIN EFFICIENCY (%), G ps, POWER GAIN (db) V DD =28Vdc,I DQ =50mA f = 1960 MHz, N--CDMA IS--95 (Pilot, Sync, 40 Paging, Traffic Codes 8 Through 13) G 20 ps ACPR --60 D P out, OUTPUT POWER (WATTS) AVG. Figure 9. Single -Carrier CDMA ACPR, Power Gain and Drain Efficiency versus Output Power ACPR (db) T C =--30_C G ps --30_C 50 G ps, POWER GAIN (db) _C 85_C V DD =28Vdc I DQ =50mA f = 1960 MHz D 85_C D DRAIN EFFICIENCY (%) P out, OUTPUT POWER (WATTS) CW Figure 10. Power Gain and Drain Efficiency versus CW Output Power G ps, POWER GAIN (db) I DQ =50mA f = 1960 MHz 15.5 V DD =24V V 32 V P out, OUTPUT POWER (WATTS) CW Figure 11. Power Gain versus Output Power S21 (db) S21 14 V DD =28Vdc --20 P out =2WCW S11 I DQ =50mA f, FREQUENCY (MHz) Figure 12. Broadband Frequency Response S11 (db) 6

7 Z o =10 Z load f = 1990 MHz f = 1930 MHz f = 1990 MHz Z source f = 1930 MHz f MHz V DD =28Vdc,I DQ =50mA,P out = 4 W PEP Z source Z load j j j j j j7.97 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network Device Under Test Output Matching Network Z source Z load Figure 13. Series Equivalent Source and Load Impedance 7

8 Table 7. Common Source S -Parameters (V DD =28Vdc,I DQ =50mA,T A =25 C, 50 Ohm System) f S 11 S 21 S 12 S 22 MHz S 11 S 21 S 12 S (continued) 8

9 Table 7. Common Source S -Parameters (V DD =28Vdc,I DQ =50mA,T A =25 C, 50 Ohm System) (continued) f MHz S 11 S 21 S 12 S 22 S 11 S 21 S 12 S

10 inches mm Figure 14. Solder Footprint for PLD -1.5 M1014 N( )QQ YYWW Figure 15. Product Marking 10

11 PACKAGE DIMENSIONS 11

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14 PRODUCT DOCUMENTATION AND SOFTWARE Refer to the following resources to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator For Software, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. REVISION HISTORY The following table summarizes revisions to this document. Revision Date Description 0 July 2014 Initial Release of Data Sheet 14

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