RF LDMOS Wideband Integrated Power Amplifiers

Transcription

1 Freescale Semiconductor Technical Data Document Number: A2I2D4N Rev., 4/216 RF LDMOS Wideband Integrated ower Amplifiers The A2I2D4N wideband integrated circuit is designed with on--chip matching that makes it usable from 14 to 22 MHz. This multi--stage structure is rated for 2 to 32 V operation and covers all typical cellular base station modulation formats MHz Typical Single--Carrier W--CDMA Characterization erformance: V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma, out =WAvg., Input Signal AR = 9.9 robability on CCDF. (1) Frequency G ps (db) A (%) ACR (dbc) 18 MHz MHz A2I2D4NR1 A2I2D4GNR MHz, W AVG., 28 V AIRFAST RF LDMOS WIDBAND INTGRATD OWR AMLIFIRS TO -27WB -17 LASTIC A2I2D4NR1 2 MHz MHz MHz All data measured in fixture with device soldered to heatsink. Features xtremely Wide RF Bandwidth RF Decoupled Drain ins Reduce Overall Board Space On--Chip Matching ( Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with nable/disable Function (2) TO -27WBG -17 LASTIC A2I2D4GNR1 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to and search for AN1977 or AN1987., 216. All rights reserved. A2I2D4NR1 A2I2D4GNR1 1

2 V DS1A RF ina V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation (1) Quiescent Current Temperature Compensation (1) VBW A RF out1 /V DS2A V DS1A V GS2A 1 2 V GS1A 3 RF ina N.C. 4 GND 6 GND 7 N.C. 8 RF inb V GS1B V GS2B 11 V DS1B VBW (2) A RF out1 /V DS2A GND RF out2 /V DS2B VBW (2) B RF inb V DS1B RF out2 /V DS2B VBW B (Top View) Note: xposed backside of the package is the source terminal for the transistors. Figure 1. Functional Block Diagram 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Gotohttp:// and search for AN1977 or AN1987. Figure 2. in Connections 2. Device can operate with V DD current supplied through pin 13 and pin 17. Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS., +6 Vdc Gate--Source Voltage V GS., + Vdc Operating Voltage V DD 32, + Vdc Storage Temperature Range T stg 6 to + C Case Operating Temperature Range T C 4 to + C Operating Junction Temperature Range (3,4) T J 4 to +22 C Input ower in 18 dbm Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 78 C, W, 19 MHz Stage 1, 28 Vdc, I DQ1(A+B) =6mA Stage 2, 28 Vdc, I DQ2(A+B) = 22 ma Table 3. SD rotection Characteristics Human Body Model (per JSD22--A114) Machine Model (per IA/JSD22--A11) Characteristic Symbol Value (4,) Unit Test Methodology Charge Device Model (per JSD22--C1) Table 4. Moisture Sensitivity Level R JC Class Test Methodology Rating ackage eak Temperature Unit er JSD22--A113, IC/JDC J--STD C 3. Continuous use at maximum temperature will affect MTTF. 4. MTTF calculator available at Refer to AN19, Thermal Measurement Methodology of RF ower Amplifiers. Go to and search for AN19. 1B A II C/W A2I2D4NR1 A2I2D4GNR1 2

3 Table. lectrical Characteristics (T A =2 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Stage 1 - Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =6Vdc,V GS =Vdc) I DSS Adc Zero Gate Voltage Drain Leakage Current (V DS =32Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =1.Vdc,V DS =Vdc) Stage 1 - On Characteristics Gate Threshold Voltage (1) (V DS =Vdc,I D =3. Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1(A+B) =6mAdc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1(A+B) = 6 madc, Measured in Functional Test) Stage 2 - Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =6Vdc,V GS =Vdc) Zero Gate Voltage Drain Leakage Current (V DS =32Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =1.Vdc,V DS =Vdc) I DSS 1 Adc I GSS 1 Adc V GS(th) Vdc V GS(Q) 1.9 Vdc V GG(Q) Vdc I DSS Adc I DSS 1 Adc I GSS 1 Adc Stage 2 - On Characteristics Gate Threshold Voltage (1) (V DS =Vdc,I D =22 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ2(A+B) = 22 madc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2(A+B) = 22 madc, Measured in Functional Test) Drain--Source On--Voltage (1) (V GS =Vdc,I D = 22 madc) 1. ach side of device measured separately. V GS(th) Vdc V GS(Q) 1.8 Vdc V GG(Q) Vdc V DS(on) Vdc (continued) A2I2D4NR1 A2I2D4GNR1 3

4 Table. lectrical Characteristics (T A =2 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Functional Tests (1,2) (In Freescale roduction Test Fixture, ohm system) V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma, out = W Avg., f = 19 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal AR = 9.9 robability on CCDF. ACR measured in 3.84 MHz Channel MHzOffset. ower Gain G ps db ower Added fficiency A % Adjacent Channel ower Ratio ACR dbc 3 db Compression oint, CW 3dB W Load Mismatch (In Freescale roduction Test Fixture, ohm system) I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma, f = 22 MHz VSWR :1 at 32 Vdc, 46.8 W CW Output ower No Device Degradation (3 db Input Overdrive from 4.7 W CW Rated ower) Typical erformance (3) (In Freescale Characterization Test Fixture, ohm system) V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma, MHz Bandwidth 1 db Compression oint, CW 1dB 36.3 W 3 db Compression oint (4) 3dB 44.6 W AM/M (Maximum value measured at the 3dB compression point across the MHz frequency range.) 11.8 VBW Resonance oint (IMD Third Order Intermodulation Inflection oint) Quiescent Current Accuracy over Temperature () with2k Gate Feed Resistors (--3 to 8 C) Stage 1 with2k Gate Feed Resistors (--3 to 8 C) Stage 2 VBW res 18 MHz I QT Gain Flatness in 4 MHz out =WAvg. G F.9 db Gain Variation over Temperature ( 3 C to+8 C) G.38 db/ C % Output ower Variation over Temperature ( 3 C to+8 C) 1dB.7 db/ C Table 6. Ordering Information Device Tape and Reel Information ackage A2I2D4NR1 A2I2D4GNR1 R1 Suffix = Units, 44 mm Tape Width, 13--Reel TO--27WB--17 TO--27WBG art internally input and output matched. 2. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull wing (GN) parts. 3. All data measured in fixture with device soldered to heatsink. 4. 3dB = avg + 7. db where avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output AR is compressed to 7. probability on CCDF.. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to and search for AN1977 or AN1987. A2I2D4NR1 A2I2D4GNR1 4

5 V DD1A V GG2A V GG1A R C17 Z1 R4 C18 C1 R1 R2 R3 C16 C C7 Q1 C8 C6 C13 C11 C9 C3 C4 C C12 C14 V DD2A C1 Z2 C2 R6 A2I2D4N Rev. 4 V GG1B V GG2B V DD2B D776 V DD1B Note: All data measured in fixture with device soldered to heatsink. roduction fixture does not include device soldered to heatsink. Figure 3. A2I2D4NR1 Test Circuit Component Layout Table 7. A2I2D4NR1 Test Circuit Component Designations and Values art Description art Number Manufacturer C1, C2 8.2 pf Chip Capacitors ATC6F8R2BT2XT ATC C3, C4.3 pf Chip Capacitors ATC6FR3BT2XT ATC C, C6, C7, C8, C9, C, C11, C12, C13, C14 F Chip Capacitors GRM31CR61H6KA12L Murata C1, C16, C17, C F Chip Capacitors GRM31CR71H47KA12L Murata Q1 RF LDMOS ower Amplifier A2I2D4NR1 NX R1, R2, R3, R4 4.7 k, 1/4 W Chip Resistors CRCW1264K7FKA Vishay R, R6, W Chip Resistors 612A2Z--2 Anaren Z1, Z MHz, 9, 3 db Hybrid Couplers X3C191-3S Anaren CB Rogers RO43B,.2, r =3.66 D776 MTL A2I2D4NR1 A2I2D4GNR1

6 TYICAL CHARACTRISTICS MHz G ps, OWR GAIN (db) V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2 (A+B) = 22 ma 33.4 out = W (Avg.), Single--Carrier W--CDMA MHz Channel Bandwidth G ps ARC ACR Input Signal AR = 9.9 robability on CCDF f, FRQUNCY (MHz), DRAIN FFICINCY (%) Figure 4. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = Watts Avg. ACR (dbc) ARC (db) IMD, INTRMODULATION DISTORTION (dbc) V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma out =W(Avg.), out = 24 W, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 2 MHz IM--L IM--U IM3--U IM3--L IM7--U IM7--L TWO--TON SACING (MHz) Figure. Intermodulation Distortion roducts versus Two -Tone Spacing 3 G ps, OWR GAIN (db) OUTUT COMRSSION AT.1% ROBABILITY ON CCDF (db) db = 4.99 W 2 db = 7.26 W V DD =28Vdc,I DQ1(A+B) =6mA I DQ2(A+B) = 22 ma, f = 2 MHz 3 db =.6 W ACR 4 2 ARC G ps 1 Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth Input Signal AR = 9.9 robability on CCDF out, OUTUT OWR (WATTS) Figure 6. Output eak -to -Average Ratio Compression (ARC) versus Output ower RAIN FFICINCY (%) ACR (dbc) A2I2D4NR1 A2I2D4GNR1 6

7 TYICAL CHARACTRISTICS MHz G ps, OWR GAIN (db) V DD =28Vdc,I DQ1(A+B) =6mA,I DQ2(A+B) = 22 ma Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth Input Signal AR = 9.9 robability G ps 22 MHz ACR 2 MHz 18 MHz 18 MHz 2 MHz 22 MHz 2 MHz 3 22 MHz 18 MHz out, OUTUT OWR (WATTS) AVG. Figure 7. Single -Carrier W -CDMA ower Gain, Drain fficiency and ACR versus Output ower , DRAIN FFICINCY (%) ACR (dbc) 36 GAIN (db) Gain V DD =28Vdc in =dbm I DQ1(A+B) =6mA I DQ2(A+B) = 22 ma f, FRQUNCY (MHz) Figure 8. Broadband Frequency Response A2I2D4NR1 A2I2D4GNR1 7

8 Table 8. Load ull erformance Maximum ower Tuning V DD =28Vdc,I DQ =111mA, ulsed CW, sec(on), % Duty Cycle f (MHz) Z source Z in Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j (%) AM/M f (MHz) Z source Z in Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB power. (2) Load impedance for optimum 3dB power. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 9. Load ull erformance Maximum Drain fficiency Tuning V DD =28Vdc, I DQ =111mA, ulsed CW, sec(on), % Duty Cycle f (MHz) Z source Z in Max Drain fficiency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j (%) (%) AM/M AM/M f (MHz) Z source Z in Max Drain fficiency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j8. 7. j j (1) Load impedance for optimum 1dB efficiency. (2) Load impedance for optimum 3dB efficiency. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load A2I2D4NR1 A2I2D4GNR1 8

9 1dB - TYICAL LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 9. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure. 1dB Load ull fficiency Contours (%) IMAGINARY RAL Figure 11. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 12. 1dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain fficiency Linearity Output ower = Maximum Drain fficiency A2I2D4NR1 A2I2D4GNR1 9

10 3dB - TYICAL LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 13. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 14. 3dB Load ull fficiency Contours (%) IMAGINARY RAL RAL Figure 1. 3dB Load ull Gain Contours (db) 33 IMAGINARY Figure 16. 3dB Load ull AM/M Contours Gain Drain fficiency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain fficiency A2I2D4NR1 A2I2D4GNR1

11 Table. Load ull erformance Maximum ower Tuning V DD =28Vdc,I DQ =111mA, ulsed CW, sec(on), % Duty Cycle f (MHz) Z source Z in Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j (%) AM/M f (MHz) Z source Z in Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB power. (2) Load impedance for optimum 3dB power. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 11. Load ull erformance Maximum Drain fficiency Tuning V DD =28Vdc, I DQ =111mA, ulsed CW, sec(on), % Duty Cycle f (MHz) Z source Z in Max Drain fficiency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j (%) (%) AM/M AM/M f (MHz) Z source Z in Max Drain fficiency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance for optimum 1dB efficiency. (2) Load impedance for optimum 3dB efficiency. Z source = Measured impedance presented to the input of the device at the package reference plane. Z in = Impedance as measured from gate contact to ground. Z load = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. (%) AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z source Z in Z load A2I2D4NR1 A2I2D4GNR1 11

12 1dB - TYICAL LOAD ULL CONTOURS 214 MHz IMAGINARY RAL RAL Figure 17. 1dB Load ull Output ower Contours (dbm) Figure 18. 1dB Load ull fficiency Contours (%) IMAGINARY IMAGINARY RAL RAL Figure 19. 1dB Load ull Gain Contours (db) Figure 2. 1dB Load ull AM/M Contours IMAGINARY Gain Drain fficiency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain fficiency A2I2D4NR1 A2I2D4GNR1 12

13 3dB - TYICAL LOAD ULL CONTOURS 214 MHz RAL RAL Figure 21. 3dB Load ull Output ower Contours (dbm) Figure 22. 3dB Load ull fficiency Contours (%) IMAGINARY IMAGINARY 3. 6 IMAGINARY RAL Figure 23. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 24. 3dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain fficiency Linearity Output ower = Maximum Drain fficiency A2I2D4NR1 A2I2D4GNR1 13

14 ACKAG DIMNSIONS A2I2D4NR1 A2I2D4GNR1 14

15 A2I2D4NR1 A2I2D4GNR1 1

16 A2I2D4NR1 A2I2D4GNR1 16

17 A2I2D4NR1 A2I2D4GNR1 17

18 A2I2D4NR1 A2I2D4GNR1 18

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20 RODUCT DOCUMNTATION, SOFTWAR AND TOOLS Refer to the following resources to aid your design process. Application Notes AN197: Solder Reflow Attach Method for High ower RF Devices in Over--Molded lastic ackages AN19: Thermal Measurement Methodology of RF ower Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family ngineering Bulletins B212: Using Data Sheet Impedances for RF LDMOS Devices Software lectromigration MTTF Calculator RF High ower Model.s2p File Development Tools rinted Circuit Boards To Download Resources Specific to a Given art Number: 1. Go to 2. Search by part number 3. Click part number link 4. Choose the desired resource from the drop down menu The following table summarizes revisions to this document. RVISION HISTORY Revision Date Description Apr. 216 Initial Release of Data Sheet A2I2D4NR1 A2I2D4GNR1 2

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