30V N-Channel Enhancement Mode MOSFET DESCRIPTION FEATURE APPLICATIONS PIN CONFIGURATION. Top View

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1 30V N-Channel Enhancement Mode MOSFET DESCRIPTION The up6400 is the N-Channel logic enhancement mode power field effect transistor is produced using high cell density advanced trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applciation, power management and other DC-DC converter. FEATURE R DS(ON) =1.8mΏ(typ.)@VGS= 10V R DS(ON) =2.6mΏ(typ.)@VGS= 4.5V Super high design for extremely low R DS(ON) Exceptional on-resistance and Maximum DC current capability Full RoHS compliance SOP8 package design 100% UIS Tested 100% Rg tested APPLICATIONS Power Management DC/DC Converter Load Switch PIN CONFIGURATION Top View DFN5X6 Bottom View Top View D G PIN1 S up 6400 Rev A 1 / 8 com

2 PART NUMBER INFORMATION UP6400AA-BB C A= Package Code P: PQFN5X 6 BB=Handing Code TR: Tape&Reel C=Lead Plating Code G: Green Product P: Pb free ORDERING INFORMATION Part Number UP6400AP-TRG Package Code Package Shipping P PQFN5X6 3000EA / T&R Year Code : 0~9 Week Code : A~Z(1-26); a~z(27~52) G : Green Product. This product is RoHS compliant. ABSOLUTE MAXIMUM RATINGS ( T A = 25 Unless otherwise noted ) V DS V GS I T A = 25 I T A = 70 I T C(Bottom) = 25 I T C(Bottom) = 100 I DM P A = 25 P T C(Bottom) = 25 T J T STG Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, V 10V Continuous Drain Current, V 10V Continuous Drain Current, V 10V Continuous Drain Current, V 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Max. 30 ± to Units V A W W/ Note: Absolute maximum ratings are those values bey ond which the device could be permanently damaged. Absolute maximum ratings are stress rating only and functional device operation is not implied up6400rev A 2 / 8 com

3 ELECTRICAL CHARACTERISTICS (T A =25 Unless otherwise noted) Symbol Parameter Condition Min Typ Max Unit Static Parameters V (BR)DSS Drain-Source Breakdown Voltage V GS =0V, I D = 250uA 30 V V GS(th) Gate Threshold Voltage V DS =V GS, I D = 250uA V I GSS Gate Leakage Current V DS =0V, V GS =±25V ±100 na V DS =-24V, V GS =0 1 I DSS Zero Gate Voltage Drain Current V DS =-24V, V GS =0 ua 30 T J =85 R DS(ON) V GS = 10V, I D = 50 A Drain-Source On-Resistance m V GS = 4.5V, I D = 45 A Source-Drain Diode V SD Diode Forward Voltage I S = 50 A, V GS =0V V Dynamic Parameters Q g Total Gate Charge V DS =15V 81 Q gs Gate-Source Charge V GS =10V 19 nc Q gd Gate-Drain Charge I D = 50 A 15 C iss Input Capacitance V DS = 15V 5540 C oss Output Capacitance V GS =0V 1320 pf C rss Reverse Transfer Capacitance f=1mhz 78 T d(on) V DS = 15V 19 Turn-On Time T r I D = 50A 11 T V GEN = d(off) 4.5V 54 Turn-Off Time R G =3 16 T f Note: 1. Pulse test: pulse width<=300us, duty cycle <=2% 2.Static parameters are based on package level with recommended wire bonding ns up6400 Rev A 3 / 8 com

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6 up6400 PQFN 5x6 Outline Package Details PQFN 5x6 Outline Part Marking UNIVERSAL LOGO DATE CODE ASSEMBLY SITE CODE UP XXXX XYWWX XXXXX PIN 1 IDENTIFIER PART NUMBER ( 4 or 5 digits ) MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 digits of EATI#) (Prod Mode - 4 digits of SPN code) up6400 Rev A 6/8

7 SOLDERING METHODS FOR UNIVERCHIP Storage environment Temperature=10 ~35 Humidity=65%±15% Reflow soldering of surface mount device Profile Feature Sn-Pb Eutectic Assembly Pb free Assembly Average ramp-up rate (T L to T P ) <3 /sec <3 /sec Preheat -Temperature Min (Ts min ) -Temperature Max (Ts max ) -Time (min to max) (ts) Tsmax to T L -Ramp-up Rate Time maintained above -Temperature (T L ) -Time (t L ) ~120 sec <3 /sec ~150 sec ~180 sec <3 /sec ~150 sec Peak Temperature (T P ) / /-5 Time within 5 of actual Peak Temperature (t P ) 10~30 sec 20~40 sec Ramp-down Rate <6 /sec <6 /sec Time 25 to Peak Temperature <6 minutes <6 minutes up6400rev A 7 / 8 com

8 Flow (wave) soldering (solder dipping) Product Peak Temperature Dipping Time Pb device 245 ±5 5sec±1sec Pb-Free device /-5 5sec±1sec This integrated circuit can be damaged by ESD Univer Chip Corporation recommends that all integrated cir cuits be handled with appropriate precautions. Failure to observe proper handling and installation procedure can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integraetd circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its pub lished specifications. up6400rev A 8 / 8 com