YJG80G06A. N-Channel Enhancement Mode Field Effect Transistor

Transcription

1 RoHS COMPLIANT Top View N-Channel Enhancement Mode Field Effect Transistor PDFN 5X6 8L Bottom View Product Summary V DS I D (at V GS =10V) R DS(ON) ( at V GS =10V) R DS(ON) ( at V GS =4.5V) 100% UIS Tested 100% Rg Tested 100% VDS Tested 60V 80A <4.2mΩ <5.2mΩ Top View Pin1 Pin1 General Description Split Gate Trench Power MV MOSFET technology Low R DS(ON) Low Gate Charge Optimized for fast-switching applications Applications Synchronous Rectification in DC/DC and AC/DC Converters Industrial and Motor Drive application Absolute Maximum Ratings (T =25 unless otherwise noted) A Parameter Symbol Maximum Unit Drain-source Voltage V DS 60 V Gate-source Voltage V GS ±20 V Drain Current G T C =25 T C = I D 80 A Pulsed Drain Current C I DM 320 A Avalanche energy L=0.5mH C E AS 450 mj Power Dissipation A T C =25 P DSM T C = W Junction and Storage Temperature Range T J,T STG -55~+150 Thermal Characteristics Junction-to-Ambient A T 10s Parameter Symbol Typ. Max. Unit R θja / W Junction-to-Ambient A D Steady-State / W Junction-to-Case Steady-State R θjc / W Ordering Information (Example) PREFERED P/N PACKING CODE Marking MINIMUM PACKAGE(pcs) INNER BOX QUANTITY(pcs) OUTER CARTON QUANTITY(pcs) DELIVERY MODE YJG53G06A F reel 1 / 7

2 Electrical Characteristics (T J =25 unless otherwise noted) Parameter Symbol Conditions Min Typ Max Units Static Parameter Drain-Source Breakdown Voltage BV DSS V GS = 0V, I D =250μA V Zero Gate Voltage Drain Current I DSS V DS =60V,V GS =0V 1 V DS =60V,V GS =0V,T J =55 5 μa Gate-Body Leakage Current I GSS V GS = ±20V, V DS =0V ±100 na Gate Threshold Voltage V GS(th) V DS = V GS, I D =250μA V Static Drain-Source On-Resistance R DS(ON) V GS = 10V, I D =40A V GS = 4.5V, I D =40A mω Diode Forward Voltage g FS V DS =5V,I D =40A 30 S Diode Forward Voltage V SD I S =40A,V GS =0V V Maximum Body-Diode Continuous Current G I S 80 A Dynamic Parameters Input Capacitance C iss 3980 Output Capacitance C oss V DS =30V,V GS =0V,f=1MHZ 690 pf Reverse Transfer Capacitance C rss 24 Gate Resistance R g V DS =0V,V GS =0V,f=1MHZ 2.5 Ω Switching Parameters Total Gate Charge Q g (10V) 67 Total Gate Charge Q g (4.5V) 32 V GS =10V,V DS =30V,I D =20A Gate Source Charge Q gs 12 nc Gate Drain Charge Q gd 8.5 Turn-on Delay Time t D(on) 15 Turn-on Rise Time t r V GS =10V,V DS =15V,R L =2.5Ω, 8 Turn-off Delay Time t D(off) R GEN =3Ω 48 ns Turn-off Fall Time t f 12 Body Diode Reverse Recovery Time t rr I F =Is,di/dt=500A/us 48 Body Diode Reverse Recovery Charge Q rr I F =Is,di/dt=500A/us 60 nc A. The value of R θja is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with T A =25 C. The Power dissipation P DSM is based on R θja t 10s and the maximum allowed junction temperature of 150 C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) =150 C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Single pulse width limited by junction temperature T J(MAX) =150 C. D. The R θja is the sum of the thermal impedance from junction to case R θjc and case to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300μs pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-case thermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) =150 C. The SOA curve provides a single pulse rating. G. The maximum current rating is package limited. 2 / 7

3 Typical Performance Characteristics 3 / 7

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6 PDFN 5X6-8L Package information Symbol Min. Typ. Max A A REF D E D E D E k b e L H / 7

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