AOD405 P-Channel Enhancement Mode Field Effect Transistor

Transcription

1 Jan 4 P-Channel Enhancement Mode Field Effect Transistor General Description The uses advanced trench technology to provide excellent R DS(ON), low gate chargeand low gate resistance. With the excellent thermal resistance of the DPAK package, this device is well suited for high current load applications. Features V DS (V) = -V I D = -18A R DS(ON) < 32mΩ (V GS = V) R DS(ON) < 6mΩ (V GS = V) TO-252 D-PAK D Top View Drain Connected to Tab G S G D S Absolute Maximum Ratings T A =25 C unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Symbol V DS V GS Maximum - ± Continuous Drain T A =25 C G -18 Current B,G T A = C B I D -18 Pulsed Drain Current Avalanche Current C I DM I AR Repetitive avalanche energy L=.1mH C E AR 16 T C =25 C 6 Power Dissipation B P D T C = C T A =25 C 2.5 P DSM Power Dissipation A T A =7 C 1.6 Junction and Storage Temperature Range T J, T STG -55 to 175 Units V V A A mj W W C Thermal Characteristics Parameter Symbol Typ Max Units Maximum Junction-to-Ambient A t s C/W R Maximum Junction-to-Ambient A θja Steady-State 4 5 C/W Maximum Junction-to-Case C Steady-State R θjl C/W

2 Electrical Characteristics (T J =25 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS Drain-Source Breakdown Voltage I D =-25µA, V GS =V - V I DSS Zero Gate Voltage Drain Current V DS =-24V, V GS =V -1 T J =55 C -5 µa I GSS Gate-Body leakage current V DS =V, V GS =±V ± na V GS(th) Gate Threshold Voltage V DS =V GS I D =-25µA V I D(ON) On state drain current V GS =-V, V DS =-5V -4 A V GS =-V, I D =-18A R DS(ON) Static Drain-Source On-Resistance T J =125 C mω V GS =-4.5V, I D =-A 41 6 mω g FS Forward Transconductance V DS =-5V, I D =-18A 17 S V SD Diode Forward Voltage I S =-1A,V GS =V V I S Maximum Body-Diode Continuous Current -18 A DYNAMIC PARAMETERS C iss Input Capacitance 9 1 pf C oss Output Capacitance V GS =V, V DS =-15V, f=1mhz 19 pf C rss Reverse Transfer Capacitance 122 pf R g Gate resistance V GS =V, V DS =V, f=1mhz Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge (V) nc Q g (4.5V) Total Gate Charge (4.5V) 9.7 nc V GS =-V, V DS =-15V, I D =-18A Q gs Gate Source Charge 2.54 nc Q gd Gate Drain Charge 5.4 nc t D(on) Turn-On DelayTime 7.8 ns t r Turn-On Rise Time V GS =-V, V DS =-15V, R L =.82Ω, 8.7 ns t D(off) Turn-Off DelayTime R GEN =3Ω 17.7 ns t f Turn-Off Fall Time 8.5 ns t rr Body Diode Reverse Recovery Time I F =-18A, di/dt=a/µs ns Q rr Body Diode Reverse Recovery Charge I F =-18A, di/dt=a/µs 13 nc A: The value of R θja is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25 C. The value in any a given application depends on the user's specific board design. The current rating is based on the t s thermal resistance rating. B: Repetitive rating, pulse width limited by junction temperature. C. The R θja is the sum of the thermal impedence from junction to lead R θjl and lead to ambient. D. The static characteristics in Figures 1 to 6,12,14 are obtained using 8 µs pulses, duty cycle.5% max. E. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25 C. The SOA curve provides a single pulse rating.

3 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 25 -V -6V -5V -4.5V 25 V DS =-5V -4V -I D (A) 15 -I D (A) V 5 V GS =-3V V DS (Volts) Fig 1: On-Region Characteristics C 25 C V GS (Volts) Figure 2: Transfer Characteristics R DS(ON) (mω) V GS =-4.5V V GS =-V I D (A) Figure 3: On-Resistance vs. Drain Current and Gate Voltage Normalized On-Resistance V GS =-4.5V I D =-A V GS =-V I D =-18A Temperature ( C) Figure 4: On-Resistance vs. Junction Temperature R DS(ON) (mω) C I D =-18A 125 C V GS (Volts) Figure 5: On-Resistance vs. Gate-Source Voltage -I S (A) 1.E+1 1.E+ 1.E-1 1.E-2 1.E-3 1.E-4 1.E-5 1.E C 25 C V SD (Volts) Figure 6: Body-Diode Characteristics

4 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 1.E+1 8.E+ V DS =-15V I D =-18A C iss -V GS (Volts) 6.E+ 4.E+ 2.E+ Capacitance (pf) C oss C rss.e Q g (nc) Figure 7: Gate-Charge Characteristics V DS (Volts) Figure 8: Capacitance Characteristics -I D (Amps).. 1. T J(Max) =15 C, T A =25 C R DS(ON) limited 1s 1ms ms.1s µs µs Power (W) 4 T J(Max) =15 C T A =25 C s DC V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note E) Pulse Width (s) Figure : Single Pulse Power Rating Junction-to- Ambient (Note E) Z θja Normalized Transient Thermal Resistance 1.1 D=T on /T T J,PK =T A +P DM.Z θja.r θja R θja =4 C/W Single Pulse In descending order D=.5,.3,.1,.5,.2,.1, single pulse P D T on T Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance

5 ALPHA & OMEGA SEMICONDUCTOR, INC. Document No. Version Title PD-115 rev A Package Data Sheet DIMENSION IN MILLIMETERS DIMENSIONS IN INCHES GAUGE PLANE SEATING PLANE SEE DETAIL 'D' A A1 A2 b b1 b2 c c1 D D1 E E1 e e1 H L L1 L2 MIN NOM. MAX BSC BSC MIN. NOM. MAX BSC..18 BSC DETAIL 'D' SCALE: 1.5X NOTE 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND GATE BURRS 2. DIMENSION L IS MEASURED IN GAGE PLANE 3. TOLERANCE. mm UNLESS OTHERWISE SPECIFIED 4. CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. 5. FOLLOWED FROM JEDEC TO-252 (AA) PACKAGE MARKING DESCRIPTION RECOMMENDED LAND PATTERN D 4 5 F A Y W L T NOTE: D45 F&A Y W L T - AOS LOGO - PART NUMBER CODE. -FOUNDRY AND ASSEMBLY LOCATION - YEAR CODE - WEEK CODE. - ASSEMBLY LOT CODE DPAK PART NO. CODE PART NO. CODE D45 UNIT: mm

6 ALPHA & OMEGA SEMICONDUCTOR, INC. TO-252 (DPAK) Tape and Reel Data TO-252 (DPAK) Carrier Tape TO-252 (DPAK) Reel TO-252 (DPAK) Leader / Trailer & Orientation