MC34071,2,4,A MC33071,2,4,A, NCV33074A

Transcription

1 MC347,2,4,A MC337,2,4,A, NCV3374A Single Supply 3. V to 44 V Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC337/72/74, MC347/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 3 V/ s slew rate and fast settling time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (V EE ). With a Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC337/72/74, MC347/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC and TSSOP surface mount packages. 4 PDIP P SUFFIX CASE 626 SOIC D SUFFIX CASE 75 PDIP4 P SUFFIX CASE 646 Features Wide Bandwidth: 4.5 MHz High Slew Rate: 3 V/ s Fast Settling Time:. s to.% Wide Single Supply Operation: 3. V to 44 V Wide Input Common Mode Voltage Range: Includes Ground (V EE) Low Input Offset Voltage: 3. mv Maximum (A Suffix) Large Output Voltage Swing: 4.7 V to 4 V (with ±5 V Supplies) Large Capacitance Drive Capability: pf to, pf Low Total Harmonic Distortion:.2% Excellent Phase Margin: 6 Excellent Gain Margin: 2 db Output Short Circuit Protection ESD Diodes/Clamps Provide Input Protection for Dual and Quad PbFree Packages are Available 4 4 SOIC4 D SUFFIX CASE 75A TSSOP4 DTB SUFFIX CASE 94G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 26 October, 26 Rev. Publication Order Number: MC347/D

2 MC347,2,4,A MC337,2,4,A, NCV3374A PIN CONNECTIONS CASE 626/CASE 75 CASE 646/CASE 75A/CASE 94G Offset Null NC Output 2 7 V CC Inputs 3 6 Output Inputs V EE 4 5 Offset Null V CC (Single, Top View) Inputs 2 Output V CC 2 7 Output 2 Output 2 Inputs 3 6 Inputs 2 V EE 4 5 (Dual, Top View) (Quad, Top View) Output 4 Inputs 4 V EE Inputs 3 Output 3 V CC Q Q3 Q4 Q5 Q6 Q7 Bias Q2 Q R Q9 C Q Q D2 Q7 R6 R7 Q Output Inputs R C2 D3 Q9 Base Current Cancellation Q2 D Q3 Q4 Q5 R5 Q6 Current Limit R3 R4 Offset Null (MC337, MC347 only) V EE /GND Figure. Representative Schematic Diagram (Each Amplifier) MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (from V EE to V CC ) V S 44 V Input Differential Voltage Range V IDR (Note ) V Input Voltage Range V IR (Note ) V Output Short Circuit Duration (Note 2) t SC Indefinite Sec Operating Junction Temperature T J 5 C Storage Temperature Range T stg 6 to 5 C. Either or both input voltages should not exceed the magnitude of V CC or V EE. 2. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded (see Figure 2). 2

3 MC347,2,4,A MC337,2,4,A, NCV3374A ELECTRICAL CHARACTERISTICS (V CC = 5 V, V EE = 5 V, R L = connected to ground, unless otherwise noted. See Note 3 for T A = T low to T high ) A Suffix NonSuffix Characteristics Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage (R S =, V CM = V, = V) V CC = 5 V, V EE = 5 V, V CC = 5. V, V EE = V, V CC = 5 V, V EE = 5 V, T A = T low to T high Average Temperature Coefficient of Input Offset Voltage R S =, V CM = V, = V, T A = T low to T high Input Bias Current (V CM = V, = V) T A = T low to T high Input Offset Current (V CM = V, = V) T A = T low to T high Input Common Mode Voltage Range T A = T low to T high Large Signal Voltage Gain ( = ± V, R L = 2. k ) T A = T low to T high Output Voltage Swing (V ID = ±. V) V CC = 5. V, V EE = V, R L = 2. k, V CC = 5 V, V EE = 5 V, R L = k, V CC = 5 V, V EE = 5 V, R L = 2. k, T A = T low to T high V CC = 5. V, V EE = V, R L = 2. k, V CC = 5 V, V EE = 5 V, R L = k, V CC = 5 V, V EE = 5 V, R L = 2. k, T A = T low to T high V IO V IO / T V/ C I IB I IO V ICR A VOL 5 25 H L 6. V EE to (V CC.) V EE to (V CC 2.2) V EE to (V CC.) V EE to (V CC 2.2) mv na na V V/mV V V Output Short Circuit Current (V ID =. V, = V, ) Source Sink Common Mode Rejection R S k, V CM = V ICR, Power Supply Rejection (R S = ) V CC /V EE = 6.5 V/6.5 V to 3.5 V/3.5 V, I SC CMR db PSR db ma Power Supply Current (Per Amplifier, No Load) V CC = 5. V, V EE = V, = 2.5 V, V CC = 5 V, V EE = 5 V, = V, V CC = 5 V, V EE = 5 V, = V, T A = T low to T high I D ma 3. T low = 4 C for MC337, 2, 4, /A T high = 5 C for MC337, 2, 4, /A = C for MC347, 2, 4, /A = 7 C for MC347, 2, 4, /A = 4 C for MC3472, 4/V = 25 C for MC3472, 4/V 3

4 MC347,2,4,A MC337,2,4,A, NCV3374A AC ELECTRICAL CHARACTERISTICS (V CC = 5 V, V EE = 5 V, R L = connected to ground., unless otherwise noted.) A Suffix NonSuffix Characteristics Symbol Min Typ Max Min Typ Max Unit Slew Rate ( = V to V, R L = 2. k, C L = 5 pf) A V =. A V =. Setting Time ( V Step, A V =.) To.% (/2 LSB of 9Bits) To.% (/2 LSB of 2Bits) SR Gain Bandwidth Product (f = khz) GBW MHz Power Bandwidth A V =., R L = 2. k, = 2 V pp, THD = 5.% t s V/ s BW 6 6 khz s Phase margin R L = 2. k R L = 2. k, C L = 3 pf Gain Margin R L = 2. k R L = 2. k, C L = 3 pf Equivalent Input Noise Voltage R S =, f =. khz Equivalent Input Noise Current f =. khz Differential Input Resistance V CM = V Differential Input Capacitance V CM = V Total Harmonic Distortion A V =, R L = 2. k, 2. V pp 2 V pp, f = khz f m A m Deg e n nv/ Hz i n pa/ Hz R in 5 5 M C in pf THD.2.2 % db Channel Separation (f = khz) 4

5 MC347,2,4,A MC337,2,4,A, NCV3374A P, D MAXIMUM POWER DISSIPATION (mw) SOIC4 Pkg & 4 Pin Plastic Pkg SOIC Pkg T A, AMBIENT TEMPERATURE ( C) Figure 4. Maximum Power Dissipation versus Temperature for Package Types VМ, V IO INPUT OFFSET VOLTAGE (mv) T A, AMBIENT TEMPERATURE ( C) V CC = 5 V V EE = 5 V V CM = Figure 5. Input Offset Voltage versus Temperature for Representative Units V CC V CC. V CC.6 V CC 2.4 V CC V CC /V EE =.5 V/.5 V to 22 V/ 22 V V EE. V EE V EE T A, AMBIENT TEMPERATURE ( C) VМ, ICR INPUT COMMON MODE VOLTAGE RANGE (V) IМ, IB INPUT BIAS CURRENT (NORMALIZED) T A, AMBIENT TEMPERATURE ( C) V CC = 5 V V EE = 5 V V CM = Figure 6. Input Common Mode Voltage Range versus Temperature Figure 7. Normalized Input Bias Current versus Temperature IМ, IB INPUT BIAS CURRENT (NORMALIZED) V CC = 5 V V EE = 5 V V IC, INPUT COMMON MODE VOLTAGE (V), OUTPUT VOLTAGE SWING (V pp ) R L Connected to Ground R L = k R L = 2. k V CC, V EE, SUPPLY VOLTAGE (V) Figure. Normalized Input Bias Current versus Input Common Mode Voltage Figure 9. Split Supply Output Voltage Swing versus Supply Voltage 5

6 MC347,2,4,A MC337,2,4,A, NCV3374A 6

7 MC347,2,4,A MC337,2,4,A, NCV3374A THD, TOTAL HARMONIC DISTORTION (%).4 A V =.3 V CC = 5 V V EE = 5 V.2 = 2. V pp R L = 2. k A V =. A V = A V =.. k k k f, FREQUENCY (Hz) Figure 6. Total Harmonic Distortion versus Frequency THD, TOTAL HARMONIC DISTORTION (%) A V = A V = A V = A V = , OUTPUT VOLTAGE SWING (V pp ) V CC = 5 V V EE = 5 V R L = 2. k Figure 7. Total Harmonic Distortion versus Output Voltage Swing AМ, VOL OPEN LOOP VOLTAGE GAIN (db) V CC = 5 V V EE = 5 V = V to V R L = k f Hz T A, AMBIENT TEMPERATURE ( C) Figure. Open Loop Voltage Gain versus Temperature AМ, VOL OPEN LOOP VOLTAGE GAIN (db) Gain Phase 45 6 Phase Margin 9 4 = 6 V CC = 5 V V EE = 5 V 35 2 = V R L = 2. k.. k k k. M M M f, FREQUENCY (Hz) Figure 9. Open Loop Voltage Gain and Phase versus Frequency φ, EXCESS PHASE (DEGREES) AМ, VOL OPEN LOOP VOLTAGE GAIN (db) 2 Phase Margin = 6 Gain 2 Margin = 2 db 4. Phase R L = 2. k 6 2. Phase R L = 2. k, C L = 3 pf Gain R L = 2. k 4. Gain R L = 2. k, C L = 3 pf V CC = 5 V 4 3 V EE = 5 V 2 = VМММММ f, FREQUENCY (MHz) Figure 2. Open Loop Voltage Gain and Phase versus Frequency φ, EXCESS PHASE (DEGREES) GBW, GAIN BANDWIDTH PRODUCT (NORMALIED) T A, AMBIENT TEMPERATURE ( C) V CC = 5 V V EE = 5 V R L = 2. k Figure 2. Normalized Gain Bandwidth Product versus Temperature 7

8 MC347,2,4,A MC337,2,4,A, NCV3374A 7 PERCENT OVERSHOOT V CC = 5 V V EE = 5 V R L = 2. k = V to V φ m, PHASE MARGIN (DEGREES) V CC = 5 V V EE = 5 V A V =. R L = 2. k to = V to V. k k C L, LOAD CAPACITANCE (pf) Figure 22. Percent Overshoot versus Load Capacitance. k k C L, LOAD CAPACITANCE (pf) Figure 23. Phase Margin versus Load Capacitance 4 AМ, m GAIN MARGIN (db) V CC = 5 V V EE = 5 V A V =. R L = 2. k to = V to V φ m, PHASE MARGIN (DEGREES) C L = pf C L = pf C L =, pf C L =, pf V CC = 5 V V EE = 5 V A V =. R L = 2. k to = V to V. k k C L, LOAD CAPACITANCE (pf) Figure 24. Gain Margin versus Load Capacitance T A, AMBIENT TEMPERATURE ( C) Figure 25. Phase Margin versus Temperature AМ, m GAIN MARGIN (db) V CC = 5 V V EE = 5 V A V =. R L = 2. k to = V to V C L =, pf C L = pf C L = pf C L =, pf T A, AMBIENT TEMPERATURE ( C) Figure 26. Gain Margin versus Temperature AМ, m GAIN MARGIN (db) R R 2 Gain 4. 3 V CC = 5 V V EE = 5 V 2. R T = R R 2 2 Phase A V = = V.. k k k R T, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 27. Phase Margin and Gain Margin versus Differential Source Resistance φ m, PHASE MARGIN (DEGREES)

9 MC347,2,4,A MC337,2,4,A, NCV3374A SR, SLEW RATE (NORMALIZED) V CC = 5 V V EE = 5 V A V =. R L = 2. k C L = 5 pf T A, AMBIENT TEMPERATURE ( C) Figure 2. Normalized Slew Rate versus Temperature VМ, O OUTPUT VOLTAGE SWING FROM V (V) Δ mv mv. mv. mv. mv. mv t s, SETTLING TIME ( s) Figure 29. Output Settling Time V CC = 5 V V EE = 5 V A V =. Compensated Uncompensated 5 mv/div V CC = 5 V V EE = 5 V A V =. R L = 2. k C L = 3 pf 5. V/DIV V CC = 5 V V EE = 5 V A V =. R L = 2. k C L = 3 pf 2. s/div Figure 3. Small Signal Transient Response. s/div Figure 3. Large Signal Transient Response CMR, COMMON MODE REJECTION (db) T A = 55 C V CM A DM V CM CMR = 2 Log x A DM... k k k. M M f, FREQUENCY (Hz) V CC = 5 V V EE = 5 V V CM = V V CM = ±.5 V Figure 32. Common Mode Rejection versus Frequency PSR, POWER SUPPLY REJECTION (db) 6 4 A DM PSR = 2 Log V CC V EE /A DM V CC 2 /A DM PSR = 2 Log PSR V EE ( V EE =.5 V)... k k k. M M f, FREQUENCY (Hz) V CC = 5 V V EE = 5 V ( V CC =.5 V) Figure 33. Power Supply Rejection versus Frequency PSR 9

10 MC347,2,4,A MC337,2,4,A, NCV3374A IМ CC, SUPPLY CURRENT (ma) T A = 55 C V CC, V EE, SUPPLY VOLTAGE (V) Figure 34. Supply Current versus Supply Voltage PSR, POWER SUPPLY REJECTION (db) PSR ( V EE =.5 V) PSR = 2 Log PSR = 2 Log PSR ( V CC =.5 V) /A DM V CC /A DM V EE A DM T A, AMBIENT TEMPERATURE ( C) Figure 35. Power Supply Rejection versus Temperature V CC = 5 V V EE = 5 V V CC V EE CHANNEL SEPARATION (db) V CC = 5 V V EE = 5 V f, FREQUENCY (khz) Figure 36. Channel Separation versus Frequency nv Hz ) e, n INPUT NOICE VOLTAGE ( Voltage Current. k k k f, FREQUENCY (khz) V CC = 5 V V EE = 5 V V CM = Figure 37. Input Noise versus Frequency iм, INPUT NOISE CURRENT (pa Hz ) n APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the MC347 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the V EE potential, single supply operation is feasible to as low as 3. V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to ±44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between V EE and V CC supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the V CC voltage by approximately 3. V and decrease below the V EE voltage by.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to approximately 5. ma of current from V EE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pf) than the typical JFET input gate capacitance (5. pf), better frequency response for a given input source resistance can be achieved using the MC347 series of amplifiers. This performance feature becomes evident, for example, in fast settling DtoA current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher

11 MC347,2,4,A MC337,2,4,A, NCV3374A values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2. k of feedback resistance, the MC347 series can settle to within /2 LSB of bits in. s, and within /2 LSB of 2bits in 2.2 s for a V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is ±3 V/ s. In the classic noninverting unity gain configuration, the output positive slew rate is V/ s, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3. mv prime and 5. mv downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A k load resistance can swing within. V of the positive rail (V CC ), and within.3 V of the negative rail (V EE ), providing a 2.7 V pp swing from ±5 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q 7, and V BE of the NPN pull up transistor Q 7, and the voltage drop associated with the short circuit resistance, R 7. The negative swing is limited by the saturation voltage of the pulldown transistor Q 6, the voltage drop I L R 6, and the voltage drop associated with resistance R 7, where I L is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of V EE. For large valued sink currents (>5. ma), diode D3 clamps the voltage across R 6, thus limiting the negative swing to the saturation voltage of Q 6, plus the forward diode drop of D3 ( V EE. V). Thus for a given supply voltage, unprecedented peaktopeak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to V CC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to V CC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitterfollower transistor has been eliminated, the MC347 series offers a 2 ma minimum current sink capability, typically to an output voltage of (V EE. V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier s high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (3 MHz) allows capacitive drive capability from pf to, pf without oscillation in the unity closed loop gain configuration. The 6 phase margin and 2 db gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC347 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5. V, these amplifiers are functional to C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted inputoutput coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous pick up at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for ±5 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.

12 MC347,2,4,A MC337,2,4,A, NCV3374A (Typical Single Supply Applications V CC = 5. V) V CC 5. M 3.7 V pp 2 k C. M k in C O VO 6 k MC mv pp C in k k k R L k V. k A V = in 37 mv pp BW (3. db) = 45 khz A V = BW (3. db) = 45 khz V CC C O 3.7 V pp k R L Figure 3. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier Figure 4. DC Coupled Inverting Amplifier Maximum Output Swing Figure 4. Unity Gain Buffer TTL Driver Figure 42. Active HighQ Notch Filter Figure 43. Active Bandpass Filter 2

13 MC347,2,4,A MC337,2,4,A, NCV3374A C F 2. V Bit Switches k 5. k 5. k k k 5. k R F MC347 V CC MC k R L. V 4. V 3 V/ s t.2 s Delay 25 V/ s (R) Ladder Network Settling Time. s (Bits, /2 LSB). Delay. s t Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator V CC ON" < V ref V CC V CC V ref MC347 ON" > V ref MC347 R L MC347 R L (A) PNP (B) NPN Figure 46. LED Driver Figure 47. Transistor Driver I Load Ground Current Sense Resistor R S MC347 R = I Load R S R I Cell R F MC347 For >.V BW ( 3. db) = GBW R V Cell = V = I Cell R F >. V Figure 4. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier 3

14 I MC347,2,4,A MC337,2,4,A, NCV3374A Hysteresis V ref L = R R R MC347 (L V ref )V ref H L L H V ref MC347 I out H = R R (H V ref )V ref V H = R RR (H L ) I out = ±V IO R R Figure 5. Low Input Voltage Comparator with Hysteresis Figure 5. High Compliance Voltage to Sink Current Converter R R4 V V2 = R = R4 R3 /2 MC3472 (Critical to CMRR) R4 R3 For (V2 V), V > V2V R4 R3 R3 /2 MC3472 R R = R V ref RF R R MC347 R R F = V ref R < < R R F 2R 2 R F > > R (. V) Figure 52. High Input Impedance Differential Amplifier Figure 53. Bridge Current Amplifier f OSC.5 RC V B I SC V P t MC347 = (pk) t Base Charge Removal I out R L V P, pf C R /2 MC3472 /2 MC3472 ±I B V k 47 k k V P Pulse Width Control Group V P Figure 54. Low Voltage Peak Detector t OSC Comparator High Current Output Figure 55. High Frequency Pulse Width Modulation 4

15 MC347,2,4,A MC337,2,4,A, NCV3374A GENERAL ADDITIONAL APPLICATIONS INFORMATION V S = ±5. V R R C.44 Figure 56. Second Order LowPass Active Filter 5.6 k MC347 C2.2 f o =. khz H o = Choose: f o, H o, C2 Then: C = 2C2 (H o ) 2 = R3 = R = 4 f o C2 H o H o C2.5 C. C.. k R 46. k Choose: f o, H o, C Then: R = Figure 57. Second Order HighPass Active Filter MC347 = C2 = f o = Hz H o = 2 H o.5 f o C f o C (/H o 2) C H o C F * R F = V Step 2. k MC347 R MC347 R L I High Speed DAC Uncompensated Compensated t s =. s to /2 LSB (Bits) t s = 2.2 s to /2 LSB (2Bits) = R BW (3. db) = GBW R R *Optional Compensation SR = 3 V/ s SR = 3 V/ s Figure 5. Fast Settling Inverter Figure 59. Basic Inverting Amplifier MC347 R L MC347 R = R R BW (3. db) = GBW R BW p = 2 khz = 2 V pp SR = V/ s Figure 6. Basic Noninverting Amplifier Figure 6. Unity Gain Buffer (A V =.) 5

16 MC347,2,4,A MC337,2,4,A, NCV3374A MC3474 R R R R E R MC3474 MC3474 R R Example: Let: R = R E = 2 k Then: A V = 3. BW =.5 MHz A V = 2 R R E Figure 62. High Impedance Differential Amplifier k MC3474 R L MC pf R L.93.7 k 5. k k k MC3474 R L Figure 63. Dual Voltage Doubler 6

17 MC347,2,4,A MC337,2,4,A, NCV3374A ORDERING INFORMATION Op Amp Function Single Dual MC347P MC347PG MC347AP MC347APG MC347D MC347DG MC347D MC347DG MC347AD MC347ADG MC347AD MC347ADG MC337D MC337DG MC337D MC337DG MC337AD MC337ADG MC337AD MC337ADG MC337AP MC337APG MC337P MC337PG MC3472P MC3472PG MC3472AP MC3472APG MC3472D MC3472DG MC3472AD MC3472ADG MC3472D MC3472DG MC3472AD MC3472ADG Device Operating Temperature Range T A = to 7 C T A = 4 to 5 C T A = to 7 C Package PDIP PDIP (PbFree) PDIP PDIP (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) PDIP PDIP (PbFree) PDIP PDIP (PbFree) PDIP PDIP (PbFree) PDIP PDIP (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) Shipping 5 Units / Rail 5 Units / Rail 9 Units / Rail 25 / Tape & Reel 9 Units / Rail 25 / Tape & Reel 9 Units / Rail 25 / Tape & Reel 9 Units / Rail 25 / Tape & Reel 5 Units / Rail 9 Units / Rail 25 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. 7

18 MC347,2,4,A MC337,2,4,A, NCV3374A ORDERING INFORMATION (continued) Op Amp Function Device MC3372P Dual Quad MC3372PG MC3372AP MC3372APG MC3372D MC3372DG MC3372AD MC3372ADG MC3372D MC3372DG MC3372AD MC3372ADG MC3472VD MC3472VDG MC3472VD MC3472VDG MC3472VP MC3472VPG MC3474P MC3474PG MC3474AP MC3474APG MC3474D MC3474DG MC3474AD MC3474ADG MC3474AD MC3474ADG MC3474D Operating Temperature Range T A = 4 to 5 C T A = 4 to 25 C T A = to 7 C Package PDIP PDIP (PbFree) PDIP PDIP (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) PDIP PDIP (PbFree) PDIP4 PDIP4 (PbFree) PDIP4 PDIP4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 Shipping 5 Units / Rail 9 Units / Rail 25 / Tape & Reel 9 Units / Rail 25 / Tape & Reel 5 Units / Rail 25 Units / Rail 55 Units / Rail 25 Units / Tape & Reel MC3474DG SOIC4 (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.

19 MC347,2,4,A MC337,2,4,A, NCV3374A ORDERING INFORMATION (continued) Op Amp Function Device MC3374P Quad MC3374PG MC3374AP MC3374APG MC3374D MC3374DG MC3374AD MC3374ADG MC3374D MC3374DG MC3374AD MC3374ADG MC3374DTB MC3374DTBG MC3374DTB MC3374DTBG MC3374ADTB MC3374ADTBG MC3374ADTB MC3374ADTBG MC3474VD MC3474VDG MC3474VD MC3474VDG MC3474VP MC3474VPG Operating Temperature Range T A = 4 to 5 C T A = 4 to 25 C Package PDIP4 PDIP4 (PbFree) PDIP4 PDIP4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) TSSOP4* TSSOP4* TSSOP4* TSSOP4* TSSOP4* TSSOP4* TSSOP4* TSSOP4* SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) PDIP4 PDIP4 (PbFree) Shipping 25 Units / Rail 55 Units / Rail 25 / Tape & Reel 96 Units / Rail 25 / Tape & Reel 96 Units / Rail 25 / Tape & Reel 55 Units / Rail 25 / Tape & Reel 25 Units / Rail NCV3374ADTBG** TSSOP4* 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. *This package is inherently PbFree. **NCV prefix for automotive and other applications requiring site and control changes. 9

20 MC347,2,4,A MC337,2,4,A, NCV3374A MARKING DIAGRAMS PDIP P SUFFIX CASE 626 MC3x7P AWL YYWWG MC3x7AP AWL YYWWG MC3x72P AWL YYWWG MC3x72AP AWL YYWWG MC3472VP AWL YYWWG SOIC D SUFFIX CASE 75 3x7 ALYW 3x7 ALYWA 3x72 ALYW 3x72 ALYWA 3472 ALYWV 4 MC3x74P AWLYYWWG 4 PDIP4 P SUFFIX CASE 646 MC3x74AP AWLYYWWG 4 MC3474VP AWLYYWWG SOIC4 D SUFFIX CASE 75A TSSOP4 DTB SUFFIX CASE 94G MC3x74DG AWLYWW MC3x74ADG AWLYWW MC3474VDG AWLYWW MC33 74 ALYW MC33 74A ALYW NCV3 74A ALYW x = 3 or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package (Note: Microdot may be in either location) 2

21 MC347,2,4,A MC337,2,4,A, NCV3374A PACKAGE DIMENSIONS PDIP P SUFFIX CASE 6265 ISSUE L 5 B NOTES:. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. NOTE 2 T SEATING PLANE H 4 F A C N D K G.3 (.5) M T A M B M L J M MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 2.54 BSC. BSC H J K L 7.62 BSC.3 BSC M N

22 MC347,2,4,A MC337,2,4,A, NCV3374A PACKAGE DIMENSIONS SOIC NB CASE 757 ISSUE AH Y B X A 5 4 S.25 (.) M Y M K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 756 ARE OBSOLETE. NEW STANDARD IS 757. Z H G D C.25 (.) M Z Y S X S SEATING PLANE. (.4) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC.5 BSC H J K M N S SOLDERING FOOTPRINT* SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 22

23 MC347,2,4,A MC337,2,4,A, NCV3374A PACKAGE DIMENSIONS PDIP4 CASE 6466 ISSUE P 4 B 7 A DIM MIN MAX MIN MAX MILLIMETERS INCHES A 23

24 MC347,2,4,A MC337,2,4,A, NCV3374A SOIC4 CASE 75A3 ISSUE H T SEATING PLANE G A 4 D 4 PL 7 B K P 7 PL C.25 (.) M T B S A S.25 (.) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.27 BSC.5 BSC J K M 7 7 P R SOLDERING FOOTPRINT* 4X.5 7X 7.4 4X PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 24

25 MC347,2,4,A MC337,2,4,A, NCV3374A PACKAGE DIMENSIONS TSSOP4 CASE 94G ISSUE B.5 (.6) T.5 (.6) T L. (.4) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF. (.4) M T U S V S N.25 (.) M B U 7 A V G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTION NN DETAIL E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED.5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.47 D F G.65 BSC.26 BSC H J J W K K L 6.4 BSC.252 BSC M SOLDERING FOOTPRINT* PITCH 4X.36 4X.26 DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 25

26 MC347,2,4,A MC337,2,4,A, NCV3374A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC347/D