CS5101. Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters

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Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters The CS50 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output

1 Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters The CS50 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC/DC or DC/DC converters. Leading edge pulse width modulation is used with the CS50. The CS50 is designed to operate over an 8. to 45 V supply voltage (C ) range and up to a 75 V drive voltage ( ). The CS50 features include a totem pole output with.5 A peak output current capability, externally programmable overcurrent protection, an on chip 2.0% precision reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 4 lead plastic DIP or a 6 lead wide body SOIC package. 4 6 PDIP4 N SUFFIX CASE 646 SO6WB DW SUFFIX CASE 75G Features.5 A Peak Output (Grounded Totem Pole) 8. to 75 ate Drive Voltage 8. to 45 V Supply Voltage 300 ns Propagation Delay.0% Error Amplifier Reference Voltage Lossless Turn On and Turn Off Sleep Mode: < 00 A Overcurrent Protection with Dedicated Differential Amp Synchronization to External Clock External Power Switch Drain Voltage Monitor PbFree Packages are Available* MARKING DIAGRAMS AND PIN ASSIGNMENTS SYNC VCC VREF LGND CS50EN4 AWLYYWWG PDIP4 4 IS IS IS 6 SYNC C V REF DGND AGND CS50 AWLYYWWG IS IS IS SO6WB A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2006 October, 2006 Rev. 6 Publication Order Number: CS50/D

2 TR V SY C R4 3 6 Q 4 C R5 L 5 R8 R0 R R3 V OUT C6 R5 R6 R9 R2 R4 GND C R C5 R R2 C R3 R7 V SYNC R3 C R2 C V REF CS50 SSPR LGND C4 IS C C2 R4 IS IS 2 C3 C R Figure. Application Diagram MAXIMUM RATINGS Rating Value Unit Power Supply Voltage, C 0.3 to 45 V V SYNC and Output Supply Voltages,,, V SYNC, 0.3 to 75 V V IS, V IS (C 4., up to 24 V) 0.3 to 24 V V REF,, OMP, V, V IS 0.3 to Operating Junction Temperature, T J 40 to 50 C Operating Temperature Range 40 to 85 C Storage Temperature Range 65 to 50 C Output Energy (Capacitive Load Per Cycle) 5.0 J ESD Human Body 2.0 kv Lead Temperature Soldering Wave Solder (through hole styles only) (Note ) Reflow (SMD styles only) (Note 2) 260 peak 230 peak Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. 0 second maximum second maximum above 83 C C C 2

3 ELECTRICAL CHARACTERISTICS (40 C T A 85 C, 40 C T J 50 C, < C < 45 V, 8. < < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Error Amplifier Input Voltage Initial Accuracy = OMP, C = 5 V, T = 25 C, Note V Input Voltage = OMP, includes line and temp V Input Bias Current =, I flows out of pin 500 na Open Loop Gain.5 V < OMP < db Unity Gain Bandwidth.5 V < OMP < 3., Note MHz Output Sink Current OMP = 2., = 2.2 V ma Output Source Current OMP = 2., =.8 V ma OMP High =.8 V V OMP Low = 2.2 V V PSRR < C < 45 V, = OMP, Note db Voltage Reference Output Voltage Initial Accuracy C = 5 V, T = 25 C, Note V Output Voltage 0 A < I REF < 8.0 ma V Line Regulation < C < 45 V, I REF = 0 A 0 60 mv Load Regulation 0 A < I REF < 8.0 ma mv Current Limit V REF = 4.8 V 0 50 ma V REF OK FAULT V V SYNC =, V REF = V LOAD V REF OK V V SYNC =, V REF = V LOAD V REF OK Hysteresis mv Current Sense Amplifier IS High V IS =, IS = IS V IS Low V IS =, IS = IS V Source Current IS =, IS = ma Sink Current IS =, IS = 0 20 ma Open Loop Gain.5 V OMP 4.5 V, R L = 4.0 k db CMRR Note db PSRR < C < 45 V, Note db Unity Gain Bandwidth.5 V OMP 4.5 V, R L = 4.0 k, Note MHz Input Offset Voltage V IS = 2.5 V, V IS = V IS mv Input Bias Currents V IS = V IS =, I IS flows out of pins na Input Offset Current (IS, IS) na Input Signal Voltage Range Note C 4. /SYNC Generator Source Current Initial Accuracy V SYNC =, V = 2.5 V, T = 25 C, Note ma Source Current V SYNC =, V = 2.5 V ma Sink Current V SYNC =, V = 2.5 V ma Peak Voltage V SYNC = V Valley Voltage V SYNC = V Dynamic Range V DR = V PK V VY V Sleep Threshold Voltage V REF < SYNC Threshold V V > 2.5 V V SYNC Input Bias Current V SYNC =, I SYNC flows out of pin.0 20 A 3. Guaranteed by design. Not 00% tested in production. 3

4 ELECTRICAL CHARACTERISTICS (40 C T A 85 C, 40 C T J 50 C, < C < 45 V, 8. < < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage, High V SYNC =, I = 200 ma, V, Low V SYNC =, I = 200 ma V Rise Time Switch V SYNC High, C G =.0 nf, C = 5 V, measure 2. to 8. Fall Time Switch V SYNC Low, C G =.0 nf, C = 5 V, measure 8. to ns ns Resistance to GND Remove supplies, = k Resistance to GND Remove supplies, = General I CC, Operating V SYNC = 2 8 ma I CC in UVL C = A I CC in Sleep Mode High V =, C = 45 V A I CC in Sleep Mode Low V =, C = A I C, Operating High V SYNC =, = V IS =, = 75 V ma I C, Operating Low V SYNC =, = V IS =, = ma UVLO Start Voltage V UVLO Stop Voltage V UVLO Hysteresis V Leading Edge, t DELAY V SYNC = 2.5 V to = ns Trailing Edge, t DELAY V SYNC = 2.5 V to = ns PACKAGE PIN DESCRIPTION PACKAGE LEAD # PDIP4 SO6WB LEAD SYMBOL SYNC Synchronization input. FUNCTION 2 2 C Logic supply ( to 45 V). 3 3 V REF voltage reference. 4 LGND Logic level ground (analog and digital ground tied). 5 6 Error amplifier inverting input. 6 7 Error amplifier output and compensation. 7 8 programmable with the external capacitor. 8 9 IS Current sense amplifier noninverting input. 9 0 IS Current sense amplifier inverting input. 0 IS Current sense amplifier compensation and output. 2, 3 Power ground. 2 4 External power switch gate drive. 3 5 Output power stage supply voltage (8. to 75 V). 4 6 External FET DRAIN voltage monitor. 5 AGND Analog ground. 4 DGND Digital ground. 4

5 ORDERING INFORMATION CS50EN4 CS50EN4G Device Package Shipping PDIP4 PDIP4 (PbFree) 25 Units / Rail CS50EDW6 CS50EDW6G SOIC6WB SOIC6WB (PbFree) 47 Units / Rail CS50EDWR6 CS50EDWR6G SOIC6WB SOIC6WB (PbFree) 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. CIRCUIT DESCRIPTION C V REF LGND C REF OK UVL 8./7. SLEEP 0.7 V Q Q 2 EA V 0 k 0 k 2.4 V Q 4 I = 200 A.5 V G 24.6 k BUF REF_OK PWM Q LATCH Q S R 4.5 V/4.4 V C IS C OK 0.7 V Q 3 C IS IS IS SYNC SYNC 2.5 V G 2 Figure 2. Block Diagram 5

6 Theory of Operation The CS50 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turnon. It can be used with both single ended and dual ended topologies. The voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor C R. When the ramp voltage V R, exceeds the control voltage, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q turns on, and the external power switch, usually an NFET, turns on. SYNC Function The SYNC circuit is activated at time t (Figure 3) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor C R is allowed to charge through the internal current source I (200 A). At time t 2, the ramp voltage intersects with the control voltage and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH. 2 V SY V SY 3 4 V SY V SY V OUT 5 V SY 6 V OUT V SY V S V S V L The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5 V) and the voltage is less than the threshold voltage of the comparator (.65 V). On the negative going transition of the secondary side pulse V SY, gate G 2 output goes high, resetting the latch at time t 3. Capacitor C R is discharged through transistor Q 4. C R s output goes low disabling the output stage, and the external power switch (an NFET) is turned off. Function The value of the ramp capacitor C R is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse V SY. If the pin is pulled externally to 0.3 V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 00 A, and the IC is in SLEEP mode. FAULT Function The voltage at the C pin is monitored by the undervoltage lockout comparator with hysteresis. When C falls below the UVL threshold, the reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500 A. The C supply voltage is further monitored by the C _OK comparator. When C is reduced below V REF 0.7 V, a fault signal is sent to gate G. This fault signal, which determines if C is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turnoff. This feature protects the FET from overvoltage stress. This is accomplished through gate G by driving transistor Q 4 on. An additional fault signal is derived from the REF_OK comparator. V REF is monitored so to disable the output through gate G when the V REF voltage falls below the OK threshold. As in the C _OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when V REF voltage is within the specification limits of REF_OK. DRAIN Function The drain pin, monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when or C is below the minimum specified voltage. Ground Level (Gate doesn t go below GND) t t 2 t 3 t 4 t Figure 3. Waveforms for CS50. The Number to the Left of Each Curve Refers to a Node On the Application Diagram on Page 2. 6

7 C.0 F S SW SPST R 00 k V V 00 khz to Square Wave V SYNC R2 00 k C2 0. F R6 0 k R3 5.0 k C4 0. F R7 0 k C V REF LGND C5 680 pf CS50 IS IS IS R5 0 k R4 2.2 k C3.0 nf Figure 4. CS50 Bench Test on DIP4 Package 7

8 PACKAGE DIMENSIONS PDIP4 CASE ISSUE P B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M 8

9 PACKAGE DIMENSIONS SOIC6WB CASE 75G03 ISSUE C 8X H 0.25 M B M D A 6 9 E 8 6X B B 0.25 M T A S B S A h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L q 0 7 4X e A T SEATING PLANE C L PACKAGE THERMAL DATA Parameter PDIP4 SOIC6WB Unit R JC Typical C/W R JA Typical C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative CS50/D

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