IRGB6B60KD IRGS6B60KD IRGSL6B60KD

Transcription

1 PD - 93E INSULATED GATE BIPOLAR TRANSISTOR WITH ULTRAFAST SOFT RECOVERY DIODE Features Low VCE (on) Non Punch Through IGBT Technology. Low Diode VF. µs Short Circuit Capability. Square RBSOA. Ultrasoft Diode Reverse Recovery Characteristics. Positive VCE (on) Temperature Coefficient. Benefits Benchmark Efficiency for Motor Control. Rugged Transient Performance. Low EMI. Excellent Current Sharing in Parallel Operation. G C E n-channel IRGBBKD IRGSBKD IRGSLBKD V CES = V I C = 7.A, T C = C t sc > µs, T J =5 C V CE(on) typ. =.V Absolute Maximum Ratings Parameter Max. Units V CES Collector-to-Emitter Voltage V I T C = 5 C Continuous Collector Current 3 I T C = C Continuous Collector Current 7. I CM Pulsed Collector Current I LM Clamped Inductive Load Current A I T C = 5 C Diode Continuous Forward Current 3 I T C = C Diode Continuous Forward Current 7. I FM Diode Maximum Forward Current V GE Gate-to-Emitter Voltage ± V P T C = 5 C Maximum Power Dissipation 9 W P T C = C Maximum Power Dissipation 3 T J Operating Junction and -55 to +5 T STG Storage Temperature Range C Soldering Temperature, for sec. 3 (.3 in. (.mm) from case) Thermal Resistance TO-AB IRGBBKD D Pak IRGSBKD TO- IRGSLBKD Parameter Min. Typ. Max. Units R θjc Junction-to-Case - IGBT. R θjc Junction-to-Case - Diode. R θcs Case-to-Sink, flat, greased surface.5 C/W R θja Junction-to-Ambient, typical socket mount R θja Junction-to-Ambient (PCB Mount, steady state) Wt Weight. g //

2 IRG/B/S/SLBKD Electrical T J = 5 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions Ref.Fig. V (BR)CES Collector-to-Emitter Breakdown Voltage V V GE = V, I C = 5µA V (BR)CES/ T J Temperature Coeff. of Breakdown Voltage.3 V/ C V GE = V, I C =.ma, (5 C-5 C) V CE(on) Collector-to-Emitter Saturation Voltage.5.. V I C = 5.A, V GE = 5V 5,,7..5 I C = 5.A,V GE = 5V, T J = 5 C 9,, V GE(th) Gate Threshold Voltage V V CE = V GE, I C = 5µA 9,, V GE(th) / T J Temperature Coeff. of Threshold Voltage - mv/ C V CE = V GE, I C =.ma, (5 C-5 C) g fe Forward Transconductance 3. S V CE = 5V, I C = 5.A, PW=µs I CES Zero Gate Voltage Collector Current. 5 µa V GE = V, V CE = V 5 V GE = V, V CE = V, T J = 5 C V FM Diode Forward Voltage Drop.5.5 I C = 5.A.. V I C = 5.A T J = 5 C I GES Gate-to-Emitter Leakage Current ± na V GE = ±V Switching T J = 5 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions Qg Total Gate Charge (turn-on). I C = 5.A Qge Gate - Emitter Charge (turn-on).9 nc V CC = V Qgc Gate - Collector Charge (turn-on) 9. V GE = 5V E on Turn-On Switching Loss µj I C = 5.A, V CC = V E off Turn-Off Switching Loss 35 5 V GE = 5V,R G = Ω, L =.mh E tot Total Switching Loss 5 55 Ls = 5nH T J = 5 C ƒ t d(on) Turn-On Delay Time 5 3 I C = 5.A, V CC = V t r Rise Time 7 V GE = 5V, R G = Ω L =.mh t d(off) Turn-Off Delay Time 5 3 ns Ls = 5nH, T J = 5 C t f Fall Time 3. E on Turn-On Switching Loss 5 I C = 5.A, V CC = V E off Turn-Off Switching Loss 9 3 µj V GE = 5V,R G = Ω, L =.mh E tot Total Switching Loss 3 5 Ls = 5nH T J = 5 C ƒ t d(on) Turn-On Delay Time 37 I C = 5.A, V CC = V t r Rise Time 7 V GE = 5V, R G = Ω L =.mh t d(off) Turn-Off Delay Time 55 ns Ls = 5nH, T J = 5 C t f Fall Time 7 C ies Input Capacitance 9 V GE = V C oes Output Capacitance 3 pf V CC = 3V C res Reverse Transfer Capacitance f =.MHz RBSOA Reverse Bias Safe Operting Area FULL SQUARE T J = 5 C, I C = A, Vp =V V CC = 5V, V GE = +5V to V, SCSOA Short Circuit Safe Operting Area µs T J = 5 C, Vp =V, R G = Ω V CC = 3V, V GE = +5V to V Erec Reverse Recovery energy of the diode 9 75 µj T J = 5 C t rr Diode Reverse Recovery time 7 ns V CC = V, I F = 5.A, L =.mh I rr Diode Peak Reverse Recovery Current A V GE = 5V,R G = Ω, Ls = 5nH Note: to are on page 5 Ref.Fig. CT CT CT CT 3,5 WFWF, CT WF WF R G = Ω CT CT3 WF 7,,9, CT,WF3

3 I C (A) I C A) I C (A) P tot (W) IRG/B/S/SLBKD T C ( C) T C ( C) Fig. - Maximum DC Collector Current vs. Case Temperature Fig. - Power Dissipation vs. Case Temperature µs µs DC ms. V CE (V) V CE (V) Fig. 3 - Forward SOA T C = 5 C; T J 5 C Fig. - Reverse Bias SOA T J = 5 C; V GE =5V 3

4 I CE (A) I F (A) I CE (A) I CE (A) IRG/B/S/SLBKD V GE = V VGE = 5V VGE = V VGE = V VGE =.V V GE = V VGE = 5V VGE = V VGE = V VGE =.V V CE (V) V CE (V) Fig. 5 - Typ. IGBT Output Characteristics T J = - C; tp = µs Fig. - Typ. IGBT Output Characteristics T J = 5 C; tp = µs 3 V GE = V VGE = 5V VGE = V VGE = V VGE =.V 5 - C 5 C 5 C V CE (V) V F (V) Fig. 7 - Typ. IGBT Output Characteristics Fig. - Typ. Diode Forward Characteristics T J = 5 C; tp = µs tp = µs

5 V CE (V) I CE (A) V CE (V) V CE (V) IRG/B/S/SLBKD I CE = 3.A I CE = 5.A I CE = A I CE = 3.A I CE = 5.A I CE = A V GE (V) V GE (V) Fig. 9 - Typical V CE vs. V GE T J = - C Fig. - Typical V CE vs. V GE T J = 5 C I CE = 3.A I CE = 5.A I CE = A T J = 5 C T J = 5 C T J = 5 C 5 T J = 5 C 5 5 V GE (V) 5 5 V GE (V) Fig. - Typical V CE vs. V GE Fig. - Typ. Transfer Characteristics T J = 5 C V CE = 5V; tp = µs 5

6 Energy (µj) Swiching Time (ns) Swiching Time (ns) IRG/B/S/SLBKD 7 td OFF Energy (µj) 5 3 E ON E OFF t F td ON t R 5 5 I C (A) 5 5 I C (A) Fig. 3 - Typ. Energy Loss vs. I C T J = 5 C; L=.mH; V CE = V R G = Ω; V GE = 5V Fig. - Typ. Switching Time vs. I C T J = 5 C; L=.mH; V CE = V R G = Ω; V GE = 5V 5 E OFF td OFF 5 E ON td ON t R t F R G (Ω) R G (Ω) Fig. 5 - Typ. Energy Loss vs. R G T J = 5 C; L=.mH; V CE = V I CE = 5.A; V GE = 5V Fig. - Typ. Switching Time vs. R G T J = 5 C; L=.mH; V CE = V I CE = 5.A; V GE = 5V

7 I RR (A) Q RR (µc) I RR (A) I RR (A) IRG/B/S/SLBKD 5 R G = Ω R G = 7 Ω 5 R G = Ω R G = 5 Ω I F (A) R G (Ω) Fig. 7 - Typical Diode I RR vs. I F T J = 5 C Fig. - Typical Diode I RR vs. R G T J = 5 C; I F = 5.A Ω 7Ω A Ω 5Ω 5.A 3.A di F /dt (A/µs) di F /dt (A/µs) Fig. 9- Typical Diode I RR vs. di F /dt V CC = V; V GE = 5V; I CE = 5.A; T J = 5 C Fig. - Typical Diode Q RR V CC = V; V GE = 5V;T J = 5 C 7

8 Capacitance (pf) V GE (V) Energy (µj) IRG/B/S/SLBKD 3 Ω 5 7Ω 5 Ω 5 Ω I F (A) Fig. - Typical Diode E RR vs. I F T J = 5 C Cies Coes 3V V Cres V CE (V) 5 5 Q G, Total Gate Charge (nc) Fig. - Typ. Capacitance vs. V CE Fig. 3 - Typical Gate Charge vs. V GE V GE = V; f = MHz I CE = 5.A; L = µh

9 Thermal Response ( Z thjc ) IRG/B/S/SLBKD D = SINGLE PULSE ( THERMAL RESPONSE ) R R R 3 R R R 3 τ J τ J τ τ τ τ 3 τ τ 3 Ci= τi/ri Ci= i/ri τ C τ Ri ( C/W) τi (sec) Notes:. Duty Factor D = t/t. Peak Tj = P dm x Zthjc + Tc. E- E-5 E- E-3 E- E- t, Rectangular Pulse Duration (sec) Fig. Maximum Transient Thermal Impedance, Junction-to-Case (IGBT) Thermal Response ( Z thjc ) D = R R R 3 R R R 3 τ J τ J τ τ τ τ 3 τ τ 3 Ci= τi/ri Ci= i/ri Ri ( C/W) τi (sec) SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t. Peak Tj = P dm x Zthjc + Tc τ C τ. E- E-5 E- E-3 E- E- E+ t, Rectangular Pulse Duration (sec) Fig 5. Maximum Transient Thermal Impedance, Junction-to-Case (DIODE) 9

10 IRG/B/S/SLBKD L K DUT L VCC V + - Rg DUT V Fig.C.T. - Gate Charge Circuit (turn-off) Fig.C.T. - RBSOA Circuit Driver diode clamp / DUT L DC DUT 3V - 5V Rg DUT / DRIVER VCC Fig.C.T.3 - S.C.SOA Circuit Fig.C.T. - Switching Loss Circuit R = VCC ICM Rg DUT VCC Fig.C.T.5 - Resistive Load Circuit

11 IRG/B/S/SLBKD VCE (V) tf 9% I CE 5% V CE 5% I CE Eoff Loss time(µs) Fig. WF- Typ. Turn-off Loss T J = 5 C using Fig. CT ICE (A) VCE (V) 3 - tr Eon Loss TEST CURRENT 9% test current % test current 5% V CE time (µs) 5 Fig. WF- Typ. Turn-on Loss T J = 5 C using Fig. CT. 5-5 ICE (A) t RR Q RR V CE -5 3 I CE 3 VF (V) Peak I RR % Peak IRR IF (A) VCE (V) ICE (A) time (µs) Fig. WF3- Typ. Diode Recovery T J = 5 C using Fig. CT time (µs) Fig. WF- Typ. S.C T J = 5 C using Fig. CT.3

12 IRG/B/S/SLBKD TO-AB Package Outline Dimensions are shown in millimeters (inches).7 (.3). (.3).5 (.5).9 (.5) 3.7 (.9) 3.5 (.39) - A -.9 (.5). (.5) - B -.3 (.5). (.) 5. (.). (.5).9 (.555) 3.7 (.53) 3.7 (.55). (.).5 (.5) MIN. (.) 3.55 (.) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE - DRAIN - GATE - DRAIN 3 - SOURCE - COLLECTOR 3- SOURCE - DRAIN 3- EMITTER - DRAIN - COLLECTOR 3X. (.55).5 (.5) 3X.93 (.37).9 (.7).3 (.) M B A M.55 (.) 3X. (.).9 (.5). (.).5 (.) X NOTES: DIMENSIONING & TOLERANCING PER ANSI Y.5M, 9. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-AB. CONTROLLING DIMENSION : INCH HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 79 ASS EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 997 WE E K 9 LINE C

13 IRG/B/S/SLBKD D Pak Package Outline Dimensions are shown in millimeters (inches) D Pak Part Marking Information THIS IS AN IRF53S WIT H LOT CODE AS SEMBLED ON WW, IN THE ASSEMBLY LINE "L" Note: "P" in assembly line pos ition indicates "L ead-f ree" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F53S PART NUMBER DATE CODE YEAR = WEEK LINE L INTERNAT IONAL RECT IFIER LOGO ASSEMBLY LOT CODE F53S PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR = WEEK A = ASSEMBLY SIT E CODE 3

14 IRG/B/S/SLBKD TO- Package Outline Dimensions are shown in millimeters (inches) TO- Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 79 AS S EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line pos ition indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C INT ERNAT IONAL RECTIFIER LOGO AS S E MB LY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 997 WEEK 9 A = AS S EMBLY SITE CODE

15 D Pak Tape & Reel Information Dimensions are shown in millimeters (inches) IRG/B/S/SLBKD TRR. (.3).5 (.59). (.) 3.9 (.53). (.3).5 (.59).3 (.5).3 (.35) FEED DIRECTION TRL.5 (.73).5 (.5).9 (.9).7 (.). (.57). (.9). (.3) 5.9 (.).75 (.9).5 (.9) 5. (.9) 5. (.).3 (.957) 3.9 (.9).7 (.3).5 (.7) FEED DIRECTION 3.5 (.53). (.5) 7. (.79) 3.9 (.9) 33. (.73) MAX.. (.3) MIN. NOTES :. COMFORMS TO EIA-.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB.. INCLUDES FLANGE OUTER EDGE.. (.39). (.9) 3 3. (.97) MAX. Notes: This is only applied to TO-AB package This is applied to D Pak, when mounted on " square PCB ( FR- or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-99. ƒ Energy losses include "tail" and diode reverse recovery. V CC = % (V CES ), V GE = V, L = µh, R G = Ω. TO- package is not recommended for Surface Mount Application Data and specifications subject to change without notice. This product has been designed and qualified for Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 95, USA Tel: (3) 5-75 TAC Fax: (3) Visit us at for sales contact information. / 5

16 Note: For the most current drawings please refer to the IR website at: