PAD: Procedural Analog Design Tool D. Stefanovic, M. Kayal, M. Pastre

Transcription

1 PAD: Procedural Analog Design Tool D. Stefanovic, M. Kayal, M. Pastre Swiss Federal Institute of Technology, Electronic Labs, STI/IMM/LEG, Lausanne, Switzerland

2 Procedural Analog Design Tool Interactive chart-based tool Dedicated to step-by-step design of analog cells The present version covers the design of: basic analog structures procedural design of OTAs and different operational amplifiers topologies (complex analog structures) Transistor-level calculator embedded in PAD uses the complete set of equations of the EKV MOS model

3 Top down system design approach Digital Behavioral modeling and simulation Analog PAD tool Behavioral simulation and synthesis Specs of basic blocks Circuit schematic Layout generation, extraction and post layout simulation Transistor sizing Layout generation, extraction and post layout simulation Assembling

4 Combine approaches: PAD tool Analog Structures Sizing and Layout Generation Procedural Design of Complex Analog structures top-down High Level Behavioural System simulation (VHDL_AMS, VerilogA,...) System On Chip Complete design methodology, from system-level to transistor-level bottom-up Structured Transistor-level Design of Analog Cells Analog structures library, Procedural design methodology

5 PAD structure

6 The charts!

7 EKV MOS model Transistor level calculator dedicated to the design of analog circuits based on device physics links weak and strong inversion in a continuous way has small number of model parameters, but good accuracy solutions for different input parameter sets are found without using complex numerical methods large number of transistor parameters can be extracted

8 Analog structures library single transistor current mirror cascode current mirror differential pair cascode stage folded cascode stage common source common drain general params small signal params DC biasing values parasitic capas transition frequency specific params maximum DC offset current mismatch output resistance gain

9 g m /I D design procedure set priority targets (gain, noise, speed ) choose bias current and accordingly gm/id ratio change free variables (W, L) observe effects on other parameters

10 Procedural Design of Complex Structures Circuit Partitioning Chart-Oriented Basic Analog Structures Sizing Circuit Level Performances

11 Procedural Design of Complex Structures

12 Procedural Design of Folded Cascode OTA V DD m20 m18 m17 m9 m10 m12 m14 V DD V DD V DD V DD V DD V DD V DD V bias1 V bias1 V bias1 m7 m8 m11 V bias3 I bias I bias I o m1 m2 V DD I 2 I 2 V DD V DD V bias4 I bias2 m15 V out m19 V bias2 V DD m3 V DD I 1 I 1 m4 V ss m5 m6 V ss V bias2 I bias1 m13 V ss m16 V DD C L V ss V ss V ss V ss V SS

13 PAD Design Flow Initialisation :

14 PAD Design Flow Circuit partitioning : I bias I bias p current mirror folded cascode pair cascode current mirror bias3 bias4 n current mirror

15 PAD Design Flow Determination of circuit currents : V DD I I o _ calc I o = SR o C L _ calc m1 I o m2 I 2 I 2 I 2 = V bias4 I 1 I o 2 V DD V DD V ss m5 m6 V ss I o I 1 n I o I 1 I 1 g _ calc = 2π f _ GBW m C L V SS

16 PAD Design Flow SR, CMR +, CMRR, PSRR + Sizing of basic analog structures : CMR -, PSRR -, noise, stability I bias I bias p current mirror folded cascode pair n current mirror gain, noise, offset, stability, output swing cascode current mirror GBW, gain, noise, offset, stability

17 Circuit level design : PAD Design Flow

18 Circuit level design : PAD Design Flow

19 Circuit level design : PAD Design Flow

20 Circuit level design : PAD Design Flow

21 Conclusion new chart-based procedural analog design tool new knowledge-based analog design methodology design and re-design of wide range of circuits didactical tool that helps to hand analog knowledge towards non-expert designer

22 Download If you have any questions: