Transistor-Level Fault Detection Based on Power. Gianluca Cornetta, Jordi Cortadella. Department of Computer Architecture

Transcription

1 Transistor-Level Fault Detection Based on Power Consumption Gianluca Cornetta, Jordi Cortadella Department of Computer Architecture Universitat Politecnica de Catalunya 87 Barcelona, Spain fcornetta, January 4, 997 Abstract Gate level fault models, although simplify test pattern generation and permit to gather dierent faults into equivalence classes, in some case are unrealistic and may lead to test invalidation since they do not take into account the physical aspects of the problem. In general all the faults that may aect a circuit may be divided into shorts and opens, a logic test may not be able to detect all the possible shorts and opens. The detectability or not of a fault is strictly tied to physical factors such as layout structure and technology used, since these parameters may determine whether the output of a faulty gate is indeterminate or not. The presence of indeterminate logic values at a faulty gate output is an hard-to-solve problem in high level test generation, because, if the faulty gate has multiple fanouts, it is not guaranteed the fault to propagate along all the fanouts. The necessity of a test strategy closer to the physical nature of a fault has led to the exploitation of current monitoring as a means to test a faulty circuit. In fact it has been found that the quiescent currents of a faulty circuit are at least two or three times the ones of a fault-free circuit. Thus a faulty circuit has a power consumption bigger than a fault-free circuit. A current test has the advantage that a test pattern may be easily generated for all the multiple physical faults that are current-testable, on the other hand it does not detect all the possible physical faults and it is slowlier than a voltage test since we have to wait for the transient currents to settle, before performing the measurement. Anyway, the scientic community seems to agree with the idea that the testing strategy that oers the best fault coverage is a combined current and voltage test. The measurement of the faulty currents is performed by an analog sensor that may be placed on or o-chip. Built-in current sensors lead to a faster test but they also complicate and slow down the circuit to be tested. This problems may be avoided using an external sensor, anyway such sensors slow down the test. In this paper we perform a study on several types of physical faults, analyzing the eect of the fault on the power consumption of the gate. Almost in every case analyzed we have found an increase in the quiescent current of the faulty gate and hence in power consumption. Finally we study two possible implementations of built-in current sensors for monitoring the quiescent currents in integrated circuit.

2 Introduction Progress in VLSI technology has produced very complex chips lowering drastically the implementation costs of complex designs. However the nal product is not guaranteed to be fault free due to fabrication errors. The probability that errors in the process could lead to a malfunctioning device is even higher for implementations with a great number of transistors. In addition, even if a design behaves correctly it is not guaranteed to be free of fabrication defects, and such defects, so long, may lead to malfunctioning. As we have pointed out, a fault may be caused by an erroneous manufacturing process such as photo-lithography errors, deciencies in process quality that may lead to contamination, improper contacts, electromigration, corrosion, oxide defects, as well as incorrect design or specication of the system. Also environmental eects, such as alpha particles and cosmic radiation may produce an erroneous behaviour. Furthermore, even if a chip is manufactured perfectly, it could subsequently be worn out because of electromigration, hot-electrons injection, spreading charge loss. A physical failure may also produce an output at a non-logical value, i.e. a value between logic and called indeterminate. Such faults are dicult to describe and detect, but the errors due to such faults may be detected by error detection techniques. It is necessary to study the eects of failures at the transistor level and develop accurate fault model at this level, since a good understanding of fault eects at a lower level may be of great help in developing fault models at a higher level of abstraction which may be used for complex systems. The problem of test generation consist in deriving a sequence of input vectors, as short as possible, capable of detecting the presence of a certain type of fault. The eventually faulty behaviour must be observed in one of the primary output of the circuit under test. The nature of the fault strongly inuence test generation. It is clear that the more the fault model is near to the physical nature of the fault, the higher is the quality of the test. However, a physical model also increases test generation time. So two contradictory requirements have to be satised: sucient failure coverage and fast test generation time. In practice, rather than considering individually each kind of fault, it is a common approach to introduce a more general model which may represent all of these faults according to their logical eects on the output of the circuit under test. This model is known as the stuck-at model. A Review of MOS Transistor Theory A MOS (metal-oxide-semiconductor) transistor is an electronic device capable of regulating the current ow between two electrodes called source and drain (see Figure ). The current ow between source and drain is regulated by applying a particular voltage to a third electrode called gate. The name MOS has been kept for historical reasons since the gate electrode of the actual devices is implemented in polysilicon, i.e. a crystalline form of silicon with the electrical properties similar to those of the metal. There are two types of MOS transistors, according to the which is the majority carrier. In NMOS devices the majority carriers are the electrons so the channel is n-doped while source and drain are p-doped. In PMOS devices the majority carriers are the holes so the channel is p-doped while drain and source are n-doped.. The Enhancement MOSFET At zero gate voltage the device does not conduct; the magnitude of the output current increases as the magnitude of the gate potential increases.

3 gate source drain t ox L. The Depletion MOSFET Figure : MOS Transistor Structure. A depletion device has a narrow channel between source and drain, so it already conducts for V GS = ; for V GS < the charges in the channel decrease and for V GS = V T they are completely depleted and the channel is pinched-o. The device may work in enhancement mode as well, applying a positive gate voltage. The current owing in the channel when the device is in enhancement mode is clearly greater than the current owing when in depletion mode, because the number of carrier is enhanced. The behaviour of a depletion MOSFET is ruled by the same equations of an enhancement MOSFET, the only dierence is that the threshold voltage V T is lesser than zero..3 The Enhancement NMOSFET Volt-Ampere Characteristics When the gate voltage is below the threshold, i.e. when V GS < V T, there is no channel established between source and drain, so drain current I D is zero and the device is cut-o. When V GS > V T the MOSFET is said to be in the ohmic region. In this region the device behaves as a resistor whose value is controlled by V DS. In the ohmic region we have: V GS? V T > V DS (or V GS? V DS = V GD > V T ) W I D = K L (V GS? V T )V DS? V DS Where L is the channel length, W the channel width and K = ""ox t ox is the process gain factor. Furthermore, represents the carrier mobility ( n for NMOS devices and p for PMOS devices), " = 8:85?4 Fcm? is the permittivity of free space, " ox is the relative permittivity of the insulation between gate and channel (" ox = 4 for silicon dioxide) and t ox is the thickness of oxide strate. If we do not take into account the Early eect, in saturation region the drain current I D is constant and independent of V DS. So we have: V GS? V T < V DS I D = K (but greater than zero) () W (V GS? V T ) = I DS () L The subscript S in I DS stands for saturation. The dividing line between the ohmic and saturation regions is obtained for V GS? V T = V DS, so I D becomes: 3

4 I D = K W VDS (3) L In reality, in the saturation region, the I D versus V DS characteristics are not constant, but present a certain slope due to Early eect. However this eect is negligible for digital circuits while must be taken into account for analog design..4 Enhancement PMOSFET Volt-Ampere Characteristics The equations that rule a p-channel MOSFET are the same that those for a n-channel device, the only dierence is in the polarities of currents and voltages. In Figure are shown the I DS versus V DS plots for a NMOS and a PMOS transistor. Ids [ma] :5 : Vgs=5V : :8 Vgs=4V :5 Vgs=3V : Vgs=V : 3 Vds [V] 4 5 (a) :?: Vgs=-V?:5 Vgs=-3V Ids [ma]?:8 Vgs=-4V?:?: Vgs=-5V?:5?5?4?3?? Vds [V] (b) Figure : I DS versus V DS Characteristics for: (a) a NMOS Transistor, (b) a PMOS Transistor. The plots of Figure refer to a NMOS and a PMOS transistor whose design parameters are shown in Table. Parameter Device Type NMOS PMOS W 3 m 9 m L.6 m.6 m K 7. AV? 9.7 AV? 5 cm V? s? cm V? s? V T.7 V -. V Table : Transistor Characteristic Parameters. The set of curves of Figure are a graphical representation of equations () and () for dierent values of V GS..5 The Eect of Carrier Mobility on Drain Current The typical hole mobility is about 5 cm Vs at normal eld intensities, while typical electron mobility for the same conditions is about 3 cm Vs, this means that for devices having the same dimensions: the current in a PMOS transistor is less than a half of that in a NMOS device; 4

5 the on-resistance of a PMOS transistor is nearly three times that of a NMOS. In order to achieve the same values of current and on-resistance for both the device types we must operate on the W L ratio of the PMOS transistor increasing it (a PMOS is roughly three times a NMOS). This justies our design choice of implementing the p-type transistor with a gate area three times greater than the gate area of the n-type one (see Table ). As we may note in Figure, with this design choice, the drain currents for both n and p devices are approximately the same..6 The CMOS Inverter Figure 3 shows the layout of a CMOS inverter. source n-tub V dd n diff p diff metal poly drain in p-type transistor out n-type transistor drain p-tub tub-tie V ss source Figure 3: Layout of a CMOS Inverter. According to what has been said previously, the p-transistor area is three times that of the n-transistor. The step response and the rail to rail current of this implementation are shown in Figure 6. The smaller peak in Figure 6(b) is due to parasitic currents in the device; furthermore, from Figure 6(b), we also note that the short circuit current does not reach its maximum for t = ns as one would expect. This is due to the fact that the threshold voltages of n and p devices are dierent, i.e. V Tn <j V Tp j, thus the n-transistor saturates before its complementary device, shifting the curve to the left. Figure 6(b) clearly shows that the maximum current ow between V DD and V SS occurs when the inverter switches, i.e. when both the p and n device are in the saturation region. In all the other cases, rail to rail current is zero so the gate does not consume energy..7 On-Resistance Estimation When in the ohmic region a transistor behaves like a resistor, while in saturation region its behaviour is, approximately, that of a constant current source. However it is good to choose a unique resistor value to represent the transistor over its entire operating range. An approximate calculation consist in nding the transistor resistance in two points of its characteristic and then taking the average of these two values. To achieve this we evaluate the 5

6 resistance in the middle of the linear region and the resistance in the saturation region as also expressed by (4): where: R on = Vsat I sat + Vlin I lin V lin = V DD? V T From the analysis of the characteristics of Figure or, equivalently, from () and (), we obtain: R onn = R onp ' 3K.8 The Eect of n = p Ratio on the Transfer Characteristic The gain is dened as: W = K L Thus, for a given process, if we want to change the gain factor of a transistor, we must act on its geometry modifying the aspect ratio W L. As the n= p ratio change, also the transfer characteristic changes. If n = p is decreased the transition region shifts from left to right, if the ratio is increased the transition region shift in the opposite direction. However the switching capabilities of the gate are not aected by the variations of the n = p ratio, i.e. the transfer characteristic maintains the same slope in the switching region independently of the value of n = p. This is not true for an NMOS inverter where the transition gain is aected by the gains of both pull-up and pull-down transistors. For a CMOS inverter a ratio of: n p = is often preferable since it allows the capacitive load to charge and discharge in the same amount of time because source and sink currents are the same. However, in many conguration, the n = p ratio is often unimportant, so minimum size congurations are used for both p and n-transistors. 3 Fault Models at Transistor Level The physical faults that may aect a design implementation may be divided into two categories: faults that aect the interconnections; faults that aect the transistors. Both these categories are, as a matter of fact, shorts or opens between metalization or diusions. A short between metalizations is formed by connecting points not intended to be connected, an open is generated by a broken connection. If the short or open aects the diusions, the faulty transistor may result stuck on or stuck o. In case of a stuck o fault the faulty transistor is permanently interdicted, in case of a stuck on fault the faulty transistor permanently conducts. Mild shorts and opens, that is shorts and opens that have an intermediate resistance (of the magnitude of few M) may result in slow on or slow o faulty transistors. When the faulty transistor switches slowly we are in presence of a slow o (4) 6

7 fault if the transistor goes in the interdiction region slowlier than expected, or of a slow on fault if the transistor conducts slowlier than expected. Another type of fault aecting the transistor is the oating gate fault; this fault occurs when the polysilicon line that drives a transistor gate is broken. In MOS networks, the lines left in an high impedance state (oating) will keep their previous logic value for a relatively long time, until their charge leaks away. This is due to the capacitance of the lines. Because of this property, faults in MOS circuits may lead to situations where stuck-at tests may not detect some of the transistor-level shorts and open. The simplest models only take into account shorts and opens of transistor interconnections while the most accurate also evaluate the delay eect of failures. Coupling and crosstalk between nodes are taken into account only by the fault models for memories, while degradation of devices is used only in models for analog circuits. A short or an open among the interconnections may be modeled as a resistance; an hard short is characterized by low resistance values, that may reach few halfs a score of K. A mild short or open, instead, has a resistance of few M. Figure 4 shows all the possible shorts that may aect a transistor. D G S Figure 4: Shorts aecting a transistor. In [], the authors modeled MOS faults through an extra fault transistor. The gate nodes of the fault transistors are considered to be extra fault inputs. To each transistor is also assigned a discrete strength i, in order to model the behaviour of NMOS logic. The strength p+ is greater than that of any normal transistor. Figure 5 shows the class of MOS failures using the additional fault transistor. When the fault is active the input f is equal to. In our simulation we will model shorts and opens simply as a resistance having an opportune value. Galiay et al. [6] in a study performed on a 4 bit microprocessor found that the great majority of the faults aecting circuit layout were shorts and opens at the level of the metalizations and at the level of the diusions. It is interesting to note that no short between metalizations and diusion was observed. We report in Table the results of such study. Failure Occurrence Short between metalizations 39% Open metalization 4% Short between diusions 4% Open diusion 6% Short between metalization and substrate % Unobservable % Insignicant 5% Table : Observed Failure Mode. 7

8 n γ p+ γ p+ (a) n (b) t γ i t γ i γ i f f γ i (c) f (d) f n m n m γ p+ γ p+ (e) (f) Figure 5: Modeling MOS failure with an Extra Fault Transistor: (a) Node n Stuck at, (b) Node n Stuck at, (c) Transistor t Stuck o, (d) Transistor t Stuck on, (e) Nodes m and n Shorted, (f) Open between Nodes m and n. It also has been found that all the failures are randomly distributed. Examining Table we may observe that in the % of the cases the circuit was faulty at the logical level but no physical faults was observable. Finally, in the 5% of the cases the circuit presented a very large imperfection, for example a scratch from one side to the other of the chip, that is obviously insignicant for test purposes since such faults may be detected by any test sequence. Many test generation algorithms for detecting transistor faults in combinational logic have been developed. In [], for example. the D-algorithm was used to generate tests for MOS circuits, after converting the transistor network into an equivalent logical network of conventional gates. The only faults considered were transistor level shorts and opens, that were modeled as stuck-at faults at the gate level. The problem of this technique is that the transistor faults considered do not cover all the possible physical faults that may aect a layout. For example, the algorithm is not designed to detect faults that are likely to occur such as short between gate and drain or gate and source. 3. Shorts A short may be due to impurity in the mask during the fabrication process or to electromigration. If the short causes the circuit to look as if the faulty transistor were permanently on, both P and N networks of the CMOS circuit may conduct and the fault may or may not be detectable. Depending upon the resistance of the transistors some potential vectors may not detect this kind of fault while others will. Let us consider the CMOS inverter of Figure 7, whose design parameters are summarized in Table. The voltage and current responses of this device are shown in Figure 6, while the total number of possible shorts are resumed in Table 3. We again point out that the short may be between interconnections or between diusions; short resistances of up to few halfs a score of K are referred as hard shorts. Low hard shorts values refers to shorts between metalizations; higher values are, clearly, intended to represent shorts between diusions. In the simulation performed, we modeled the short as a resistance of joining two electrodes (gate, source and drain). This seems a quite realistic value for shorts 8

9 [V] Vout 3 Vin * q? : :4 :8 : :6 : (a) [ma] : :5 : :5 : : :5 : :5 : (b) Figure 6: CMOS Inverter: (a) Response, (b) Rail to Rail Current. S In G G T D D T S Out Figure 7: CMOS inverter. 9

10 between interconnections. Transistor T T T Shorted Terminals gate-source source-drain gate-drain T gate-source source-drain Table 3: Possible shorts in a CMOS Inverter. Let us consider rst the short between source and gate of transistor T of the CMOS inverter. Applying at the gate input In, the pattern In =, such fault should be detectable since the gate output should, theoretically, be instead of. This, in general, is not true, because this fault may be not testable by voltage. The testability or not depends on the strength of the driving gate. The stronger is the driver, the lesser this fault is testable. Anyway this fault may be detected by an I DDQ test, since it alters the rail to rail current as also shown in Figure 8.? [A]??3?4?5 : :5 : :5 : Figure 8: Rail to Rail Current of the Inverter when Transistor T has Source and Gate Shorted. From Figure 8 is clear that this kind of short generates a current that the transistor cannot handle, since the maximum I D for both P and N devices is approximately. ma. Let us, now, consider the NOR gate of Figure 9(a), whose inputs are those shown in Figure 9(b). A gate-source short of transistor T in the NOR gate of Figure 9(a) may produce an intermediate output voltage so it is not guaranteed to be detectable by a voltage test since the next gate may interpret a non logical value either as a logical or as a logical. However this kind of fault is I DDQ testable as shown in Figure. In the case of an inverter shorts between gate and drain are detectable both with a voltage and an I DDQ test since input and output of the logic gate under test are short-circuited, thus the output of the gate always follows the input; Figure (a) shows the rail to rail current when input and output of the inverter are shorted. The previous assumption is not valid for a more complex gate; let us consider again the twoinput NOR of Figure 9(a).

11 5 a T 4 b T a, b [V] 3 T3 T4 a Y : :5 : :5 : (b) Figure 9: Two-Inputs Nor Gate: (a) Transistor Level Representation, (b) Input Voltage. :4 : :3?: [ma] : [ma]?:4 :?:7 : :5 :5 (a)?: : :5 : :5 : (b) Figure : Rail to Rail Current for : (a) Fault-free Nor Gate, (b) Faulty Nor Gate with T Gate and Source Shorted.

12 The short between gate and drain of transistor T produces an intermediate output voltage that may be interpreted by the next gate either as a logical or as a. Figure (b) shows the rail to rail current of a faulty NOR gate with gate and drain of transistor T shorted. How we may see it is slightly dierent from Figure (a), so such fault is I DDQ testable. : :?:?: [ma]?:4 [ma]?:4?:7?:7?: : :5 : :5 : (a)?: : :5 : :5 : (b) Figure : Rail to Rail Current of : (a) an Inverter with Gate and Drain Shorted, (b) a Nor Gate with Gate and Drain of T Shorted. In case of a short between source and drain the gate behaves as if the faulty transistor were permanently on. Also in this case a voltage test does not guarantee the fault to be detected, since the output may be an intermediate voltage that may be interpreted by the next gate either as a logical or as a. This is what happens, for example, if either transistor T or T of the NOR gate of Figure 9(a) has source and drain shorted. :4 :4 :3 :3 [ma] : [ma] : : : : : :5 : :5 : (a) : : :5 : :5 : (b) Figure : Rail to Rail Current of a Faulty Nor Gate with : (a) Source and Drain of T Shorted, (b) Source and Drain of T Shorted. Figure shows the rail to rail currents in the NOR gate when the input pattern is that shown in Figure 9(b). With such test pattern the fault is, probably, undetectable by an I DDQ test as well, since the current of both fault-free and faulty gate are similar. If we apply the input pattern of Figure 3(a) and 3(b) we obtain the rail to rail currents shown in Figure 3(c) and (d). With this test pattern the faults are detectable by an I DDQ test. Also in the case of the inverter (see Figure 4), the shorts between source and gate are detectable performing an I DDQ test. Let us now consider the other two type of faults aecting transistor T of the CMOS inverter

13 a [V] 3 b [V] 3 : :5 : :5 : (a) : : :5 : :5 : (b) : : : [ma]?:?:4 [ma]?:?:4?:6?:6?:8 : :5 : :5 : (c)?:8 : :5 : :5 : (d) Figure 3: Faulty Nor Gate: (a) Input Voltage a, (b) Input Voltage b, (c) Rail to Rail Current when T has Source and Drain Shorted, (d)rail to Rail Current when T has Source and Drain Shorted. : : [ma]?:?:4?:6?:8 : :5 : :5 : Figure 4: Rail to Rail Current of a Faulty Inverter with Source and Drain of the T Shorted. 3

14 of Figure 7. In Figure 5 are represented the rail to rail currents of the inverter in the cases of a gate-source and a source-drain short. : : :5?: [ma] : [ma]?:4 :5?:7 : : :5 : :5 : (a)?: : :5 : :5 : (b) Figure 5: Rail to Rail Current of a Faulty Inverter with : (a) Source and Gate of T Shorted, (b) Source and Drain of T Shorted. As we may see from Figure 5(a), a short between gate and source of the transistor T of the CMOS inverter of Figure 7 does not aect the consumption of the gate, since rail to rail current of both faulty and fault-free device are approximately the same. This fault is detectable by applying at the gate input In the pattern In = only if the strength of the driving gate does not overcome that of V SS line connected to T source. If the driving gate is suciently weak, in case of shorts between T gate and V DD or T gate and V SS, the inverter should behave as if the input were stuck at or stuck at. This means that under these conditions the gate does not dissipates any dynamic power, since no transition occurs. 5 T T 4 a T 3 Y a, b [V] 3 b (a) T 4 : :5 : :5 : (b) Figure 6: Two-Inputs Nand Gate : (a) Transistor Level Representation, (b) Input Voltages. Let us consider a gate-source short aecting transistor T 3 of the NAND gate of Figure 6(a); with the test pattern of Figure 6(b), also this fault seems not testable by current but only by voltage, since current consumption of both faulty and fault-free gate are approximately the same (see Figure 7). In reality the testability or not of gate to source shorts of p-type transistors depends upon the strength of the driving gate. This kind of faults is I DDQ testable only if the driver of the faulty gate is suciently weak, as demonstrated in Figure 8, where the faulty NOT and NAND gate 4

15 :4 :4 :3 :3 [ma] : [ma] : : : : : :5 : :5 : (a) : :5 :5 (b) Figure 7: Rail to Rail Current of a : (a) Fault-Free Nand Gate, (b) Nand Gate with Gate and Source of T 3 Shorted. are driven by a four low- inverters chain. : : :8 :8 :6 :6 [ma] :4 [ma] :4 : : : :?: :5 :5 (a)?: :5 :5 (b) Figure 8: Rail to Rail Current of a : (a) Faulty Inverter with Gate and Source of T Shorted, (b) Faulty Nand Gate with Gate and Source of T 3 Shorted. Applying to the gate input the test pattern (a; b) = f(; ); (; )g the short between gate and drain of transistor T 4 may be detected, as also shown in Figure 9(a). A short between source and drain of transistor T 3 of the NAND gate of Figure 6 may not be observable by voltage since it produces at the gate output an intermediate voltage that may be interpreted by the next gate either as a logical or as a logical. However this fault may be easily detected by a current test with pattern (a; b) = f(; ); (; )g because the power consumption of the gate increases, as shown in Figure 9(b). Let us now introduce the concepts of parallel and series connections, conducting path and elementary transistor subnetwork. Denition (Parallel Connection) Let T j and T k, with j 6= k, two generic MOS transistors. Then T j and T k are said to be connected in parallel (T j k T k ) if and only if source(t j ) = source(t k ) and drain(t j ) = drain(t k ). Denition (Series Connection) Let T j and T k, with j 6= k, two generic MOS transistors. Then T j and T k are said to be connected in series if and only if drain(t j ) = source(t k ) or source(t j ) = drain(t k ). 5

16 : : : : [ma]?:?:4 [ma]?:?:4?:6?:6?:8 : :5 : :5 : (a)?:8 : :5 : :5 : (b) Figure 9: Rail to Rail Current of a Faulty Nand Gate with: (a) Gate and Drain of T 4 Shorted, (b) Source and Drain of T 3 Shorted. These denitions may be easily extended to the case of the interconnections of n transistors, with n >. Denition 3 (n-conducting Path) Let T j be a generic MOS transistor, let g(t j ) be the logic gate input that controls T j gate, i.e. g(t j ) f; g. Let y be the logic gate output to which T j belongs and N n be a complex n-transistors network. The n-conducting path Cn i is the subset of n-type transistors that satisfy the following condition: C i n = ft j N n j Y j g(t j ) = ; all the T j C i n are connected in series; 9T k; T l C i n such that drain(t k ) = y and source(t l ) = V SS g Analogously, the p-conducting path may be dened as the subset of p-type transistors that satisfy the following condition: C i p = ft j N p j Y j (g(t j ) = ; all the T j C i p are connected in series; 9T k ; T l C i p such that drain(t k ) = y and source(t l ) = V DD g Note that it is not excluded that could be k = l; in this case, clearly, the conducting path is formed by only one transistor. Denition 4 (Elementary n-subnetwork) Let T j be a generic MOS transistor, let g(t j ) the logic gate input that controls T j gate and N n be a complex n-transistor network. The elementary n-subnetwork S i n is the subset of n-transistors that satisfy the following condition: Sn i = ft j N n j6 9T l N n with l 6= j and T j k T l ; if C(Sn i ) > ) ft jg Sn i are connected in seriesg 6

17 Where C(S i n) is the cardinality of the set S i n. Analogously the elementary p-subnetwork S i p may be dened as: Sp i = ft j N p j6 9T l N p with l 6= j and T j k T l ; if C(Sp) i > ) ft j g Sp i are connected in seriesg According to denition 4, the NOR gate of Figure 9(a) has one p-subnetwork, that is Sp = ft ; T g and two n-subnetworks: Sn = ft 3 g, S n = ft 4g. Analogously, the NAND gate of Figure 6(a) has two p-subnetworks: Sp = ft g, S p = ft g, and one n-subnetwork, that is Sn = ft ; T g. The experimental results of the simulations performed are summarized in Table 4. Network Short Gate NOT NOR NAND voltage current voltage current voltage current Source-Gate y y y P Source-Drain YES YES I YES YES YES Gate-Drain YES YES YES, I YES YES YES Source-Gate y y y N Source-Drain YES YES YES YES I YES Gate-Drain YES YES YES YES YES, I YES Table 4: Experimental Results with a Hard Short of. With we have indicated that class of faults that, depending on the driving gate, may be detectable, undetectable or produce an indeterminate output. With I we have indicated that class of faults that always produces an indeterminate output. With y we have labeled that class of faults that is I DDQ testable only if the driving gate is suciently weak. In reality, this kind of fault is always testable, since it is likely to suppose that an intermediate voltage falls at the transistor gate. Consequently, even if such voltage is not sucient to saturate the transistor, it is sucient to make the device conduct, thus establishing a low resistance conducting path between the power rails. A short that is untestable may be extremely dangerous since it aects the dynamic behaviour, reduces the noise margin and cause the chip to age quickly due to large power consumption. The simulation results are summarized in the following denition: Denition 5 (IDDQ testability) A faulty circuit aected by a single hard short is NOT testable by current if and only if the faulty transistor T j N is such that source(t j ) and gate(t j ) are shorted and gate(t j ) is controlled by a strong driver. We must, moreover, point out that the bridges between input and output that we have simulated do not induce oscillations in the gate response, since the simulations have been performed with a strong driver, so the logic value inputed by the driver always prevail over the one returned by the feedback loop. We will deal with oscillating bridging faults in the next section. 3.. Some Remarks on Test Pattern Generation Test pattern generation strictly depends on several physical factors: layout structure, fanout of the gates, type of physical fault and technology. This kind of fault is detectable only if the drain of the faulty transistor is connected to the output node of the logic gate. 7

18 As we will see in the next sections, the interconnections at logic gate level do not reect the real interconnections among the transistors; so, when considering the gate level representation of a certain logic function it is possible to generate a test pattern for a fault that does not exist physically. Moreover if a faulty gate produces a non-logical value at its output, this value may be interpreted by the next gate correctly or not; so if the faulty gate has multiple fanout it is not guaranteed that the error will propagate along all the paths and this may be a serious problem when generating the test pattern. Test pattern generation also depends on the type of fault; for example, as we have already seen, bridging in the interconnections are testable with deterministic test. This is not true in case of oating gate, as we will see later on. Let us, now, consider the NMOS NAND gate of Figure and let us suppose that a bridge exist between gate and source of transistor T. The detectability or not of such fault depends on several factors: the value of the bridge resistance; the load of the faulty gate; the strength of the driver of the gate of T. It is clear that the higher is the bridge resistance, the lesser the fault aects the behaviour of the gate, since a very high resistance is equivalent to an open circuit. o a T b T Figure : Two-Input NMOS Nand Gate. A very important factor is the load of the gate, since it determines the working point of the transistors. Let us suppose that both the inputs are and that the gate load is such that the V DS of T is 3 Volts; this means that if the driver of the gate of T is suciently weak and the short resistance suciently small, the V GS of T is Volts. If the characteristics of the n-transistor are those shown in Figure, the resulting V DS is less or equal to Volt, so the output voltage falls in the range between 3 and 4 Volts. This means that this fault, in this conditions may produce an indeterminate output. If the voltage drop between source and drain of T rises, the gate to source voltage drop of T goes down and may be less than the threshold voltage V T. In this case, even if the gate input of T is at the logical, the transistor is interdicted, the gate of T results to be stuck at and the test pattern to detect this fault is (a; b) = (; ). In CMOS circuits, faults aecting the n-network have a direct correspondence with the faults in a NMOS circuit. Anyway, the presence in a CMOS circuit of a pull-up complementary stage, may result in untestable faults. Let us suppose that transistor T of the NMOS NAND gate of Figure have a source to drain hard short. This fault is equivalent to an input a stuck at fault and is easily detected by the test pattern (a; b) = (; ), since a low-resistance conducting path has been created among the gate output and V SS. The same test pattern, unfortunately does not detect the input a stuck at fault of the CMOS NAND gate of Figure 6(a) if the same kind of 8

19 short aects transistor T 3, since there are two low resistance conducting path, one toward V SS and the other toward V DD, thus the gate output is indeterminate. 3.. Fault Detection Based on Power Consumption The simulations performed on faulty gates aected by shorts among the metalizations have shown that the rail to rail current, i.e. the current that ows between V DD and V SS rails is three o four times that of a fault-free gate. This means that a faulty gate has a power consumption greater than that of a fault-free gate. Power consumption of a CMOS gate is the sum of two components: static dissipation, due to leakage currents; dynamic dissipation, due to switching transient current or to the charging and discharging of the load capacitances. When the gate output is in the logic state the p-transistor network is disconnected; when in logic state the n-transistor network is disconnected, so there is no path established between V DD and V SS so the resultant quiescent current and hence the power are zero. However, the junction between the wells and the substrate forms a parasitic diode. Fortunately this diode is reverse biased so the parasitic currents involved are reverse bias leakage current and their eect is, in general, negligible. Anyway, this is not true for submicronic technologies, where static dissipation must be taken into account. During the transition from either to or vice versa, p and n-transistor are both in saturation for a short period of time. This time is sucient to establish a conductive path between V DD and V SS rails. A current is also needed to charge and discharge the output capacitive load. The dynamic dissipation may be computed assuming that rise and fall time of the input signal are negligible when compared with the repetition period. The average dynamic power P avg dissipated during switching for a square wave input with a repetition frequency f in = t in is given by (5): P avg = Z tin t in i n (t)v o dt + Z tin i t in t p (t)(v DD? V o ) dt (5) in Figure shows power consumptions of both a fault-free and a faulty CMOS inverter with a short between source and drain of the pull-up transistor. : 4 :8 3 P [mw] :6 :4 P [mw] : : : :5 : :5 : (a) : :5 : :5 : (b) Figure : Power Consumption of a: (a) Fault-Free CMOS Inverter, (b) Faulty CMOS Inverter with Source and Drain of the Pull-Up Transistor Shorted. From the analysis of Figure we may see how the maximum instantaneous power P(t) dissipated by the faulty gate is more than four times the one dissipated by the fault-free gate. The 9

20 average power consumption P avg of the faulty inverter is.7 mw, while the average power consumption of the fault-free inverter is W. Fault-free NOR and NAND gates dissipate 8 and 36 W respectively. From these results we may deduce that an estimation of the power consumption may be used for detecting faulty circuit since the power dissipated by a circuit with fabrication defects increases enormously with respect that of a circuit without defects. Tables 5, 6, 7, report the average power consumption of the faulty inverter, NOR and NAND gate respectively. Transistor Shorted Terminals P avg T gate-source 3.3 W source-drain.7 mw T T gate-drain.6 mw T gate-source.9 mw source-drain.8 mw Table 5: Average Power Dissipation of a Faulty CMOS Inverter. Transistor Shorted Terminals P avg T gate-drain.6 mw source-drain.77 mw T gate-source.6 mw source-drain.6 mw Table 6: Average Power Dissipation of a Faulty CMOS Nor Gate. Transistor Shorted Terminals P avg T 3 gate-source.6 mw source-drain.43 mw T 4 gate-drain.43 mw Table 7: Average Power Dissipation of a Faulty CMOS Nand Gate. 3. Opens The open is the other kind of fault that may aect the interconnections between two transistors. Let us consider the NAND gate of Figure 6(a); if there is an open between transistor T 3 and T 4, the pull-down network will never be active. Consequently, the gate output will result always stuck-at. Problems may arise for testing an open between the drains of T and T. If the input

21 pattern is (a; b) = (; ), the fault will not allow the load capacitance to be charged, thus the load capacitance will retain its previous value and the circuit will exhibit a sequential behaviour []. This means that two vectors are needed to test such a fault: the rst vector initializes the output, the second sensitizes the path between the faulty transistor and the output. However a two-vectors test pattern does not guarantee the testability of a stuck-open fault, since, as we will see later on, there are some physical factors such as timing skews, charge distribution, glitches, that may lead to test invalidation. The open may be modeled as a resistance and a capacitance in parallel [8]. Generally, a 5 K resistance is used to model the leakage currents. The capacity value depends on the size of the line break, on the line width and on the type of dielectric present in the break (air or silicon dioxide); anyway most of the breaks may be modeled by a capacitance falling in the range from?5 F to? F. 3.. Test Invalidation by Timing Skew A two-pattern test sequence may be invalidated if it is not correctly designed [9]. Let us consider the following non-redundant combinational function: F (w; x; y; z) = w x + wx + xy + yz Figure shows the two-level NAND-NAND implementation and the CMOS complex gate implementation of this function. Let us suppose that the p-network of the output NAND gate have a stuck-open fault aecting the interconnection between it and the NAND gate implementing the prime implicant xy. w x w w x y w x x y stuck open F x x y n-network z stuck open F y z (a) (b) Figure : Function F (w; x; y; z) = w x+wx+xy+yz: (a) Two-Level Nand-Nand Representation, (b) CMOS Complex Gate Representation. In order to detect this stuck-open fault we must operate on the prime xy. The only essential vertex of xy is wxyz, so this combination of input must belong to the testing sequence. In order to initialize the gate output we may choose a vertex belonging to the o-set of function F, say wxyz. Unfortunately, the test sequence we have chosen, i.e. (w; x; y; z) = f(; ; ; ); (; ; ; )g may be not able to detect the stuck-open fault considered due to circuit delays. In fact, during the transition from state (,,,) to state (,,,) the circuit may pass through one of the following spurious state: (,,,), or (,,,). In state (,,,) is active the prime wx, while in state (,,,) is active the prime w x, thus the delay caused by the stuck-open fault is masked by the switching of other gates. In order to make this fault detectable we have to choose initializations pattern whose Hamming's distance from the essential vertex that sensitizes the fault is. In this way it is guaranteed that always the desired gate will switch.

22 In our case study the sequence (w; x; y; z) = f(; ; ; ); (; ; ; )g, will detect the fault since the Hamming's distance between the two patterns is. Anyway, founding test patterns that avoid intermediate state and that are hazard free is computationally very expensive and is not always possible. An alternative approach consists in adding extra-transistors [9] in order to transform the test of a complex CMOS gate into that of pseudo-nmos or pseudo-pmos logic (see Figure 3). p-network Tp Cp in out n-network Tn Cn Figure 3: Design of Single Pattern Testable CMOS Gate. In complementary logic, if an input vector switches on the p-network, it will switch o the n-network and vice versa. Consequently, if we add two extra transistors, Tp and Tn, the former connected in parallel to the p-network, the latter in parallel with the n-network we will be able to test separately the p and n-network using only a single test pattern. Of course we have to add two extra control signal, Cp and Cn, one to activate Tp when testing the n-network, the other to activate Tn when testing the p-network. Transistors Tp and Tn must be accurately designed so that the resistance ratio be made similar to that between the depletion load and the n-network on-resistance in a NMOS gate. In practice a n = p ratio of =6 for Tp and Tn is the ideal. It is important to note that an inverter does not need any extra transistor, while a NAND gate only needs Tn and a NOR gate only needs Tp. Unfortunately, this technique, even if reduces test generation times, leads to a great area occupation due to the extra hardware and to a performance degradation, since the switching delay of the gate increase due to the two extra transistors. In [] single pattern testability has been achieved by using only one extra transistor but adding an extra control signal. 3.. Test Invalidation by Charge Distribution For very complex gates with a lot of internal nodes, charge sharing among the load capacitance and the parasitic capacitances of the internal nodes may lead to test invalidation []. When the second pattern sensitizes the stuck-open fault the gate output goes in a high impedance state, thus the gate retains its previous logic value. During the high impedance state the charge stored in the load capacitance is shared with the parasitic capacitances of the internal nodes of the faulty gate. As a consequence, this charge redistribution, may cause signicant output voltage swings if the number of internal nodes is high. If the charge remaining in the load capacitance is small, the output voltage may be indeterminate, so the next gate may fail to recognize the correct logic value and the fault may result undetectable.

23 3..3 Test Invalidation Due to Glitches Voltage glitches, also known as hazards, aects drastically the testability of a design [9]. Let us consider the boolean function F (x; y; z) = y + xz and let us suppose the circuit to have a n-transistor stuck-open, as shown in Figure 4(a). y x y stuck open z x F xy z z (a) F (b) Figure 4: Function F (x; y; z) = y + yz: (a) Transistor Level representation, (b) Karnaugh Map. In order to test for a stuck-open fault in the n-network we must apply two test patterns: the former to initialize the gate output to logical, the latter to sensitize the faulty transistor setting the output to logical. In case of a faulty p-transistor the initialization pattern should set the output to and the sensitization pattern should set the output to. Let us consider the Karnaugh Map of F (x; y; z), represented in Figure 4(b). From its analysis we may deduce that a robust test pattern for detecting the considered fault is the sequence (x; y; z) = f(; ; ); (; ; )g, since the Hamming's distance between the two pattern is and only one prime of F (x; y; z) is active. Anyway, if a glitch caused by a preceding gate occurs on input x, a low resistance conducting path between the output and V SS will be established for the entire duration of the glitch. Consequently, the stuck-open fault will be masked and the test sequence, in spite of its correctness, will fail to detect the fault Floating Gate A particular kind of open is the so called oating gate. This fault aects the polysilicon interconnections and, dierently from the other types of open faults is I DDQ testable. The testability by current monitoring, as we will see, depends on the equivalent capacitance of the break in the polysilicon. Figure 5 shows current and voltage response of a NAND gate whose input a is oating. The break capacitance is?5 F and the test patterns are those of Figure 6(b). The rst pattern initialize the output, the second one sensitizes the faulty transistor by establishing a low resistance conducting path between V DD and V SS ; in fact, although gate input a is logical, transistor T still conducts since its gate capacitance discharges through the n-network of the preceding gate very slowly, due to the polysilicon break. Also, Figure 6 shows current and voltage responses for a oating gate fault aecting transistor T. In this case the equivalent gate capacitance is? F. From Figure 6 we may deduce that, in this case, an I DDQ test would not be eective. Anyway, this is not contradictory with the simulation results of Figure 5. In general the smaller the break capacitance the more probably the fault is I DDQ testable. This is due to the fact that the smaller is the break capacity, the higher is its impedance, thus the charge stored in the gate of the faulty transistor, discharges through the n-network of the preceding logical gate with a very high time constant. As a consequence the faulty transistor conducts for a time greater than expected. 3

24 [ma] :4 :?:?:4?:6 : :4 :8 : :6 : (a) [V] : :4 :8 : :6 : (b) Figure 5: Nand with a Gate Floating and a Floating Gate Equivalent Capacity of?5 F: (a) Rail to Rail Current, (b) Output Voltage. :4 6 :3 5 4 [ma] : [V] 3 : : :4 :8 : :6 : (a) : :4 :8 : :6 : (b) Figure 6: Nand with a Gate Floating and a Floating Gate Equivalent Capacity of? F: (a) Rail to Rail Current, (b) Output Voltage. 4

25 A big break capacitance, on the other hand, makes the gate capacitance of the faulty transistor to be be charged slowlier. This means that the faulty transistor saturates slowlier and thus the gate switches slowlier than expected. As a consequence, this kind of fault may be easily detected by a delay test. 3.3 IDDQ Test Pattern Generation From the experiments performed in the previous sections we may deduce that in order to perform a supply current test of a gate we must establish a conducting path between V DD and V SS. In order to generate the test pattern we must take into account the switch level model of the circuit. The faulty p-transistor is excited by applying a logical to its input and a logical to the remaining ones. The faulty n-transistor is excited by applying a logical to its input and a logical to the remaining ones. If there are two or more paths in parallel, only one at time must be sensitized. This method is also applyable to circuits containing complex gates, while test generation methods based on logic gate cannot be applied since a complex gate is modeled as a network of elementary gates, say ANDs and ORs, hence cannot be generated a test vector for covering internal bridging faults. On the contrary a switch-level model provides all possible test vectors suitable for I DDQ testing. Since we have to examine all the possible paths between V DD and V SS, don't care must be eliminated during test generation. The adopted strategy consist in replacing a don't care to a logic gate input with a if the gate is a NOR, with a if the gate is a NAND. In [5] has been found that all single non-redundant bridging faults in a combinational circuit are detected by I DDQ testing. In [8] are resumed some interesting results about I DDQ testing: A test vector that detects a single bridging fault f i under I DDQ testing, also detects all multiple faults that contains f i ; a test set that detects all single PMOS stuck-on faults also detects all single line stuck-at faults; a test set that detects all single NMOS stuck-on faults also detects also detects all single line stuck-at faults; the testing strategy previously described permits to achieve the % bridging and stuck-on fault coverage under I DDQ testing. Consequently, a test a of all transistor stuck-on faults will also detect all line stuck-at fault of a static CMOS circuit Limitations of IDDQ Testing Although I DDQ testing may detect, as we have just seen, all the possible bridging and oating-gate faults that neither SCAN nor BIST techniques may be able to detect, there are some diculties that make current monitoring dicult. When a gate switches, a low resistance path between V DD and V SS is established and both the n-network and the p-network conduct. Because of the low resistance, the current ow from V DD to ground is large. If the transition is slow, the transient current will exist for a long time, so if the measurement is done before the transient settles down, a correct circuit may be marked as faulty by an I DDQ test. As a consequence, the current must be monitored only after the transient current has settled down. This is even more dicult in a complex circuit where many gates switch in succession and the transient may last up to a few microseconds. Thus a good fault-free current estimation [] is essential in order to perform a correct I DDQ test. If, under a certain test vector, n gates are expected to switch in succession, and if the gates average switching time is t avg, the pulse duration of the input signal must be much greater than 5