i N,R u TP Introduction Origins of Non-Ideal Operating Behavior

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1 Analysis of he Effecs of Non-Idealiies of Power Componens and Mains Volage Unbalance on he Operaing Behavior of a Three-Phase/Swich Bck-Type Uniy Power Facor PWM Recifier Marina Bamann Vienna Universiy of Technology Dep. of Elecrical Drives and Machines Gsshassrasse 25-29/E 372 A 1040 Vienna/Asria marina.bamann+e372@wien.ac.a Johann W. Kolar Swiss Federal Insie of Technology (ETH) Zrich Power Elecronic Sysems Laboraory Physiksrasse 3, ETH-Zenrm/ETL H22 CH 8092 Zrich/Swizerland kolar@lem.ee.ehz.ch Absrac According o he experimenal analysis of a 5kW wide inp volage range hree-phase hree-swich bck-derived niy power facor PWM recifier, he ideally consan DC op crren does show a low-freqency disorion for open-loop conrol operaion which is ranslaed ino low-freqency harmonics of he mains crren. This disorion canno be eliminaed compleely by closed-loop conrol since he conroller bandwidh has o be limied for sabiliy reasons and/or in order o avoid an exciaion of he LC inp filer. In his paper he parasiic effecs being responsible for he low-freqency disorions of DC op volage and/or crren are analyzed analyically and qanified for differen operaing condiions. Frhermore, he minimizaion of he inflence of he parasiic effecs by proper pre-conrol is discssed. All heoreical consideraions are confirmed by digial simlaions. I Inrodcion In [1] he experimenal analysis of a 5kW wide inp volage range niy power facor hree-phase bck+boos PWM recifier sysem [2],[3] wih hree-swich bck-ype inp sage and boos-ype op sage has been discssed. The invesigaion has shown clearly ha for open-loop operaion a low-freqency disorion of he ideally consan bck-sage op crren does occr, which does resl in a disorion of he crrens drawn from he mains (cf. Fig. 1). This effec canno be eliminaed compleely by an op crren conrol since he conroller bandwidh has o be limied for sabiliy reasons and/or in order o avoid an exciaion of he bck-sage LC inp filer which wold resl for ideally consan power operaion. Therefore, one has o clarify he origin of he non-ideal behavior in order o provide a proper pre-conrol or hardware adapion for improving he op and mains crren qaliy. i N,R TP i MEASUREMENT Sampling Insans Componen Tolerance A/D-Conversion Swiching Delays Condcion Volage Drops COMPONENTS FINITE SWITCHING FREQUENCY Crren Ripple Componen Tolerances SIGNAL PROCESSING Volage Ripple Unbalance MAINS PWM- Resolion Signal Processor Low Freqency Disorion NON- IDEAL BEHAVIOR Fig. 2: Origins of he non-ideal behavior of a hree-phase/hreeswich bck-ype PWM recifier sysem resling in AC- and DCside volage and crren disorion. In his paper he effec of an nbalance or of a low-freqency disorion of he mains phase volages, of he condcion volage drops of he power semicondcors, of he accracy and resolion of he signal processing, of he accracy of volage and crren measremen, and of he swiching delays of he power ransisors on he operaing behavior of he hree-phase hree-swich bck-ype inp sage of he recifier sysem is analyzed. A classificaion of all non-idealiies analyzed is shown in Fig. 2 in he form of a Fishbone-Diagram. In secion II he inflences of he differen non-idealiies on he operaing behavior are reaed analyically where always only a single non-idealiy is invesigaed and/or no mal ineracions of differen non-idealiies are considered. In secion III he absole vales of he effecs of he nonidealiies are given for raed op power, and are shown o be e.g. in he range of 0.1 V o a few vols for he bck-sage op volage and are comprising a DC componen and lowfreqency AC componens. Finally, in secion IV measres available for eliminaing he ndesired effecs are discssed wih reference o he experimenal se-p and resls of digial simlaions are shown. 0 II Origins of Non-Ideal Operaing Behavior Fig. 1: Time behavior of mains phase crren i N,R (5A/div.), of AC componens of he bck-sage op volage (5V/div), of he sysem op volage 0 (2.5V/div), and of he DC op crren i (2A/div) for open-loop operaion (op power: 1 kw, U 0 =400V,U N,l l =400V) In his secion he origins of he non-ideal saionary operaing behavior (cf. Fig. 2) of he hree-phase/swich bck PWM recifier sysem depiced in Fig. 3 are analyzed analyically. There, he behavior of bck-sage op volage and op crren i, and of he mains phase crrens i N,i, i = R, S, T is invesigaed, and formlas are given in order o be able o deermine he relevance of he differen effecs.

2 II.A Condcion Volage Drops of Power Semicondcors For achieving a resisive fndamenal mains behavior i N,i N,i, i = R, S, T, and for neglecing he fndamenal of he inp filer capacior crrens, i.e. for assming i N,i i U,(1),i, fndamenals of he disconinos recifier inp phase crrens i U,i lying in phase wih he corresponding mains phase volages N,i CF,i have o be formed by seing he relaive on-imes of he power ransisors S i, i = R, S, T, proporional o he insananeos vales of he mains phase volages [3]. Thereby, he bck-sage op crren 1 I is disribed sinsoidally o he mains phases and/or he bcksage op volage is formed by segmens of he mains phase-o-phase inp filer capacior volages. Wihinoneplseperiodherearewoaciveswiching saes, where crren is drawn from he mains, and one freewheeling sae 2, where he bck-sage op crren pah is via he free-wheeling diode D F. If we consider he inerval of he mains period where a relaion of he mains phase volages is given according o N,R > 0 > N,S > N,T, (1) heaciveswichingsaesarej = (110) and j = (101) 3. Wihin each acive swiching sae, here are for power diodes D (N),i and wo power ransisors S i involved in crren condcion, which is clearly shown in Fig. 3 for swiching sae j = (101). N,i ~ ~ ~ L F i CF,i C F i N,i D N,i S i D i CF,i i U,i Fig. 3: Srcre of he power circi of he bck-ype inp sage. The crren pah for swiching sae j =(101) is highlighed. The forward characerisic of he power diodes as known from he daa shee (cf. Fig. 1 in [4]) can be approximaed by V D,F = V F,0 + r D I, (2) where V F,0 =0.92 V and r D =10mΩ is valid. Analogosly, considering Fig. 2 in [5] he forward characerisic of he IG- BTs can be approximaed by V S,F = V CE,0 + r CE I (3) wih V CE,0 = 1.5V and r CE = 22.5mΩ. The series connecion of power diodes and power ransisors does case a volage drop redcing he insananeos vales of he bcksage op volage as compared o he ideal vale j = (101) : (101) = CF,RT 4V D,F 2V S,F, j = (110) : (110) = CF,RS 4V D,F 2V S,F, (4) j = (000) : (000) = V D,F. 1 In a firs sep he indcor crren can be assmed o be consan and impressed by he op indcor. 2 The characerizaion of he swiching sae of he bck recifier is given by he combinaion j =(s R s S s T ) of he phase swiching fncions. There, a phase swiching fncion s i does characerize he swiching sae of he corresponding power ransisors S i, i = R, S, T,wheres i = 0 denoes he off-sae, and s i = 1 denoes he on-sae. 3 Swiching sae j =(101) is eqal o swiching sae j =(111) wihin (1). I D F L Wih his, one receives wih he relaive on-imes δ j of he swiching saes for he local average vale (wihin one plse period) of he bck-sage op volage (ϕ U )= (101) δ (101) + (110) δ (110) + (000) δ (000) = (5) = 3 M ÛN,l l/2 [M (3 V D,F +2V S,F )cos(ϕ U )+V D,F ], {z } {z } ideal vale volage drop where M denoes he modlaion index of he bck inp sage being defined by he raio of he amplide of he mains phase crren o he bck-sage op crren, M = ÎN /I M [0; 1]. (6) The firs par of expression (5) denoes he ideal and consan vale of he bck-sage op volage, he second erm is de o he volage drops across he condcing power semicondcors which is ime-varying over he mains period de o he varying widh of he rn-on inervals. For he global average vale (wihin one mains period) of he non-ideal bck-sage op volage one receives Z +π/6 1 U = (ϕ U )dϕ U = (7) π/3 π/6 3 M h i Û N,l l 3 M = 2 π (2 VS,F +3VD,F )+VD,F. The AC-componen of he bck-sage op volage is showing he following harmonic specrm: X 6M(3V D,F +2V S,F ) (ϕ U ) U = cos(kϕ U )( 1) k/6 = (k + 1)(k 1)π k=6,12,.. = 6M(3V ³ D,F +2V S,F ) cos(6ϕ U ) + cos(12ϕ U )... (8) π The effecs of he condcion volage drops of he power semicondcors on he bck-sage op volage are he redcion of he global average vale in dependency on modlaion index and op power, and he generaion of a 6 h,12 h,... harmonic in he bck-sage op volage, leading o a corresponding op crren disorion for open loop operaion. This disorion is ranslaed ino he sysem inp crrens, where 5 h,7 h,11 h,13 h,... harmonics are generaed. II.B Disored Mains Volage The conrol algorihm of he hree-phase bck-ype recifier sysem is realized sch ha he local average vale of he DC op volage shows a consan vale over he mains period, i.e. consan power is drawn from he mains independen of he mains volage behavior. Assming ha he feeding mains conains low-freqency harmonics, e.g., a 5 h and 7 h harmonic, as resling from heavy loading by singlephase diode recifiers wih capaciive smoohing, he corresponding mains phase crren harmonics wih ordinal nmbers 5, 7, 11, 13...(which are no aenaed by he swiching freqency LC-inp filer) show significan amplides [6], [7]. In Fig. 4 his is confirmed by a digial simlaion employing CASPOC r [8], where a 5 h harmonic wih an amplide of 5% of he fndamenal volage was impressed. As a specrm analysis shows (cf. Fig. 4(b)), a prely DC bck-sage op volage and/or a prely DC op crren are resling, b he mains phase crrens do exhibi a significan 7 h harmonic. The amplide ÎN,(7) of he harmonic can be calclaed according o [7], Î N,(7) = 2 Û N,(5) P 0 = 2 2.5V 50V 9.8A =0.33A, (9) 3 ÛN,(1) 2 3 (50V) 2 which is in good agreemen wih he simlaion resl of 0.34 A.

3 which resls in a maximm percenage volage error of v err,adc =4/2048 = 0.2%. (11) For calclaing he relaive on-imes and for he digial conrol a signal processor wih 32-bi floaing poin arihmeic is employed, he resling error herefore can be negleced. The error resling from he PWM op resolion is dependen on he qarz oscillaor freqency f Q and/or on he precision of he coners realizing he PWM conrol as well as on he plse freqency f P (dring 1/f P acomplee swiching sae seqence is applied o he bck inp sage). Onereceivesforhewors-caseerror 50V 9.8A 50V 6.6A 0.5 Amplide / V,A V Bck Sage Op Volage DC Crren Mains Crren Mains Volage Nmber of Harmonics (a) (b) Fig. 4: Simlaion of he ime behavior of mains phase volages N,i, mains phase crrens i N,i, i = R, S, T, bck-sage op volage and DC crren i (a), and relaed specra (b) for nbalanced mains phase volages. Time scale: 2ms/div, volage scale: 10V/div, crren scale: 2.5A/div. II.C Inp Volage Measremen In order o incorporae he relevan volages and crrens ino he sysem conrol, a measremen circi employing differenial amplifiers is provided. The accracy of he signal measremen and/or level adapion is dependen on he olerance of he resisors, herefore, common-mode and differenialmode errors do occr. In Fig. 6 he signal adapion circi and he bandpass-filering for he inp filer capacior volages is depiced for phase R, N is an arificial neral poin whichisnoconnecedohemainsbformedbyheparallel connecion of C f and R f. For he adaped inp filer capacior volage one receives BP h C F,R N R 4 R 1 + R 2 = ( CF,R + N ) R i 2 RTP. (10) 200 R 3 + R 4 R 1 R 1 R HP If resisors wih a olerance of 0.1%areemployed,hemaximm (minimm) error afer signal adapion and bandpassfilering is ±0.7 % of he measred volage. Frhermore, a difference in he resisors R f and capaciors C f forming he arificial neral poin N cases an nbalance in he measred volages, which is inrodced ino he calclaion of he relaive on-imes of he power-ransisors resling in a disorion of he bck-sage op volage. In order o avoid his inflence, a zero seqence sysem of he measred inp volages is eliminaed mahemaically in he DSP-program. Therefore, a displacemen of he arificial neral poin does no case a bck-sage op volage disorion. II.D Signal Processing The conrol of a 5 kw prooype of he hree-phase bck+ boos PWM recifier sysem is realized sing a 32-bi floaing poin digial signal processor ADSP SHARC (Analog Devices [9]) [10]. The analog signals are adaped (cf. secion II.C) and digiized by 12-bi A/D converers of ype AD (Analog Devices [11]) having an analog inp range of ±2.5 V. The posiive (negaive) fll-scale error is ±4 LSB, v err,p W M = 2 3 f P Û N,l l. (12) f Q In his case a 12 MHz oscillaor and a 8-bi coner are employed, resling in a plse freqency of f P =23.4kHz and/or in v err,p W M = ÛN,l l. II.E Swiching Delay The swiching ime errors resl from signal delays of he gae drive nis and from rn-on or rn-off delay imes of he power ransisors. The experimenal invesigaion shows, ha a oal rn-on delay ime of d,on 380 ns and a oal rn-off delay-ime of d,of F 470 ns does occr in he case a hand. In Fig. 5 he ideal swiching signals s i and he swiching signals inclding he delay imes as well as he ime behavior of he bck-sage op volage are given for a plse period T P wihin mains inerval (1). The difference of he rn-on and rn-off delay imes resls in a disorion of he local average vale of he bck-sage op volage. The disorion shows a maximm absole vale of v err,d = d,of F d,on 3 Û N,l l, (13) T P /2 resling in v err,d = ÛN,l l for he given sysem parameers. Frhermore, his local disorion resls in lowfreqen componens of he bck-sage op volage and in a disorion of he mains phase crrens. The disorion is depending on he relaive difference beween rn-on and rn-off delay ime in relaion o one plse period, δ d =( d,of F d,on )/T P. (14) In he following, he bck-sage op volage specrm is given for 1. eqal delay imes for all hree bridge legs, and for 2. adelayimebeingpresenonlyforonepowerransisor, while he oher power ransisors are assmed o show no delay imes. s R s S s T CF,RT d,off CF,RS d,on 0 T P /2 T P Fig. 5: Swiching signals, swiching delay imes and resling ime behavior of he bck-sage op volage wihin one plse period T P valid for mains inerval (1). The volage-ime inegral errors are shown in grey (ligh gray: posiive error, dark gray: negaive error).

4 R C F, R C f N N R 1 R f R 3 R 4 R 2 CF,R 200 C HP R HP C TP R TP BP CF, R 200 Fig. 6: Signal adapion and bandpass-filering of he inp filer capacior volages shown for phase R, N is an arificial neral poin no conneced o he mains. The resling bck-sage op volage specrm for he firs case resls in (ϕ U )= 6 δ ÛN,l l π 3MÛN,l l (15) 2 h 1 2 cos(6ϕ U ) cos(12ϕ U ) cos(18ϕ i U )..., for he second case one receives 3M Û N,l l (ϕ U )= (16) 2 h 4 δ ÛN,l l 1 π 4 + cos(2ϕ U ) + cos(4ϕ U ) cos(6ϕ i U ) The bck-sage op volage harmonics do case low-freqen harmonics in he op power which are direcly ransferred o he mains side (if he recifier power losses are negleced, he inp power eqals he op power), hence he mains phase crrens are disored in a way ha he plsaion of he power does resl. There, he harmonic componens are depending on he behavior of he mains phase volages, frhermore he harmonics conen will be differen for mains phases R, S, T in he second case (delay ime of only one powerransisororimedelayofonepowerransisorbeing significanly larger han for he oher power ransisors), i.e. he AC side crrens will conain posiive and negaive phase-seqence sysems. E.g. one receives for a 3 rd harmonic componen I N,(3) = Î + N,(3) e3 (ω+ϕ+ 3 ) + Î N,(3) e 3 (ω+ϕ 3 ). (17) Moreover, an error in he bck-sage op volage resling from he differen raes of rise of he forward volage dv/d a rn-on and rn-off does occr, which is dependen on mains phase volage rms vale and on he poin in ime considered wihin he mains period. mains volages (e.g., 5 h,7 h ) shold no be aenaed by he bandpass filer in order o ensre a correc calclaion of he on-imes of he power ransisors (cf. secion II.B) and/or o garanee a consan bck-sage op volage (and/or preven low-freqency power componens). II.G Finie Swiching Freqency De o he finie swiching freqency ripple componens in he inp and op qaniies do resl. As menioned, he inflence of he ripple componens on measremen and hence on conrol can be eliminaed by proper signal sampling and filering. B, he ripple componens are ransferred from he AC side o he DC side and vice versa. II.G.1 Inp Filer Capacior Volage Ripple As Fig. 7(b) shows, he inp filer capacior volage ripple is sperimposed on he bck-sage op volage, whereby adifference in he insananeos vales and an excess or a defici in he volage-ime inegral wihin one plse half period occrs. If a swiching sae seqence is provided which shows a symmeric arrangemen of he swiching saes wihin each plse period, he aforemenioned excess and defici is balanced o in he sbseqen plse half period [12]. Therefore, he local and global average vale of he bck-sage op volage is no inflenced by he inp filer capacior volage ripple. II.G.2 Bck-Sage Op Crren Ripple The DC ripple appears in he disconinos recifier inp crrens i U,i and does case an excess or a defici in he crren-ime-inegral which is balanced o in he sbseqen plse half period (if a symmeric swiching paern is employed) (cf. secion II.G.1). For small vales of he bck-sage op crren (i.e. small op volage U 0 and/or high load resisance R 0 )he PWM recifier does ener ino disconinos condcion mode (DCM)wherehecrreninheDCsideindcoriszerofor a par of he plse period. Therefore, he behavior of he crren ripple changes and a 6 h harmonic does occr in he bck-sage op crren. The harmonic is ransferred o he mains, b he crren-ime inegral is sill zero wihin oneplseperiod. Inorderoavoidheoperaioninhedisconinos condcion mode, he boos op sage can be acivaed, whereby he average vale of he DC crren is shifed o higher vales. DCM herefore will no be considered frher in his paper. II.F Signal Sampling For conrolling he bck+boos PWM recifier sysem, he bck-sage op crren i and he inp filer capacior volages CF,i are sampled wice per plse period (sampling freqency: khz). In order o avoid an inflence of he signal ripple componens on he sampled vales, he sampling insans are placed a he beginning of each plse half period. There, he insananeos vales of DC crren i() and of inp filer capacior volage CF,i() are eqal o he local average vales i and BP C F,i, respecively (cf. Fig. 7). However, ime-delays in he measremen se-p do case a sligh ime displacemen of he sampling insans, hence he ripple componens are no exclded enirely. Therefore, a low-pass filer for he DC crren and a band-pass filer for he inp filer capacior volage (mid-freqency: 50 Hz, cf. Fig. 6) are employed which eliminae he ripple componens prior o sampling. Remark: For designing he bandpass filer one shold ake ino accon ha he low-freqency harmonics of he CF 0 T P /2 T P ideal C F, RT C F, RS sampling insans (a) CF 0 T P /2 T P BP C F, RT C F, RT C F, RS Fig. 7: Behavior of he bck-sage op volage: (a) ideal behavior and (b) behavior nder consideraion of he inp filer capacior volage ripple, valid for a mains phase inerval (1). (b)

5 Case Effec Remark Condcion Volage Drops 0.61 V Peak-o-peak vale of AC componens in he bck-sage op volage 0.25 V Amplide of he 6 h harmonic of he bck-sage op volage 5.4 V Redcion of he average vale of he bck-sage op volage Disored Mains 0V No inflence on he bck-sage op volage for low-freqen harmonics in he mains Measremen 2.7 V Measremen of inp filer capacior volages employing 0.1% resisors (wors case) Signal Processing 0.78 V 12-bi A/D conversion (wors case) 0V 32-bi floaing poin signal processing negligible effecs 4.6 V 12 MHz PWM signal op (wors case) Swiching Delays 5.0 V Gae drive ni delay ime + rn-on and rn-off delay imes (wors case) 0.04 V Amplide of he 6 h harmonic of he bck-sage op volage for 1% addiional swiching delay of he power ransisors in all bridge legs Signal Sampling 0V Lowpass-filering and bandpass-filering negligible effecs Finie Swiching Freqency 0V No inflence of ripple componens on average vales Crren Commaion 0V No inflence de o addiional overlap- imes Tab. 1: Comparison of he differen effecs casing non-ideal sysem behavior for a raed op power of P 0 =5kWaU N,l l =480V and U 0 = 400 V. Significan parasiic effecs are shown in bold face, negligible effecs resling in no inflence are marked wih 0V. II.H Crren Commaion For convenional hree-phase (six-swich) crren sorce inverers overlap-imes have o be provided for swiching he power ransisors in order o ensre a coninos crren flow in he DC-link indcor. These overlap-imes do affec he mains phase crrens and he DC-link crren harmonics [13]. However, for he hree-phase/hree-swich bck recifier here is no need for overlap-imes, since he commaion of he DC crren is always well defined by he phase-o-phase inp filer capacior volages. If one considers, e.g., he ransiion from swiching sae j = (110) in j = (111) in inerval (1), he crren has o be commaed from bridge leg S o bridge leg T. This is simply realized by rning on he power ransisor in bridge leg T, de o he volage condiion a he bck-sage inp side CF,RT > CF,RS he crren is immediaely commaed from bridge leg S o bridge leg T (neglecing he gae drive delay ime and he power ransisor rn-on delay ime). Hence, no inflence on he mains volage/crren or on he bck-sage op volage/crren is cased by he commaion. Bck-Sage Op Volage Error / V DC Componen (Swiching Delay) PWM P = 5 kw P = 1 kw Measremen DC Componen (Power Semicondcors) 12-bi A/D Conversion 6 h Harmonic (Power Semicondcors) P = 5 kw P = 1 kw DC Op Volage / V (b) 6 h Harmonic (Swiching Delay) (a) Fig. 8: Comparison of bck-sage op volage errors for op power levels in he range of P 0 =(5...1)kW in seps of 1 kw and for differen op volage levels U 0 =( ) V. (a): Errors in he range of a few 100 mv, and (b) errors in he rage of a few Vols. III Magnides of Op Volage Disorions In Tab. 1 he parasiic effecs discssed in secion II are smmarized and magnides are given for raed op volage P 0 = 5kW, U N,l l = 480V, and U 0 = 400V in order o provide a qanificaion of he differen effecs. Frhermore, he main effecs are depiced for differen op volages and op power levels in Fig. 8 which allows o idenify which effec is dominan or negligible a differen operaing condiions 4. IV Discssion In his secion, he parasiic effecs considered in secion II are discssed concerning he amon of inflence on he recifier op behavior based on Fig. 8, and possibiliies for compensaing he non-ideal behavior are given. Frhermore, he analyical resls are confirmed by digial simlaions. IV.A Negligible Non-Idealiies The non-idealiies of he inp volage measremen (cf. secion II.C) can be negleced since he given errors are wors case vales. In pracice componen olerances are more evenly disribed, whereby he given errors are redced. Frhermore, errors de o A/D-conversion (cf. secion II.D) show a negligibly small magnide and can herefore be negleced. Thesameisreforheharmonicscasedbyhedifference of he rn-off and rn-on delay imes (cf. secion II.E). IV.B Condcion Volage Drops In Fig. 9 he simlaed ime behavior of he bck-sage op volage and nder consideraion of semicondcor condcion losses (cf. secion II.A) is depiced for an op volage reference vale U0 = 50 V, a load resisance R 0 =5Ω, and a mains line-line volage U N,l l =60V. Themajoreffec of he semicondcor volage drops is a consan DC volage error of 5 V, which can be easily compensaed also by a low dynamics op crren conroller. The low-freqency componen of he resling bck-sage op volage cold be avoided by implemening a proper pre-conrol algorihm adjsing he bck-sage op volage reference vale in dependency on he acal posiion of he respecive plse period wihin he mains period, and on he mains volage and load condiions. There, vales for forward volage and 4 For low op volage and high op power he op crren wold exceed he raed vale, i.e. differen power semicondcors wold have o be employed, whereby he given dependencies wold be changed.

6 Fig. 9: Time behavior of he average vale of he low-pass filered bck-sage op volage TP and of he DC crren i for a given op volage reference vale U0. on-resisance of he power semicondcors have o be known wih good accracy and, frhermore, he dependency of he forward characerisics on he jncion emperare has o be aken ino accon. Neverheless, a redcion of he lowfreqency harmonics in bck-sage op volage and/or op crren of abo 50% cold be achieved. IV.C Time Resolion of he PWM Op Signals The errors de o he finie ime resolion of he PWM signal ops do show significan amon, b cold be considered o be evenly disribed, i.e. he acal error will be below he given vales. Neverheless, he effecs canno be negleced; he resolion cold be increased by employing a qarz oscillaor wih wo or hree imes he acal freqency which wold decrease he maximm error by he facor of 1 2 or 1 3 for nchanged plse freqency (which has o be generaed by an addiional freqency divider). IV.D Swiching Delays The main par of he inflence of he swiching delays is a redcion of he bck-sage op volage by a consan DC volage, which can be conrolled o zero. The harmonic componens do show a negligible inflence and can herefore be negleced in he case a hand (swiching freqency of 24 khz). However, if he swiching freqency is se o a sbsanially larger vale, e.g. 50 khz, he effec of swiching delays is linearly increased and canno be negleced any more. A way of eliminaing he inflence of swiching delays is he implemenaion of a cycle-by-cycle conrol [14], [15] or of a charge conrol [16] which allows o direcly conrol he acal local average vale of he DC op volage and crren. V Conclsions In his paper differen origins for he non-ideal behavior of a hree-phase/swich bck-ype PWM recifier sysem in openloop operaion are deermined, classified andanalyzedana- lyically. There, effecs de o signal processing and a finie swiching freqency, on-sae and swiching characerisics of power semicondcors, mains phase nbalance and measremen errors are aken ino accon. In order o ge a clear ndersanding and qanificaion of he varios effecs, ypical vales are calclaed for differen operaing poins. As a comparaive evalaion shows, he dominan parasiic inflences are de o he power semicondcor volage drops, de o he ime resolion of he PWM signal ops, and de o he rn-on and rn-off delay ime of he power ransisors. Parially, hese effecs do resl in a consan redcion of he bck-sage op volage and can herefore be eliminaed by closed-loop conrol. However, he low-freqency componens resling from he non-ideal behavior canno be flly eliminaed by he sysem conrol de o limied conrol bandwidh. Hence, he effecs have o be sppressed by proper pre-conrol mehods and/or hardware adapaion, e.g. byincreasingheimeresolionofhepwmsage. For verifying he parasiic effecs experimenally proper measremen eqipmen, i.e. differenial probes and an oscilloscope wih sfficien high resolion is reqired. Frhermore, by employing an analog power amplifier for generaing he hree-phase inp volage effecs resling from volage disorions of he feeding mains can be enirely exclded for he sysem invesigaion. Frhermore, he behavior of he recifier sysem can hen be analyzed for a defined lowfreqen harmonic disorion of he inp volage. The experimenal analysis will be described in a fre paper. References [1] Bamann, M., and Kolar, J. W.: Experimenal Analysis of a 5kW Wide Inp Volage Range Three-Phase Bck+Boos Power Facor Correcor. Proceedings of he 23rd IEEE Inernaional Telecommnicaions Energy Conference, Edinbrgh, U.K., Oc , pp (2001). [2] Kolar, J. W.: Nezrückwirkngsarmes Dreiphasen-Sromzwischenkreis-Plsgleichrichersysem mi weiem Sellbereich der Asgangsspannng. Asrian Paen Applicaion A9/2000, filed: Jan. 5, [3] Bamann, M., Drofenik, U., and Kolar, J. W.: New Wide Inp Volage Range Three-Phase Uniy Power Facor Recifier Formed by Inegraion of a Three-Swich Bck- DerivedFron-EndandaDC/DCBoosConvererOp Sage. Proceedings of he 22nd IEEE Inernaional Telecommnicaions Energy Conference, Phoenix, Arizona, U.S.A., Sep , pp (2000). [4] Inersil Corporaion: Ulrafas Diode RURG Daa shee (2000). [5] Inernaional Recifier: Warp Speed IGBT IRG4PF50W. Daa shee (1998). [6] Kolar, J. W., and Sn, J.: Three-Phase Power Facor Correcion Technology. Torial Workbook of he 32nd IEEE Power Elecronics Specialiss Conference, Seminars 1 & 4, Vancover, Canada, Jne (2001). [7] Egger, B.: Rückwirkngen des idealen Nezplssromrichers am realen Nez. ETG-Fachberich 72 (in German), ETG-Fachagng, Bad Naheim, Germany, May (1998). [8] CASPOC - Power Elecronics and Elecrical Drives Modeling and Simlaion. [9] Analog Devices: ADSP-2106x SHARC DSP Microcomper Family; ADSP / ADSP 21061L. Daa shee, Rev.B, U.S.A. (2000). [10] Moraf, G.: Signalprozessorregelng eines neen Dreiphasen-Plsgleichrichersysems mi weiem Eingangsspannngsbereich (VIENNA Recifier IV). Diploma Thesis (in German), Vienna Universiy of Technology, Dep. of Elecrical Drives and Machines, Vienna, Asria (2001). [11] Analog Devices: 12-Bi 600kSPS Analog-Digial Converer AD7892. Daa shee (2000). [12] Bamann, M., and Kolar, J. W.: Comparaive Evalaion of Modlaion Mehods for a Three-Phase/Swich Bck Power Facor Correcor Concerning he Inp Capacior Volage Ripple. Proceedings of he 32nd IEEE Power Elecronics Specialiss Conference, Vancover, Canada, Jne 17 21, pp (2001). [13] Halkosaari, T., Ksela, K., and Tsa, H.: Effec of Non-Idealiies on he Performance of he 3-Phase Crren Sorce PWM Converer. Proceedings of he 32nd IEEE Power Elecronics Specialiss Conference, Vancover, Canada, Jne 17 21, pp (2001). [14] Smedley, K.M., and Ck, S.: One-cycle conrol of swiching converers. Proceedings of he 22nd Power Elecronics Specialiss Conference, Boson, Massachses, U.S.A., Jne 24 27, pp (1991). [15] Cadros, C., Chandrasekaran, S., Wang, K., Boroyevich, D., and Lee, F.C.: Modeling an Comparison of Two Modified Vecor Modlaion Schemes wih Fee-Forward for he Qasi-Single Sage Three-Phase Zero-Volage Zero- Crren Swiched Bck Recifier. Proceedings of he 7h Eropean Conference on Power Elecronics and Applicaions, Lasanne,Swizerland,Sep.7 9(1999). [16] Wang, K., Boroyevich, D., and Lee, F.C.: Charge Conrol of Three-Phase Bck PWM Recifiers. Proceedings of he 15h Applied Power Elecronics Conference, New Orleans, Loisiana, U.S.A., Febr. 6 10, pp (2000).