High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

Transcription

1 Journal of VLS Signal Processing,, * Springer Science + Business Media, LLC. Manufacured in The Neherlands. D:./s--9- High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip G. A. RUZ, J. A. MCHELL AND A. BURÓN Deparameno de Elecrónica y Compuadores, Faculad de Ciencias, Universidad de Canabria, Avda. de Los Casros s/n, 9, Sanander, Spain Received: June ; Revised: June ; Acceped: May Absrac. This paper presens a -D DCT/DCT processor chip for high daa rae image processing and video coding. uses a fully pipelined row column decomposiion mehod based on wo -D DCT processors and a ranspose buffer based on D-ype flip-flops wih a double serial inpu/oupu daa-flow. The proposed archiecure allows he main processing elemens and arihmeic unis o operae in parallel a half he frequency of he daa inpu rae. The main characerisics are: high hroughpu, parallel processing, reduced inernal sorage, and maximum efficiency in compuaional elemens. The processor has been implemened using sandard cell design mehodology in. mm CMS echnology. measures. mm (he core is mm ) and conains a oal of. k gaes. The maximum frequency is MHz wih a laency of cycles for -D DCT and 8 cycles for -D DCT. The compuing ime of a block is close o 8 ns. has been designed o mees he demands of EEE Sd.,8,99 used in differen video codecs. The good performance in he compuing speed and hardware cos indicae ha his processor is suiable for HDTV applicaions. Keywords: discree cosine ransform (DCT), inverse discree cosine ransform (DCT), image compression, row column decomposiion, parallel pipelined archiecures, very large scale inegraion (VLS). nroducion This work was suppored by he Spanish Minisry of Science and Technology (TC-89). The Discree Cosine Transform (DCT) is widely considered o provide a near opimal performance for ransform coding and image compression, because i offers energy compacion, orhogonal separabiliy and fas algorihms []. Thus, he DCT has been applied for mos of recen sill picure and moving picure inernaional sandards for sequenial codecs [, ] as JPEG, MPEG, H. and H., as well as in highdefiniion elevision (HDTV) sysems. The compuaion complexiy requiremens in many real-ime applicaions ofen lead o he use of efficien dedicaed hardware (ASC_s) operaing a high speed wih an accepable cos in area. Since he inroducion of he DCT in he 9s, a considerable amoun of research has been performed on algorihms, archiecures and processor design for compuing of DCT. n he lieraure, here are many VLS implemenaions proposed for DCT and is inverse (DCT) which, o a greaer or lesser exen, search for some of he following characerisics: lowcos area [ 9], regulariy o reduce he design effor [, ], high hroughpu [,, 9, ] and low power [,, ]. Differen approaches have been proposed o implemen he -D DCT/DCT: row column decomposiion mehod, he direc mehod and

2 Ruiz e al. oher minoriy alernaives based on ransforms(as DFT [] and DHT []), CRDC algorihms [8] and sysolic array implemenaions [9]. The row column decomposiion mehod uses he separabiliy propery of -D DCT o be broken ino wo sequenial -D DCT, one along he row-wise block and he second along he column-wise block of previous row-wise processed blocks, which are sored in a ranspose memory [,, 8, 9,,, ]. This mehod allows a -D DCT o be compued using fas algorihms and hardware developed for -D DCT. n some implemenaions, a single muliplexer -D DCT processor is used o perform boh operaions wih he corresponding saving in hardware [8,, ]. Roughly 9% of he survey implemenaions follow he row column decomposiion mehod because is regulariy is highly suiable for VLS implemenaion. The direc mehod requires fewer compuaions, bu i incurs he irregulariy [,, ]. However, he feaure of lowcompuaion complexiy is sill aracive and some regular srucures have been researched recenly. This paper describes he archiecure of an 88 -D DCT/DCT processor chip wih a high hroughpu and a cos-effecive archiecure []. The D DCT/DCT is calculaed using he separabiliy propery, so ha is archiecure is made up of wo -D processors and a ranspose buffer (TB) as inermediae memory. This ranspose buffer presens a regular srucure based on D-ype flip-flops wih a double serial inpu/oupu daa-flow highly suiable for pipeline archiecures. The processor has been designed searching for high hroughpu, reduced hardware, parallel and pipeline archiecure, and a maximum efficiency in all arihmeic elemens. This archiecure allows he processing elemens and arihmeic unis o work in parallel a half he frequency of he daa inpu rae, excep for he normalisaion of he ransform which is carried ou in a muliplier operaing a maximum frequency. Moreover, i has been verified ha he precision analysis of he proposed processor mees he demands of EEE Sd.,8,99 [] used in video codecs TU-T H. [], TU-T H. [] y TU-T H.+ []. The processor has been conceived using a sandard cell design mehodology and manufacured in a.-mm CMS CSD M/P. V process (hp:// ausriamicrosysems.com). has an area of. mm (he core is mm ) and conains a oal of. k gaes,.8 k gaes of which are flip-flops. A daa inpu rae frequency of MHz has been esablished wih a laency of cycles for -D DCT and 8 cycles for -D DCT. The compuing ime of a block is close o 8 ns. This good performance in he compuing speed as well as hardware cos, indicae ha he proposed design is compac and suiable for HDTV applicaions. The paper is organized as follows: Secion presens he principles and algorihm used o implemen he -D DCT/DCT. Secion addresses he archiecural design and circui design feaures of he basic processing elemens. A descripion of a block diagram of he -D DCT/DCT processor is presened in Secion. Secion describes he main arihmeic elemens and, finally, chip characerisics and comparisons wih oher previous DCT/DCT processors are described in Secion.. Two-Dimensional 88 DCT/DCT La 88 DCT ransforms a block of he space domain, fxn; ð mþg n;m¼, ino is DCT domain componens, fxk; ð lþ, according o he following equaion: Xk; ð l g k;l¼ X X Þ ¼ ck ðþ cl ðþ n¼ m¼ 8k; l ¼ ; ; ;...; xn; ð m ÞCn; ð kþcm; ð lþ; ðþ where cðþ ¼ p ffiffi, c(k)= for k>, Ci; ð jþ ¼ cos iþ j The DCT is defined by: xn; ð mþ ¼ X X k¼ l¼ ck ðþ cl ðþ Xk; ð lþcn; ð kþcm; ð lþ; ðþ k; l ¼ ; ; ;...; n marix noaion, le S R8 he eigh-poin DCT marix wih rows reordered according o he sequence (,,,,,,,): C C C C C C C C C C C C C C C C C C C C C C C C S R8 ¼ C C C C C C C C C C C C C C C C ðþ C C C C C C C C C C C C C C C C C C C C C C C C

3 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip where C ¼ p ffiffi ; C i ¼ cos i ; i ¼ ; ;...;. Taking ino accoun he properies of he cosine, he C, C, C and C elemens of S R8 can be expressed as: C ¼ C ðc þ C Þ; C ¼ C ðc þ C Þ; C ¼ C ðc C Þ; C ¼ C ðc C Þ; ðþ The elemens of columns,, and of S R8 can be decomposed by applying Eq. () in he following way: S R8 ¼ P R8J R8 ¼ P R8 where ¼ P R8 J RE J R J SE Q R J B J C J D Q R8 Q R8 P R8 ¼ Diagonal ð C ; C ; C ; C ; C ; C ; C ; C Þ J SE ¼ T ; T Q R ¼ D D J B ¼ T T T T J C ¼ ; C J D ¼ C C C Q R8 ¼ D D ; ðþ ðþ ðþ ð8þ ð9þ where D is he marix resuling from permuing he rows according o he ordering sequence (,,,), D ordering according o (,), T =C /C, T =C /C and T =C /C. Figure shows he flow graph of Eq. (), frequenly referenced as Chen_s fas algorihm [] which has been used in some implemenaions [, ]. involves muliplicaion by four differen consans and he oupus are scaled which require a furher muliplicaion. Moreover, J R8 is made up by wo sub-marices which can be compued in parallel. Since S R8, Q R8 and P R8 are orhogonal, afer Eqs. () and () we ge: S R8 ¼ J R8 P Q R J SE R8 ¼ Q R8 J D J C JB P R8 ðþ The flow char of inverse DCT is shown in Fig.. n he compue of his algorihm, he role of he inpus and oupus are reversed and he J RE and J R mus be replaced by J RE and J R ; respecively. The 88 -D DCT can be expressed on he basis of he nuclei of he S R8 marix ransform as: X R ¼ S R8xS R8 ¼ K 8 J R8xJ R8 ðþ where (P) represen he Hadamard produc and K 8 is he normalizaion marix defined as C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C K 8 ¼ C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Similarly, he 88 DCT is obained as: ðþ x ¼ S R8X RS R8 ¼ JR8 ðk 8 XR ÞJ R8 ðþ Eqs. () and () allow he muliplicaion by K 8 coefficiens o be done a oupu for forward DCT or a inpu for DCT, reducing he number of inner muliplicaions. This scheme is very aracive when his ransform is incorporaed ino he decoding

4 Ruiz e al. x QR JSE / X x x x T T - / C / C / X X X x x x x C C - - T T T T - - C / C / C / C / X X X X QR8 JD JC JB Figure. Signal flow graph of -D forward DCT. process in an adapive ransform coding sysem. Therefore, he quanizaion process a he receiver or a he ransmier can include his normalizaion in he decoding/encoding lookup able. n his case, he normalizaion can be compleely eliminaed and hus a significan reducion in hardware is obained.. Archiecure of J R8 J R8 Processor Figure shows he archiecure of he J R8 J R8 processor designed o implemen he marix decomposiions defined in Eqs. () and () respecively. is made up of a double-inpu Q R8 processor, and he processors Q R j J SE J SE and J D j J C j J B J B operaing in parallel. The configuraion of forward DCT or DCT of he archiecure is performed by means of he conrol of he muliplexers and of he operaion of processors J SE J SE and J B J B. ne imporan characerisic is ha he inpu daa E and are processed in parallel and hus he oupu daa E and are also generaed in parallel. n his way, he operaion frequency of he J R8 J R8 processor is reduced o f s /, where f s is he inpu daa sampling frequency. Figure shows he archiecure of each of he basic processors specified in Fig. which are derived from Eqs. () (). The conrol is very simple and is carried ou using four signals: Clk, main clock a frequency f s, Clk, inernal clock a frequency f s /, and he muliplexer selecion signals S a frequency f s / and S a X / J SE Q R x X X X / C / C / - T T x x x X X X X C / C / C / C / T T T T J B J E - C J D C Q R8 x x x x Figure. Signal flow graph of -D inverse DCT.

5 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip Figure. Archiecure of J R8 J R8 processor. frequency f s /8. All of he basic processors have been conceived o work wih four inpu daa inroduced in series and whose four oupu daa are hus also in series, hese oupus being compaible wih he nex processor. The Forward/nverse (F/) signal modifies he operaion of he processor o perform he ransformaion or is inverse. These basic processors are made up of shif regisers (S-R), muliplexers (MUX), carry incremener adders/subracers and hardwired mulipliers and hey have been designed aiming a an efficiency of % in he arihmeic elemens in mos cases D DCT/DCT The -D 88 DCT/DCT is implemened by he row column decomposiion echnique according o Eq. () for DCT and o Eq. () for DCT. Figure shows he block diagram of he proposed archiecure composed of wo -D processors (J R8 J R8 ), a ranspose buffer (TB) for soring he inermediae daa, one down-sampling (D-S) uni and anoher upsampling (U-S) uni, and a muliplier for performing he normalizaion of he ransform according o marix K 8 described in Eq. (). ne of he main characerisics of his archiecure is ha i operaes a half he frequency of he inpu daa rae (f s /), excep for normalizaion wih K 8 performed a he oupu for he forward DCT and a he inpu for he DCT. This muli-rae operaion involves D-S and U-S modules: D-S muliplexes in parallel and a frequency f s / he inpu daa, while he U-S performs he opposie process... Archiecure of TB The 88 inermediae daa generaed by he firs -D DCT processor has o be sored and ransposed in he TB before he second -D DCT is performed. This TB allows simulaneous read and wrie operaions beween he wo processors while performing marix ransposiion. To achieve his, he daa are read ou of he memory column-wise if he previous inermediae daa were wrien ino he memory row-wise, and vice versa. The TB based on D-ype flip-flops has been found o be adequae for pipeline archiecures, unlike oher proposed archiecures based on RAM memories. The schema of his circui is shown in Fig. a. has a regular serial inpu/oupu srucure made up of eigh -bi shif-regisers and muliplexers. The conrol signals are: R/C, which selecs he inpu of shif-regisers o sore daa in row-wise (R/C=) or column-wise (R/C=), W j (j= o 8), which selecs he jh shif-regiser o make a wrie operaion, and R k (k= o ), which selecs he jh shif-regiser specified by W j o read ou he daa. The wrie & read operaion is simulaneously made wih wo serial inpu daa, { } and { }, and generaes wo serial oupu daa in parallel, { } and { }. The conrol signals allow he daa o be sored alernaively row-wise and column-wise in order o perform daa ransposing and o avoid loss of daa. For he sake of clariy, Fig. b and c show he configuraion of shif-regisers and he arrangemen of sored inpu daa when a wriing process in column-wise or in row-wise is made. Boh soring daa processes are easy o configure from he sae of he TB conrol signals. Figure d shows he iming diagram of he sae of hese variables as a funcion of he number of Clk clock cycles. Firs, he inpu daa are sored column-wise (in Fig. b, hey are filled downward) o complee each of he verical halves which he memory is divided. To do his, W j recurs sequenially o each of he shif-regisers so ha only four Clk cycles are required o sore a whole row. A he same ime as he oupus, he daa previously sored column-wise are read ou. To do

6 Ruiz e al. a a a a Clk S-R + A A A A MUX MUX B b b b b B B B S-R Clk - Clk d d d d Clk F/ S-R MUX MUX Clk x /T + Clk D D D D a) b) d d d d Clk MUX Clk S-R S-R + x C MUX D D D D d d d d Clk S-R MUX + D D D D Clk MUX Clk Clk c) d) x d d d d Clk S-R F/ T/T D D D D MUX Clk + Clk e) Figure. Archiecure of basic processors: a Q R8, b J SE J SE, c J D, d Q R and J D, and e J B J B. NP DCT DCT D-S J Transpose R8 K JR8 U-S 8 J Buffer K 8 R8 JR8 DCT DCT DCT D CT fs fs/ fs UT Figure. Block diagram of -D 88 DCT/DCT processor.

7 W8 W W W RRR RRR W R/C R/ C R/C W W W Clk Wj Qj+ Qi -bi cell a) b) c) Figure. TB circui: a Schemaic, b wriing daa in row-wise, c wriing daa in column-wise, and d iming diagram in erm of number of Clk cycles. High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip

8 8 Ruiz e al. Clk W W W W W W W W 8 R R R Figure (Coninued). (R/C=) Wriing in row-wise (R/C=) Wriing in column-wise x{ x{ x{ x{ x{ x{ x{ x{ 8x d) his, he wriing process, performed using W j, and he reading process, performed using R k, are synchronized. n he nex block, he inpu daa are sored column-wise (in Fig. c, hey are filled righward) and he oupus now read ou he daa previously sored row-wise. n his case, he daa are wrien sequenially in each of he horizonal halves ino which he memory is divided, repeaing eigh imes he sequence specified in Fig. d. As a resul, he oupus are coninuously ransposed in parallel and Clk cycles are required o fill up all of he memory... Pipeline Scheme The DCT/DCT processor uses a pipelining scheme o shoren he cycle ime and perform real-ime processing for applicaions wih high pixel raes. The pipeline regisers are insered in he criical pah o improve he operaion speed wih minimal overhead. Figure shows he daa cycle iming for calculaing he wo -D DCT/DCT and TB ransposing operaions for he differen blocks. The inpu daa are fed in row-wise order a pixel/clock and he oupu daa are produced in column-wise order. The firs -D DCT requires cycles and he -D DCT cycles, since normalizaion is necessary. The second -D DCT requires cycles and he -D DCT cycles. The oal laency for -D DCT is cycles and for -D DCT is 8 cycles. This small difference in he number of cycles is due o he synchronizaion beween he differen processors of he circui. npu TB (wrie) TB(read) upu DCT DCT Block # Block # -D DCT/DCT Block # Block # Transposing Block # 9 8 Block # Block # Block # -D DCT/DCT 8 Block # Cycles Time Figure. Daa iming of -D DCT/DCT processor.

9 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip 9 Table. Compuaion precision of DCT according o sandard []. MSE (<.) ME (<.) PMSE (<.) PME (<.) [j, ] [, j]....9 [j, ] [, j] [j, ] [, j]..8.. MSE verall mean square error, ME overall mean error, PMSE peak mean square error, PME peak mean error.. Accuracy Specificaions The accuracy of he compuing of he DCT is an imporan characerisic of his hardware. The DCT kernel componens are real numbers so ha runcaion or rounding errors are ineviably inroduced during compuaion. There are wo inheren errors in a DCT implemenaion: () finie inernal wordlengh and () coefficien quanizaion error. The sandards H., H. and H.+ defined for videoconference applicaions, esablishes he accuracy specificaions in he compuing of he DCT. The fulfilmen of he specificaions ensures he compaibiliy beween differen implemenaions of he DCT [8]. This sandard has been used o define he accuracy of he daa-pah and wordlengh of he coefficiens of he processor. A Table summarizes he simulaion resuls carried ou wih MATLAB according o he procedure described in []. This specificaion allows he errors caused by finie wordlengh in DCT o be evaluaed. Thus, he DCT archiecure mus be excied wih, 88 blocks of random numbers in he ranges [j, ], [j, ] and [j, ]. The simulaions find he following minimum archiecural requiremens: -b for daa-pah, -b for coefficiens wordlengh and -b for normalizaion coefficiens of K 8.. Arihmeic Circuis The arihmeic circuis limi he speed of he processor. They have been carefully seleced o find B -b CA S A B A B A B A B C FA S C C FA S FA S C HA S C C -bi CA S S S S Figure 8. -b CA deailed for -b.

10 Ruiz e al. d j d i CARRY SAVE {T, T, C, C, } n A n B A n:n-9 B n:n-9 REGSTER A n- B n- n- n- C C n- DCA Clk C Clk A n-: CG B n-: FNAL ADDER WTH RUNDNG CRRECTN P i Figure 9. General srucure of hardwired mulipliers. bes compromise in area, hroughpu and laency. The J R8 J R8 processor uses a oal of six -bi carry incremener adders and hree hardwired mulipliers. n he design of hese circuis, fas archiecures wih minimal overhead, radix represenaion and pipeline sages have been used o provide balanced criical pahs. However, his does no mean a grea effor in design since hese operae a half he frequency of he inpu daa rae. nly a fine grain pipeline archiecure is required for he normalizaion muliplier K 8 since i is operaing a inpu daa rae frequency. n his secion, he main arihmeic circuis are described... Carry ncremener Adder The carry incremener adder (CA) has been chosen because i has p ffiffi an asympoic performance wih (n) area and ( n ) ime, and provides a compromise beween a ripple-carry adder (RCA) and a carry look-ahead adder. has a shor criical pah a he expense of a small increase in area in comparison wih RCA. The CA is made up of an RCA divided ino blocks and some addiional selecion logic and i is a modificaion of he adder presened in [9]. Figure 8 shows he -bi CA buil from five blocks of differen lenghs {,,,, }. For he sake of clariy, a -bi block is shown in deail, is oupu being obained from he following equaions: S ¼ C S S ¼ C S S S ¼ C S S S S ¼ C S S S S ðþ where S i is he RCA oupu and C he inpu carry for his block. The oupu carry, which forms he inpu carry for he nex block, is defined as: C ¼ C þ S S S S C.. Hardwired Mulipliers ðþ The concep of hardwired muliplicaion and binary signed digi represenaion for fixed coefficiens has been adoped o simplify he hardware complexiy for realizing muliplicaion hrough a carry-saver adder scheme. The muliplicaion by fixed-coefficiens is compued in hree ypes of configurable mulipliers which perform he following arihmeic operaions: P=d i {T or T }+d j, P=d i { or T }+d j and P=d i C, where d i and d j are inpu daa. These mulipliers, whose general srucure is shown in Fig.

11 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip A B DCA C C P A B A B A B A B C C FA FA P P FA P HA P C C i i C i C i C + + -bi DCA P P P P Figure. Srucure of DCA deailed for -bi. 9, are made up of a carry save adder ree based on : and : compressors and configured according o he ype of coefficien, and a final adder wih rounding correcion. To limi he criical pah, pipeline sages and a radix-8 encoding are used for T and T. The fixed coefficiens are expressed in he carry save srucure as: T ¼ 8 9 ¼ :9899 ¼ þ 8 T ¼ 9 ¼ :98 ¼ 8 þ C ¼ 89 9 ¼ : ¼ þ þ þ þ 8 T ¼ 9 9 ¼ : ¼ þ þ þ ðþ These mulipliers generae a larger oupu han he daa-pah of he processor. This necessarily implies he use of less significaive bis o adap he oupu of he muliplier o he -bi size of he daa-pah. However, i has been verified hrough simulaion wih MATLAB ha if a rounding correcion operaion raher han a runcaion operaion is performed on his final adder, he size of he daa-pah required o verify he EEE Sd.,8,99 requiremens is reduced from -b o -b. This resul is imporan because i leads o a significan saving in he oal area of he processor. The final adder wih rounding correcion is made up of a carry generaor (CG) wih a srucure of a high-speed binary carry-look ahead [], and a -bi double carry incremener adder (DCA). The DCA mus compue he inpu carries, C and C, which indicae he ype of increase o be made: + for C =C =,+ for C = and C =, and + for C = and C =. C y C can easily be generaed from he following expressions: For example, P=x T +y=(x) j +(x) j8 jx j +y. The erm x is precompued by adding and shifing operaions, x+x, in a CA. C ¼ A n þ B n þ C n C ¼ A n B n C n where C nj is he carry generaed in he CG. ðþ

12 Ruiz e al. Table. Disribuion in erms of number of gaes for he differen blocks in D DCT processor., } deailed for he case of -bis. The oupus, P i, of his block are given by he following expressions: Block No. of gaes Q R8 processor 9 Q R processor 8 J C processor J B J B processor J SE J SE processor J D processor TB, K 8 muliplier,8 hers, Toal, P ¼ C C P P ¼ C i þ C i P P P ¼ C i P þ C i P P P P ¼ C i P P þ C i P P P P and he oupu carries are defined as: C ¼ C þ P P P P Ci C ¼ P P P C Ci.. Normalizaion Muliplier ð8þ ð9þ Figure shows he schema of he -b DCA composed of five blocks of variable lengh {,,, The Hadamard produc for he normalizaion described by Eqs. () and () are performed in a Booh-muliplier wih fine pipeline. The muliplier is Table. Comparison beween he proposed archiecure and exising archiecures which verify he sandard []. Ref. Year Funcion Tech. CMS Area in mm Gaes/Trans. Frequency/laency Archiecure [] 99 DCT/DCT.8 mm (FC) (core) k Tr. V/.8ms RC TRAM DA [] 99 DCT mm (GA) k gaes V/ cycles MUXRC ERAM HM [] 99 DCT/DCT.8 mm (FC) (core) k Tr. MHz MUXRC TRAM HM [] 99 DCT/DCT. mm (FC) K Tr V/ cycles RC TRAM DA [] 998 DCT. mm (GA) k Tr V/8 cycles RC TRAM HM [] 999 DCT. mm (SC). (core) k gaes/8 k Tr V/8 cycles DM TB DA [] 999 DCT/DCT.8 mm (SC) K gaes + RAM MHz RC TRAM DA [] 999 DCT/DCT. mm (SC) k gaes + RAM MHz RC TRAM DA [] DCT/DCT. mm (SC).8 (core). k gaes + RAM MHz/,8 cycles DM TRAM DA [8] DCT/DCT. mm (SC) 9. k gaes MHz MUXRC TB DA [] DCT/DCT.8 mm (SC) 8 k gaes. V/ cycles RC TRAM DA [9] DCT. mm (SC) (core). gaes + RAM MHz MUXRC TRAM HM [] DCT/DCT. mm (SC). (core) k gaes MHz/ cycles RC RF HM urs DCT/DCT.mm (SC) (core). k gaes V /8 cycles RC TB HM FC Full-cusom, SC semi-cusom, GA gae-array, RC row column decomposiion, MUXRC muliplexed row column decomposiion, DM direc mehod, TRAM ranspose RAM, ERAM exernal ranspose RAM, TB ranspose, RF regiser file, HM hardwired muliplier, DA disribued arihmeic.

13 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip made up of an opimised Booh-decoder, a sevensage pipeline carry-save srucure and a pipeline final adder wih rounding correcion based on a DCA and a GC. The couner selecs a specific elemen of K 8 and he Booh-decoder encodes he differen elemens of normalizaion which are defined in -b as: C C =,88/8,9, C C =,/ 8,9, C C =,8/8,9, C C =,/8,9, C C =,99/8,9, C C =,/8,9, C C =,/ 8,9, C C =,9/8,9, C C =,8/8,9 and C C =,9/8,9. This encoding has been opimized looking for common sharing erms of hese fixed-coefficiens in order of save area. This muliplier conains,8 cells of which are flip-flops. has a laency of Clk clock cycles.. mplemenaion and Comparisons A prooype of an 88 -D DCT processor chip has been designed using sandard cells in a semi-cusom mehodology. uses 9-b inpu daa and -b oupu daa for DCT and -b and 9-b for DCT. The processor was implemened wih a. mm CMS CSD M/P. V echnology of Ausria-Microsysem (hp:// The chip has an area of..$. mm (he core is..$. mm ). conains a oal of. k gaes,.8 k gaes of which are flip-flops and 8 gaes are FA/HA. Table shows he hardware cos in erms of number of gaes for he differen blocks of his processor. More deails abou chip implemenaion can be found in []. A maximum operaing frequency of abou MHz has been esablished. The laency for -D DCT is Clk cycles and for -D DCT is 8 Clk cycles. The compuing ime of a block is close o 8 ns. n he lieraure, here are many implemenaion syles for DCT and DCT. For proposes of comparison, Table liss feaures of he proposed processor and oher DCT implemenaions seleced from among hose which fulfil he specificaions of he EEE sandard. This Table shows he following parameers: year of publicaion, funcion indicaing wheher i implemens he forward DCT and he DCT or only he DCT, echnology (all are in CMS) and design mehodology (FC for full-cusom, SC for semicusom, GA for Gae Array), area in mm of die or of core, complexiy in erms of number of gaes or ransisors (some designs include addiional RAM), frequency and laency, and finally, some basic specificaions of he archiecure. Three parameers have been aken ino accoun in he specificaion of he archiecure []: mplemenaion based on row column decomposiion mehod or direc mehod. n he firs case, he propery of separabiliy of he D DCT is used o separae is compuaion ino wo sequenial -D DCT (RC) and ranspose memory, or ino a single -D DCT (MUXRC) processor which performs boh operaions. n he second case, he direc formula of he D DCT is used. Table shows clearly ha he RC or MUXRC implemenaion is superior o he direc mehod. Memory. The implemenaion of he la DCT requires inermediae memory which, in mos cases, is a RAM, eiher exernal, ERAM, or inernal, TRAM. her alernaives are he regiser file (RF) configuraion based on flip-flops or ranspose buffer (TB). Compuaion based on hardwired mulipliers (HM) or on disribued arihmeic (DA). As compared wih he exising design lised in Table, he proposed processor is clearly superior in erms of speed even for hose processors ha use a beer echnology [, ]. The parallel-pipeline archiecure and arihmeic unis operaing a half he frequency gives an inpu daa rae of MHz, far higher han ha of he fases processor lised in his able []. This speed does no imply any addiional cos in erms of he number of gaes since i is similar o ha of he oher designs proposed which offer an efficien hardware complexiy [,, 8, 9,, ]. Thus, [9,, ] use he MUXRC approach o reduce hardware, [, 9] implemen only he DCT and ohers presen he same complexiy in number of gaes bu require addiional RAM []. n his respec, noice should be aken in paricular of he highly area-efficien processor described in []

14 Ruiz e al. which combines a sofware-oriened conroller wih a hardware uni. This processor is no a pure hardwareoriened approach unlike he res of he processors.. Conclusions This paper describes he archiecure of an 88 -D DCT/DCT processor chip wih high hroughpu, reduced hardware, parallel and pipeline archiecure operaing a half he frequency of inpu daa rae, and a maximum efficiency in all arihmeic elemens. This processor is clearly superior in erms of speed wihou increasing hardware complexiy in comparison wih ohers processors which also mee he demands of EEE Sd.,8,99. This good performance in he compuing speed as well as hardware cos, indicae ha he proposed design is suiable for HDTV applicaions. ne advanage of he proposed archiecure is ha he K 8 normalizaion can be incorporaed ino he decoding process in an adapive ransform coding sysem. Therefore, he quanizaion process a he receiver or a he ransmier can include his normalizaion. Then, he K 8 muliplier can be compleely removed in he D DCT processor, reducing area by % and laency by %. References. K. R. Rao and P. Yip, BDiscree Cosine Transform: Algorihms, Advanages and Applicaions,^ Boson/San Diego/ New York/London/Sydney/Tokyo/Torono: Academic, 99.. V. Bhaskaran and K. Konsaninides, Bmage and Video Compression Sandards: Algorihms and Archiecures,^ Boson/Dordrech/London: Kluwer, nd Ediion, 99.. K. R. Rao and J. J. Hwang, BTechniques and Sandards for mage Video and Audio Coding,^ New Jersey: Prenice Hall PTR, 99.. T. Kuroda, T. Fujia, S. Mia, T. Nagamasu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Muroa, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, BA.9-V, MHz, -mw, mm, -D Discree Cosine Transform Core Processor wih Variable Threshold-volage (VT) Scheme,^ EEE J. Solidsae Circuis, vol., no., 99, pp. 9.. T. H. Chen, BA Cos-effecive 88 -D DCT Core Processor wih Folded Archiecure,^ EEE Trans. Consum. Elecron., vol., no., 999, pp K. Kim, J. J. Cha, and H. J. Cho, BA Design of -D DCT/ DCT for Real-ime Video Applicaions,^ h n. Conf. on VLS and CAD, 999, pp. 9.. T. S. Chang, C. S. Kung, and C. W. Jen, BA Simple Processor Core Design for DCT/DCT,^ EEE Trans. Circuis Sys. Video Technol., vol., no.,, pp. 9, April. 8. Dae-Won-Kim, Taek-Won-Kwon, Jung-Min-Seo, Jae-Kun-Yu, Suk-Kyu-Lee, and Jung-Hee-Suk, BA Compaible DCT/DCT Archiecure Using Hardwired Disribued Arihmeic,^ EEE n. Symp. Circuis Sys. Proc., vol.,, pp.. 9. J.. Guo and J. C. Yen, BAn Efficien DCT Processor Design for HDTV Applicaions,^ J. VLS Signal Process., vol.,, pp... Y. P. Lee, T. H. Chen, L. G. Chen, M. J. Chen, and C. W. Ku, BA Cos-effecive Archiecure for 88 Two Dimensional DCT/DCT using Direc Mehod,^ EEE Trans. Circuis Sys. Video Technol., vol., no., 99, pp. 9.. D. Gong, Y. He, and Z. Cao, BNew Cos-efecive VLS mplemenaion of a -D Discree Cosine Transform and is nverse,^ EEE Trans. Circuis Sys. Video Technol., vol., no.,, pp... S.. Uramoo, Y. noue, A. Takabaae, J. Takeda, Y. Yamashia, H. Terane, and M. Yoshimoo, BA MHz -D Discree Cosine Transform Core Processor,^ EEE J. Solidsae Circuis, vol., no., 99, pp A. Madisei and A. N. Willson, BA MHz -D 88 DCT/ DCT Processor for HDTV Applicaions,^ EEE Trans. Circuis Sys. Video Technol., vol., no., 99, pp. 8.. R. Rambaldi, A. Uguzzoni, and R. Guerrieri, BA mw. V Gae Array 88 DCT for Video Technology,^ Proc. CASSP, vol., 998, pp L. Fanucci and S. Saponara, BDaa Driven VLS Compuaion for Low Power DCT-based Video Coding,^ 9h EEE n. Conf. on Elecronics-Circuis-and-Sysems, vol.,, pp... B. D. Tseng and W. C. Miller, Bn he Compuing he Discree Cosine Transform,^ EEE Trans. Compu., vol. C-, no., 98, pp H. Malvar, BFas Compuaion of Discree Cosine Transform Through Fas Harley Transform,^ Elecron. Le., vol., no., 98, pp.. 8. S. Yu and E. E. Swarzlander, BA Scaled DCT Archiecure wih he CRDC Algorihm,^ EEE Trans. Signal Process., vol., no.,, pp.. 9. Y. T. Chang and C. L. Wang, BA New Fas DCT Algorihm and is Sysolic VLS mplemenaion,^ EEE Trans. Circuis Sys., Analog Digi. Signal Process., vol., no., 99, pp P. A. Ruez, P. Tong, D. Bailey, A. D. Luhi, and P. H. Ang, BA High-performance Full-moion Video Compression Chip Se,^ EEE Trans. Circuis Sys. Video Technol., vol., no., 99, pp... L. Fanucci, R. Salei, and F. Vavala, BA Low-complexiy -D Discree Cosine Transform Processor for Mulimedia Applicaions,^ 999, pp. 9.. G. A. Ruiz, J. A. Michell, and A. M. Burón, BParallel-pipeline D DCT/DCT Processor Archiecure,^ SPE Symp. on Microechnologies for he New Millennium, pp. 8, May.. BEEE Sandard Specificaions for he mplemenaions of 88 nverse Discree Cosine Transform,^ nsiue of Elecrical and Elecronics Engineers, New York, March 99.

15 High Throughpu Parallel-Pipeline -D DCT/DCT Processor Chip. Video Codec for Audio-Visual Services a px kbis/s, TU-T H., 99.. TU-T recommendaion H.. Video Coding for Low Bi- Rae Communicaion, 99.. TU-T recommendaion H.+, Jan., 999, Draf.. W. Chen, C. H. Smih, and S. Fralick, BA Fas Compuaion Algorihm for he Discree Cosine Transform,^ EEE Trans. Commun., vol., 9, pp S. Kim and W. Sung, Bpimum Wordlengh Deerminaion of 88 DCT Archiecures Conforming o he EEE Sandard Specificaions,^ Conference Record of The 9h Asilomar Conference on Signals, Sysems and Compuers, vol., 99, pp T. Y. Chang and M. J. Hsiao, BCarry-selec Adder Using Single Ripple-carry Adder,^ Elecron. Le., vol., no., 998, pp... R. P. Bren and H. T. Kung, BA Regular Layou for Parallel Adders,^ EEE Trans. Compu., vol. C-, no., 98, pp... G. S. Taylor and G. M. Blair, BHigh Design for he Discree Cosine Transform in VLS,^ EE Proc. Compu. Digi. Tech., vol., no., 998, pp., March. Juan A. Michell was born in Cáceres, Spain, in 9. He received he M.S. and he Ph.D. degrees in physical sciences from he Universiy of Canabria, Spain, in 9 and 9, respecively. Since 9 he has been wih he Deparmen of Elecronics and Compuers a he Universiy of Canabria, where he was appoined Professor in Elecronics in 99. His curren research ineress are VLS archiecures and inegraed circui design for digial signal processing applicaions. Gusavo A. Ruiz was born in Burgos, Spain, in 9. He received he M.Sc. degree in physics in 98 from he Universiy of Navarra, Spain, and he Ph.D. degree in physical science in 989 from he Universiy of Canabria, Sanander, Spain. Since 98, he has been wih he Deparmen of Elecronics and Compuers a he Universiy of Canabria, where he is currenly an Associae Professor. His curren research ineress are mainly focused on VLS archiecures for signal processing and high-speed arihmeic circuis. Angel M. Burón was born in Co rdoba, Spain, in 98. He received he M.S. and he Ph.D. degrees in physical sciences from he Universiy of Sevilla, Spain, in 99 and 9, respecively. Since 9 he has been wih he Deparmen of Elecronics and Compuers a he Universiy of Canabria, where he was appoined Professor in Elecronics in 98. His curren research ineress are inegraed circui design and VLS/ULS archiecures for digial signal processing.