Outline Single Cycle Processor Design Multi cycle Processor. Pipelined Processor Design. Overall clock period. Analyzing performance 3/18/2015

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1 3/8/5 Pipelined Processor Design. Sahu CSE, T Guwahai Please be updaed wih hp://ainga.iig.erne.in/~asahu/c/ Ouline Single Cycle Processor Design Muli cycle Processor Merging M and, emoving dder and dder Synchronized : nroducing Mux and egiser Pipelined Processor (Daa Pah) Pipeline : nroducion and Performance Cos Hazards and emoval nalyzing performance Componens Delay egiser dder LU MUX nsrucion ory Daa ory m Bi manipulaion or Overall :, SW :, M max LW :, M Beq :,, J :, max M nalyzing performance Componens Delay Example egiser ns dder ns LU 5ns MUX ns 3ns nsrucion 6ns ory Daa ory m 6ns Bi manipulaion ns NS SW LW Beq J Delay 7ns ns 3ns ns 6ns Problems wih single cycle design Slowes rucion pulls down he frequency esource uilizaion is poor There are some rucions which are impossible o be implemened in his manner bi more complex NST Floaing poinnst

2 3/8/5 Clock in single cycle design class Muli cycle Processor 7 Clock in muli cycle design class Muli cycle Timing nalysis ssume Cycle ime 6 ns Given a Program wih N nsr NS MX : 6%, LW %, SW %, BEQ=5%, J=5% =, LW=5, SW=, BEQ= or 3, J= Compared o Single Cycle Design Cycle ime 3ns (Max ime of all ypes) Time o execue Single Cycle : 3*N = 3 N Muli Cycle: No benefis in erm of ime N* 6*(.6*.*5.*.5*.5.5*) = N*6(...5.5)=N*6*3.975= 3.85N mproving resource uilizaion Merging M & : muli cycle design Can we eliminae wo ders? How o share (or reuse) a resource (say LU) in differen cycles? class Sore resuls in regisers. Of course, more muliplexing may be required! esources in his design:, LU, MEM. M ge used in s Cycle Dm ge used in h Cycle Why o keep wo separae ory?

3 3/8/5 emoving Firsdder: muli cycle design emoving nd dder: muli cycle design class class DDE ge used in s Cycle LU ge used in 3 rd Cycle Why o keep boh LU and DDE? DDE ge used in nd Cycle LU ge used in 3 rd Cycle GN Why o keep boh LU and DDE? Muli cycle Daa Pah dd eg & Mux : Mulicycle Daa Pah [5 ] 8 [3 8] a[3 ] [5 ] 8 a[3 ] [5 ] r rd [ 6] r [5 ] [5 ] 6 LU [5 ] [ 6] [5 ] D [5 ] r rd r 6 B [3 8] 3 LU es 6 Pipe Pipeline Pipelined Processor Pipeline 3

3/8/5 Car ssembly Pipeline Car ssembly Pipeline Single Cycle Poor esource Uilizaion, TC >= long nsr

Decoding NS i you can Fech NS i Pipeline Pipeline Design nsrucion Pipeline Time or Cycle 3 5 6 7 8 NS NS

Cycle Clock T nsrucion Pipeline Time To Execue N nsrucion : Toal Time= T*N*5 Toal Time= T*(N) No Pipeline

J=5% =, LW=5, SW=, BEQ= or 3, J= Pipeline Every nsrucion is 5 cycle bu pipelined manner deal Condiion

4 3/8/5 Car ssembly Pipeline Car ssembly Pipeline Single Cycle Poor esource Uilizaion, TC >= long nsr laency Muli Cycle TC > Longer Sage, Beer Uilizaion, Sill performance need o improve using pipeline When Decoding NS i you can Fech NS i Pipeline Pipeline Design nsrucion Pipeline Time or Cycle NS NS NS 3 NS NS 5 ll he Sages work in parallel, No resource can be shared by sages Performance: rucion per Cycle Clock T nsrucion Pipeline Time To Execue N nsrucion : Toal Time= T*N*5 Toal Time= T*(N) No Pipeline Pipeline 3 Performance ssume Cycle ime 6 ns Given a Program wih N nsr NS MX : 6%, LW %, SW %, BEQ=5%, J=5% =, LW=5, SW=, BEQ= or 3, J= Pipeline Every nsrucion is 5 cycle bu pipelined manner deal Condiion Time o execue Single Cycle : 3*N = 3 N Muli Cycle: N*6*(.6*.*5.*.5*.5.5*) = N*6(...5.5)=N*6*3.975= 3.85N Pipelined : N cycles

5 3/8/5 Single cycle daapah (absrac) Pipelined daapah F D EX F/D D/EX EX/ / M r rd LU M r w rd rd LU Don share resources in Sages Pu back muliplexers n Muli Cycle Design LU used for and Offsedding Used for sdder and nd dder egiser FLE is used in nd and h Cycle n Pipeline Use Separae resource sdder, nd dder & LU egiser FLE is accesses s Half of nd Cycle and nd Half of h Cycle F D EX M F/D D/EX EX/ / W r r rd LU 7 Correcion for sage F D EX F/D D/EX EX/ / bsrac: dding conrol conrol ol M r r rd W LU M r r rd crl LU 5

6 3/8/5 Conrol signals wih delays Correcion for wrie signal conrol ol conrol ol M r r rd W crl LU M r r rd crl LU Correcion for wrie signal Degree of overlap conrol ol Serial Pipelined M r r rd crl LU Overlapped Super Pipelined Pipeline Deph Shallow Superscalar Pipeline: Penium Single Pipeline Deep Pipeline Pipeline Pipeline3 Fech 3 rucions Decode 3 rucions Execue 3 nsrucions 36 6

7 3/8/5 Difficulies in Pipeline Hazards in Pipelining esource conflics => Srucural hazards use of same resource in differen sages Daa dependencies => Daa hazards W (re afer wrie) W (wrie afer re) WW (wrie afer wrie) Procedural dependencies => Conrol hazards condiional and uncondiional branches, calls/reurns Srucural Hazards Srucural Hazards Caused by esource Conflics Use of a hardware resource in more han one cycle Differen sequences of resource usage by differen rucions B C B C B C D B C C B D Non pipelined muli cycle resources F D X X F D X X Pipeline wih Shared esources Used LU for : Mulicycle Daa Pah F/D D/EX EX/ / [5 ] 8 a[3 ] [5 ] [ 6] [5 ] D [5 ] r rd r 6 B [3 8] 3 LU es 7

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IF ID EX MEM WB 400 ps 225 ps 350 ps 450 ps 300 ps CSE 30321 Computer Architecture I Fall 2011 Homework 06 Pipelined Processors 75 points Assigned: November 1, 2011 Due: November 8, 2011 PLEASE DO THE ASSIGNMENT ON THIS HANDOUT!!! Problem 1: (15 points)