I LSB I MSB. x N 1 x N 2 I OUT. The switches are controlled by the input bits, x i. the least significant bit, LSB, and the corresponding current

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1 A STATEGY FO IMPLEMENTING DYNAMIC ELEMENT MATCHING IN CUENT-STEEING S Niklas U. Andersson and J. Jaco Wikner Microelectronics esearch Center, Ericsson Components AB, SE-64 8 Kista, Sweden Department of Electrical Engineering, Linköping University, SE Linköping, Sweden {niklasa, jacow}@isy.liu.se ABSTACT Interesting comparisons of dynamic element matching, DEM, techniques, have een presented during the last decade. However, not many chip implementations of these DEM techniques have een presented so far. A rief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PDEM, technique in a 3.3-V supply, 4-it CMOS current-steering wideand digitalto-analog converter,. I. INTODUCTION Data converters are important uilding locks in telecommunication systems, where the requirements on speed and resolution are high. The design of high resolution, wideand digital-to-analog converters, s, is hard, since they often suffer from significant conversion noise and non-linearities introduced y non-ideal circuit ehavior and inaccuracy in farication. In fact, the distortion introduced y the non-idealities in the may limit the achievale resolution of the overall telecommunication system. Although we design our converter carefully, mismatch errors etween internal reference levels will occur due to irregularities in the processing of the chip []. Within the signal and, these mismatch errors are most likely dominating the non-ideal ehavior and setting the achievale spurious-free dynamic range, SFD. We can however prepare our converter to e ale to reduce or simply change the nature of these errors. This is done dynamically, hence the input signal or circuit elements are manipulated using digital circuitry to modify the influence of the errors. This is referred to as dynamic element matching, DEM, techniques [2-6]. Distortion terms, hence signal-dependent errors, are modified to ecome signal-independent noise. Therefore, using DEM, we try to maximize the SFD. The DEM techniques differ in complexity and trade-offs etween performance and hardware complexity usually have to e done to meet the required specification. For high-speed applications, the current-steering structure [8, 9] is a suitale candidate and therefore it is chosen for a test chip which uses a DEM technique. The current-steering with its different properties is descried in Sec. II. Most common DEM techniques require a certain amount of oversampling which is discussed in Sec. III. In Sec. IV. and Sec. V. we present an overview and simulation results of some of the different DEM techniques and how these apply to the. In Sec. VI. we present an implementation of the PDEM in a 3.3-V CMOS 4-it current-steering D/A converter. II. CUENT-STEEING We choose to implement the as a current-steering since they show to e very fast and are herey well suited for wideand applications. There is no direct need for operational amplifiers and feedack loops. The general structure of a inary weighted current-steering is shown in Fig. elow. V ref I MSB I LSB x N x N 2 x I OUT Figure. A inary weighted, current-steering structure. The switches are controlled y the input its, x i, where i =, 2,...,N, and N is the numer of its. x is the least significant it, LSB, and the corresponding current source has the nominal value I LSB. The source controlled y it x i, i.e., the i-th LSB current source, has a strength of 2 i I LSB, hence the most significant it, MSB, current source therefore has the nominal value I MSB = 2 N I LSB. The output, I OUT, is terminated with a load resistance and it is given y Kirchhoff s current law

2 I OUT ( X) = I LSB X () where X is the digital input given y N X = 2 k x k (2) k = Unfortunately the current-steering s are rather sensitive to device mismatch, finite output impedance, and glitching [8, 9, ]. The matching errors arise due to the inaccuracy during the chip processing. To improve local matching of the current weights, unit current sources are used to form the current weights []. Hence for the i -th LSB we use 2 i LSB current sources (unit current sources) in parallel. For improved gloal matching, special layout techniques are needed [9]. In a CMOS implementation the unit current source can e implemented y a single-cascoded PMOS transistor (Fig. 2). The switches are generally implemented with NMOS transistors for high speed. I OUT V ias V cascode Figure 2. A single-cascoded PMOS unit current source. M M2 I OUT The linearity of the converter is also partially determined y the output impedance [] (which has to e as high as possile) since there will e a current division etween the load impedance and the output impedance. The cascode transistor M2 is therefore used to increase the output impedance of the current source. Using only the source transistor M we would have the equivalent output resistance r out = (3) g ds, This is not large enough to achieve high resolution [] and therefore y including the cascode transistor M2 we get the output resistance g m, 2 r out = (4) g ds, 2 g ds, Which is approximately times larger than in Eq. (3). In order to further increase the output resistance, even more cascode transistors could e used to the cost of a larger voltage drop over the current source which would decrease the output swing. Glitches arise due to the mismatch etween switching time instants of different its [8]. For short periods of time, wrong codes will e generated yielding large current spikes. To reduce the glitch error power it is common to use so called segmented structures, where a numer of the most significant its are thermometer coded or similar techniques [8-]. Our expectation is that the DEM technique, Sec. IV., will suppress a large amount of the mismatch errors so that the advantages of a current-steering can e utilized in a larger extent. III. OVESAMPLING AND INTEPOLATING S The output signal of the is pulse amplitude modulated through the hold functions of the current switches and the output spectrum is sinc weighted. Therefore an analog, continuous-time, filter is used to remove images. If the converter is used at Nyquist rate, the transition and of the analog filter has to e very sharp which implies a high filter order. By increasing the sample frequency through interpolation of the input signal we can allow a much wider transition and of the analog filter and hence lower filter order. We also move some of the dynamic errors to out-of-and frequencies. Ideally, we do not gain in resolution through interpolation. We can however use intentional oversampling, hence we andlimit our input signal in advance. We define the oversampling ratio, OS, as f s OS (5) 2 f where the signal andwidth is f and f s is the sampling frequency. The original input resolution of N its can e reached with an N -it converter ( N < N ) if the OS is large enough. The lower resolution contains a lower numer of current sources and chip area and other design complexities can e reduced. The signal-to-noise ratio, SN, assuming a full-scale sinusoid input, is SN 6 N logos (6) where we find that y increasing the OS y a factor two we gain 3 db in SN, or equivalently.5 it. Note that the maximum true resolution still is given y N. A 4- it converter can e realized y using a -it converter with OS = 2 8 = 256. Still a high-performance -it current-steering converter is hard to design and we have to use an even higher OS. This is however not feasile for wideand applications. Therefore, we also apply a noise shaping technique. The truncation noise introduced y the lower-resolution, N -it is spectrally shaped to out-of-and frequencies which are not used due to the oversampling. This shaping is generated with a so-called Σ modulator. The modulator high pass filters the trun-

3 cation noise and low pass (or all pass) filters the signal. Higher-order filtering functions give a higher-order modulator. Now, we have that the SN is given y SN Σ = 6 N + K + ( 2 M + ) logos (7) where K is a function of the modulator order M. Using a 3rd order modulator we find that using a -it converter ( N = ) we can realize a 4-it converter ( N = ) using an oversampling ratio of only OS = 6. The advantage of using a -it converter is totally linear even if there are matching errors [9]. The use of higher-order modulators will however increase power dissipation and chip area and introduce a much higher design complexity. For -it converters, filtering in stages, hence using socalled semi-digital FI filtering, must e applied to further relax the requirements on the analog filters due to the high out-of-and noise power. The DEM techniques descried in the following are aiming for moving the matching errors in a similar way as the truncation noise is shaped in oversampling s. IV. DYNAMIC ELEMENT MATCHING IN S The DEM techniques have shown promising results in s to improve performance [2-6]. A high-level topology of a DEM system for D/A conversion is shown in Fig. 3. The inary input word is thermometer coded and Thermometer Encoder Digital Encoder Scramler x [n] x 2 [n] x N [n] -it -it -it y [n] y 2 [n] y N [n] Figure 3. A high-level topology of a DEM system y[n] scramled efore entering the -it s. The outputs of the -it s are added to yield the desired output. One ig advantage with the structure is that y using -it s we can achieve perfect linear performance. In this section, two of the most suitale DEM techniques for high-speed and high-resolution applications are reviewed. A. Partial andomization DEM A generalized partial randomization DEM, PDEM, structure [4] is shown in Fig. 4. It contains a switching tree, which contains switching locks, S k, r, where k denotes the layer and r denotes the position of the x[n] (LSB) S, Layer - S -, - - S -, - Layer - S, S, S, Layer Figure 4. A general PDEM structure -ank -ank switching lock in the layer. The switching lock has one k + -it input and two k -it outputs, and an additional random control it c k [ n]. The random control it is equal for all locks S k, r within the k th layer. Each c k [ n] is a white random or pseudo random it-sequence, PBS, statistically independent from the control its used in all other layers. S k, r operates such that when c k [ n] =, the MSB, x k of the input is mapped to all k its of the top output (Fig. 5), and the remaining k its of the input are mapped directly to the k its of the ottom output. For c k [ n] = the situation is reversed. k+ MSB LSBs k k k k k- k-2 S k,r Figure 5. The S k, r switching lock In PDEM we introduce switching in a limited numer of layers, i.e., in layers through (Fig. 4), where 2. Since no randomness is introduced in layers through we can simply sustitute these layers y N = 2 + nominally identical -anks each with an -it input (Fig. 6). The LSB of the input controls a unit element, whereas the remaining its control an -it conventional. B. Full randomization DEM A full randomization DEM, FDEM, system uses switching in all layers, i.e., layers through and herey has -it s in the final layer. This system will in theory achieve ideal SFD performance, ut it suffers from a -ank -ank -ank -ank c k [n] k k y[n]

4 large hardware cost [3]. Therefore trade-offs have to e done for higher-resolution s. MSBs LSB - -ank (-)-it -it Figure 6. The (-/) ank. V. SIMULATION ESULTS It has een shown [4] that the PDEM yields the same SFD performance as the FDEM with only a few switching layers ut at a significantly lower hardware cost. Therefore it is of large interest to see how a PDEM structure can e implemented and then evaluate the performance to verify the theory presented lately [3-4]. Due to long simulation times a 6-it will serve as an illustrative example. A. Simulation Setup The 6-it consists of an interpolator filter, a 3rd order digital Σ modulator, a 6-it, and an analog low pass filter as shown in Fig. 7. Digital Interpolator 3rd order Σ Modulator 6-it PDEM Figure 7. Simulation setup of a 6-it Σ Analog LP filter The digital input signal contains to a large extent of truncation noise that is moved away from the signal and y the 3rd order Σ modulator. Normally step-size mismatches in a conventional (inary weighted) will result in distortion terms added to the signal and. This distortion will spoil the overall conversion precision of the. But for a using DEM the distortion will e converted into noise and herey yielding etter SFD performance. Finally, the unwanted noise is filtered y the analog low pass filter. In the simulations a Gaussian distriuted error with a rather large standard deviation, σ = 8%, has een added to the unit current sources. The input signal is a singletone sinusoid and the power spectral density (PSD) of the output signal is examined. B. Full andomization A comparison etween a conventional 6-it (Fig. 8a) and a using FDEM, i.e., switching in all six layers (Fig. 8) shows that the distortion terms have een suppressed down elow the noise floor to the cost of a higher noise floor in the signal and Conventional 6 it FDEM 6 it C. Partial andomization A comparison where the numers of switching layers have een varied can e seen in Fig. 9. The numer of switching layers is one in (a) and two in (). We gain some in SFD only y using a single switching layer (Fig. 9a) compared to the conventional (Fig. 8a). With two switching layers the distortion terms have een suppressed elow the noise floor yielding the same SFD performance as for FDEM (Fig. 8). () Figure 8. PSD plots of a 6-it a) conventional- and, ) FDEM switching layers (a) switching layers (a) () Figure 9. PSD plots of a 6-it PDEM using a) -, and ) 2 switching layers.

5 D. Comparison and Conclusions As we can see from the simulation results aove we generally do not gain much in SFD y increasing the numer of switching layers. Once the distortion terms have een suppressed elow the noise floor we do not gain in performance ut the hardware complexity is rapidly increasing. VI. IMPLEMENTATION OF A PDEM STUCTUE IN A CUENT-STEEING As simulations have shown [4], we can achieve good performance with a PDEM structure using switching in a few layers only. A four-layer PDEM structure has een found to e a good trade-off for a 4-it wide-and when considering hardware cost, matching, etc. This gives us a four-layer inary switching tree ended y 6 -anks (consisting of a -it and a - it ). One very area effective implementation of a 4-it four-layer PDEM is shown in Fig.. The signal path from input to output (dashed in Fig. ) is equally long for all -anks and guarantees same delay for all input signals. The numer of switching layers in the structure can easily e modified. S, S,5 S 2, S,2 S,3 S 2,2 S 3, S 4, S 3,2 S,7 S 2,3 S,6 S 2,4 Signal path S,4 S,8 Figure. A 4-it using a four layer PDEM structure. A. Digital Switching Blocks Since the switching locks S k, r only consist of inary switches, i.e., 2-to-2 multiplexers, they can e laid out very compact. The only extra circuitry that has to e added to the switching tree are the D-latches for pipelining the data path through the switching tree. This ensures high speed and good timing performance. A gloal clock distriution tree is used. B. Topology In order to reduce the influence of glitches, the s are implemented using a segmented structure with the four MSBs thermometer coded. To further reduce the effects of glitches and clock feedthrough, the switches are differential and implemented with NMOS transistors for high-speed. Differential output currents with peak amplitudes of 2 ma are to e douly terminated over 5Ω loads. Local iasing as well as a gloal iasing strategy is used for matching of all 6 -anks. A 5-it PBS generator [7] is distriuting the random switching signal c k [ n]. For test purpose, c k [ n] can e set to for all locks and hence no randomization is introduced in the. C. Chip Summary The 4-it is designed for an 88-MHz update frequency and a signal frequency andwidth of approximately MHz. The process is a standard digital.35 µm 3-metal layer CMOS process. The chip data is further summarized in Tale and in Fig. we show a layout plot of the converter. The chip is currently eing processed. esolution Peak output current Clock frequency Signal andwidth Chip size Process Supply voltage 4 its 2 ma differential 88 MHz.4 MHz 9.3 mm 2 incl. pads 4.7 mm 2 core 3-metal single poly.35 µm CMOS 3.3 V analog and digital supplies Tale : Chip data. VII. CONCLUSIONS We have discussed the design of a PDEM technique in a current-steering digital-to-analog converter. We have found that PDEM is the most suitale of the DEM techniques for high- resolution wide-and s. The PDEM allows a trade-off in terms of hardware and performance, since with only a few switching layers, distortion terms are sufficiently suppressed. The implementation of a 4-it current-steering CMOS for a MHz signal andwidth using the PDEM technique has also een presented. ACKNOWLEDGEMENTS The authors appreciate all the help from K. Ola Andersson and Mikael Karlsson-uderg, oth at the Micro-

6 electronics esearch Center, Ericsson Components AB, and Prof. Lars Wanhammar at the Department of Electrical Engineering, Linköping University. EFEENCES [] M.J.M. Pelgrom, et al., Matching Properties of MOS Transistors, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp , Oct [2] P. Carone and I. Galton, Conversion error in D/A converters employing dynamic element matching, in Proc. of IEEE ISCAS 94, vol. 2, pp. 3-6, 994. [3] H.T. Jensen and I. Galton, A low-complexity dynamic element matching for direct digital synthesis, IEEE Transactions of Circuits and Systems II, vol. 45., pp. 3-27, Jan [4] H.T. Jensen and I. Galton, An analysis of the partial randomization dynamic element matching technique, IEEE Transactions of Circuits and Systems II, vol. 45.2, pp , Dec [5] I. Galton, Spectral Shaping of Circuit Errors in Digital-to-Analog Converters, IEEE Transaction of Circuits and Systems II, vol. 44., pp , Oct [6].K. Henderson and O.J.A. Nys, Dynamic element matching techniques with aritrary noise shaping function, in Proc. of IEEE ISCAS'96, vol., pp , Atlanta, USA, 996. [7].N. Mutagi, Pseudo Noise Sequences for Engineers, Electronics & Communication Engineering Journal, vol. 8.2, pp , April 996. [8].J. van de Plassche, Integrated analog-to-digital and digital-to-analog converters, Kluwer, Boston, USA, 994. [9] D.A. Johns and K. Martin, Analog integrated circuit design, Wiley, New York, NY, USA, 997. [] J.J. Wikner and N. Tan, CMOS Data Converters for Communications, Kluwer, USA, 2. [] J.J. Wikner and M. Vesteracka, D/A Conversion with Linear-Coded Weights, in Proc. of the IEEE 2 Southwest Symposium on Mixed-Signal Design, SSMSD, San Diego, CA, USA, Fe , mm 2.9 mm Figure. Chip plot of a 4-it four layer PDEM