DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS

Transcription

1 DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS

2 tekst THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE Related Titles: ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC'S Claes and Sansen Vol. 854, ISBN: MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and Steyaert Vol. 843, ISBN: SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN: LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION van der Meer, van Staveren, van Roermund Vol. 841, ISBN: WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE CANCELLATION Bruccoleri, Klumperink, Nauta Vol. 840, ISBN: SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS Bajdechi and Huijsing Vol. 768, ISBN: OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENT Ivanov and Filanovsky Vol. 763, ISBN: STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEED D/A CONVERTERS van den Bosch, Steyaert and Sansen Vol. 761, ISBN: DESIGN AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR Xdsl Piessens and Steyaert Vol. 759, ISBN: LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS Silveira and Flandre Vol. 758, ISBN: X MIXED-SIGNAL LAYOUT GENERATION CONCEPTS Lin, van Roermund, Leenaerts Vol. 751, ISBN: HIGH-FREQUENCY OSCILLATOR DESIGN FOR INTEGRATED TRANSCEIVERS Van der Tang, Kasperkovitz and van Roermund Vol. 748, ISBN: CMOS INTEGRATION OF ANALOG CIRCUITS FOR HIGH DATA RATE TRANSMITTERS DeRanter and Steyaert Vol. 747, ISBN: SYSTEMATIC DESIGN OF ANALOG IP BLOCKS Vandenbussche and Gielen Vol. 738, ISBN: SYSTEMATIC DESIGN OF ANALOG IP BLOCKS Cheung and Luong Vol. 737, ISBN: LOW-VOLTAGE CMOS LOG COMPANDING ANALOG DESIGN Serra-Graells, Rueda and Huertas Vol. 733, ISBN: X CIRCUIT DESIGN FOR WIRELESS COMMUNICATIONS Pun, Franca and Leme Vol. 728, ISBN: DESIGN OF LOW-PHASE CMOS FRACTIONAL-N SYNTHESIZERS DeMuer and Steyaert Vol. 724, ISBN: MODULAR LOW-POWER, HIGH VOLUME SPEED CMOS 595 ANALOG-TO-DIGITAL CONVERTER FOR EMBEDDED SYSTEMS Lin, Kemna and Hosticka Vol. 722, ISBN:

3 DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED- CAPACITOR CIRCUITS Extending the Boundaries of CMOS Analog Front-End Filtering by Seng-Pan U University of Macau and Chipidea Microelectronics (Macau), Ltd., China Rui Paulo Martins University of Macau, China and Technical University of Lisbon, Portugal and José Epifânio da Franca Chipidea Microelectronics, S.A. and Technical University of Lisbon, Portugal

4 A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN (HB) ISBN (HB) ISBN (e-book) ISBN (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. Printed on acid-free paper All Rights Reserved 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands.

5 Dedication This book is dedicated to Our Wives

6 Contents Dedication Preface Acknowledgment List of Abbreviations List of Figures List of Tables v xiii xvii xix xxiii xxxi 1 INTRODUCTION 1 1. High-Frequency Integrated Analog Filtering Multirate Switched-Capacitor Circuit Techniques Sampled-Data Interpolation Techniques Research Goals and Design Challenges IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES Introduction Conventional and Improved Analog Interpolation Polyphase Structures for Optimum-class Improved Analog Interpolation Multirate ADB Polyphase Structures...22

7 viii Design of Very High-Frequency Multirate Switched-Capacitor Circuits 4.1 Canonic and Non-Canonic ADB Realizations FIR System Response IIR System Response SC Circuit Architectures Low-Sensitivity Multirate IIR Structures Mixed Cascade/Parallel Form Extra-Ripple IIR Form Summary PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS Introduction Power Consumption Analysis Capacitor-Ratio Sensitivity Analysis FIR Structure IIR Structure Finite Gain & Bandwidth Effects Input-Referred Offset Effects Phase Timing-Mismatch Effects Periodic Fixed Timing-Skew Effect Random Timing-Jitter Effects Noise Analysis Summary GAIN- AND OFFSET-COMPENSATION FOR MULTIRATE SC CIRCUITS Introduction Autozeroing and Correlated-Double Sampling Techniques AZ and CDS SC Delay Blocks with Mismatch-Free Property SC Delay Block Architectures Gain and Offset Errors Expressions and Simulation Verification Multi-Unit Delay Implementations AZ and CDS SC Accumulators SC Accumulator Architectures Gain and Offset Errors Expressions and Simulation Verification Design Examples Speed and Power Considerations Summary...94

8 Design of Very High-Frequency Multirate Switched-Capacitor Circuits ix 5 DESIGN OF A 108 MHZ MULTISTAGE SC VIDEO INTERPOLATING FILTER Introduction Optimum Architecture Design Multistage Polyphase Structure with Half-Band Filtering Spread-Reduction Scheme Coefficient-Sharing Techniques Circuit Design st -Stage nd - and 3 rd -Stage Digital Clock Phase Generation Circuit Layout Simulation Results Behavioral Simulations Circuit-Level Simulations Summary DESIGN OF A 320 MHZ FREQUENCY-TRANSLATED SC BANDPASS INTERPOLATING FILTER Introduction Prototype System-Level Design Multi-notch FIR Transfer Function Time-Interleaved Serial ADB Polyphase Structure with Autozeroing Prototype Circuit-Level Design Autozeroing ADB and Accumulator High-Speed Multiplexer Overall SC Circuit Architecture Telescopic opamp with Wide-Swing Biasing nmos Switches Noise Calculation I/O Circuitry Low Timing-Skew Clock Generation Layout Considerations Device and Path Matching Substrate and Supply Noise Decoupling Shielding Floor Plan Simulation Results Opamp Simulations Filter Behavioral Simulations...155

9 x Design of Very High-Frequency Multirate Switched-Capacitor Circuits 5.3 Filter Transistor-Level and Post-Layout Simulations Summary EXPERIMENTAL RESULTS Introduction PCB Design Floor Plan Power Supplies and Decoupling Biasing Currents Input and Output Network Measurement Setup and Results Frequency Response Time-Domain Signal Waveforms One-Tone Signal Spectrum Two-Tone Intermodulation Distortion THD and IM3 vs. Input Signal Level Noise Performance CMRR and PSRR Summary CONCLUSIONS 187 APPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS Spectrum Expressions for IU-ON(SH) and IN-CON(SH) IU-ON(SH) IN-CON(SH) Closed Form SINAD Expression for IU-ON(SH) and IN- CON(SH) IU-ON(SH) IN-CON(SH) Closed Form SFDR Expression for IN-CON(SH) systems Spectrum Correlation of IN-OU(IS) and IU-ON(SH) APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFILTERS Output Noise of ADB Delay Line Output Noise of Polyphase Subfilters Using TSI Input Coefficient SC Branches Using OFR Input Coefficient SC Branches...220

10 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xi APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J GOC MF SC Delay Circuit I GOC MF SC Delay Circuit J...225

11 Preface Integration of high-frequency analog filtering into the system Analog Front-End (AFE) is increasingly demanded for the ever growing high-speed communications and signal processing solutions with the corresponding advances in Integrated Circuit (IC) technology. Although the AFEs represent a small portion of the total mixed-signal system chip, they usually are its speed and performance bottleneck. Especially, the design of the AFEs becomes more and more challenging due to the continuous lowering of the supply and increasing of the operation speed, as well as noisying of the working environment driven by the constant growing digital signal processing (DSP) core. This book presents a multirate sampled-data interpolation technique and its Switched-Capacitor (SC) implementation for very high frequency filtering (over hundreds of MHz) while having also dual inherent advantages of reducing the speed of the digital-to-analog converter and the DSP core together with the simplification of the post continuous-time smoothing filter. The book is organized in eight chapters. This chapter presents an overview of the introductory aspects of the current state-of-the-art highfrequency SC filters and multirate filtering with emphasis on the SDA interpolation techniques for explicating the motivation and the objectives of the research work in this book. Chapter 2 will describe the mathematical characterization of the conventional sampled-data analog interpolation with its input lower-rate S/H shaping distortion and will also introduce the ideal improved analog interpolation model with its traditional bi-phase SC structure implementation. Then, the development of the efficient multirate polyphase-based SC structures suitable for high-performance optimum-class improved analog

12 xiv Design of Very High-Frequency Multirate Switched-Capacitor Circuits interpolation filtering will be proposed. Different low-sensitivity circuit topologies with both Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) characteristics will be developed, respectively, for low and high selectivity filtering. Chapter 3 will present the practical IC technology imperfections related to IC implementation of SC multirate circuits that will be comprehensively investigated with respect to the power requirement issue, capacitance ratio mismatches, finite gain and bandwidth, input-referred DC offset sensitivity effects of the opamps, timing random-jitter and fixed periodic skew in the multirate clock phase generation as well as filter overall noise performance. All those practical design considerations are very useful in high-speed sampled-data analog integrated circuit design. Chapter 4 will present advanced circuit techniques, i.e. gain- and offsetcompensations, specialized for multirate SC filters and that are necessary to alleviate the imperfections of the analog integrated circuitry. Such techniques will be explored first for the basic building blocks: mismatch-free SC delay cells and SC accumulator, and later the impacts in the compensation of the overall system response will also be addressed and demonstrated through specific examples for both multirate FIR and IIR SC interpolating filters. Furthermore, the practical design trade-offs for utilization of such techniques will also be analyzed with respect to the accuracy versus speed and power. Chapter 5 will set forth the design and implementation of a low-power SC baseband interpolating filter for NTSC/PAL digital video restitution system with CCIR-601 standards. The filter, which employs several novel optimized structures including coefficient-sharing, spread-reduction, semioffset-compensation, mismatch-shaping, double-sampling and analog multirate/techniques, achieves a linear-phase lowpass response with 5.5- MHz bandwidth, 108 Msample/s output from 13.5 Msample/s video input. Both behavior-, transistor- and layout-extracted level simulations will be presented for illustrating the effectiveness of the circuit in 0.35 µm CMOS technology. Chapter 6 will describe the design and implementation of a 2.5 V, 15- tap, 57 MHz SC FIR bandpass interpolating filter with 4-fold frequency uptranslation for MHz inputs at 80 MHz to MHz outputs at 320MHz to be used in a Direct-Digital Frequency Synthesis (DDFS) system for wireless communication also in 0.35 µm CMOS. Special design considerations in both filter transfer function, circuit architectures, circuit building blocks as well as specific layout techniques for dealing with nonideal properties in realization of the high-speed analog and digital clock

13 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xv circuits will be presented comprehensively in terms of the speed relaxation, noise and mismatching reduction. Chapter 7 will then present the Printed-Circuit Board (PCB) design, experimental testing setup, as well as the measured results of the prototype interpolating filter chip built for the DDFS system described in Chapter 5. In addition to the measurement summary, a comparison among previously reported SC filters will also be offered. Chapter 8 will finally draw the relevant concluding remarks. Appendixes will be also provided for detailed mathematic derivation and analysis of the timing-skew errors in parallel sampled-data systems with S/H effects, namely, non-uniformly holding effects, and also the estimation scheme of the filter noise performance including opamp finite-gain and offset error analysis of SC building blocks. Seng-Pan U, Ben Rui Paulo Martins José Epifânio da Franca

14 Acknowledgment This work was developed under the support of the Research Committee of University of Macau, Integrated Circuits and Systems Group of Instituto Superior Técnico / Universidade Técnica de Lisboa, Fundação Oriente and Chipidea Microelectronics, S.A.. We also thank Terry Sai-Weng Sin for the assistance in formatting the text and figures as well as his contribution in timing-mismatch signal-to-noise mathematical analysis in Appendix 1. Finally, we would like to express enormous respect to our wifes for their constant understanding and endless support.

15 List of Abbreviations AAF : Anti-Aliasing Filter AC : Alternating Current ADB : Active Delayed-Block ADC : Analog-to-Digital Converter AFE : Analog Front-End AIF : Anti-Imaging Filters AZ : Autozeroing BPF : Band-Pass Filter C-DFII : Complete Direct-Form II CAD : Computer-Aided Design CDMA : Code Division Multiple Access CDS : Correlated-Double Sampling CM : Common Mode CMOS : Complementary Metal Oxide Semiconductor CMFB : Common-Mode Feedback CMRR : Common-Mode Rejection Ratio CQFP : Ceramic Quad Flat-Pack CT : Continuous-Time DAC : Digital-to-Analog Converter DB : Differentiator-Based DC : Direct Current DDFS : Direct-Digital Frequency Synthesis DF : Direct-Form DFII : Direct-Form II DR : Dynamic Range

16 xx Design of Very High-Frequency Multirate Switched-Capacitor Circuits DSP : Digital Signal Processing DT : Discrete-Time DUT : Device Under Test DVD : Digital Video Disks EC : Error-storage Capacitor EM : Electromagnetic EMC : Electromagnetic Compatibility ENBW : Equivalent Noise Bandwidth ER : Extra Ripple FFT : Fast Fourier Transform FIR : Finite-Impulse-Response GBW : Gain BandWidth GOC : Gain- and Offset-Compensation H-CDS : Holding Correlated-Double Sampling IC : Integrated Circuit IF : Intermediate-Frequency IIR : Infinite Impulse Response IM3 : 3 rd -order Intermodulation Distortion IN-CON : Input & Output timing-correlatively, Nonuniformly sampled & played out IN-OU : Input Nonuniformly sampled, Output Uniformly played out IS : Impulse-Sampled IU-ON : Input Uniformly sampled, Output Nonuniformly played out I-V : Current-to-Voltage LC : Inductive-Capacitive LPF : Low-Pass Filter LVS : Layout versus Schematic MF : Mismatch-Free MCP-DFII : Mixed Cascade/Parallel Direct Form II MOS : Metal-Oxide Semiconductor MUX : Multiplexer NTSC : National Television Standards Committee OFR : Open-floating Resistor OIP3 : Output 3 rd -order Intercept Point OPAMP : operational amplifier OTA : Operational Transconductance Amplifier P-CDS : Predictive Correlated-Double Sampling

17 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xxi. P-DFII : Parallel Direct Form II PAL : Phase Alternation Line PC : Parallel-Cyclic PCB : Printed-Circuit Board PCTSC : Parasitic-Compensated Toggle-Switched Capacitor PM : Phase Margin POG : Precise Opamp Gain PSRR : Power Supply Rejection Ratio PSS-AC : Periodic Swept Steady-State AC Analysis QFP : Quad Flat-Pack R-ADB : Recursive-ADB RES : Rising-Edge Synchronizing RF : Radio Frequency ROM : Read-Only Memory RUT : ROM Look-Up Table SC : Switched-Capacitor SDA : Sample-Data Analog SDM : Sigma-Delta modulators SDV : Switched Digital Video SFDR : Spurious-Free Dynamic Range S/H : Sample-and-Hold SI : Switched-current SMD : Surface-Mount Device SINAD : Signal-to-Noise Plus Distortion Ratio SNR : Signal-to-Noise Ratio SSC : Same Sample Correction T/H : Track-and-Hold TDMA : Time Division Multiple Access THD : Total Harmonic Distortion TSC : Toggle-Switched Capacitor TSI : Toggle-Switched Inverter TV : Television UC : UnCompensated UGB : Unity-Gain Bandwidth VCM : Common-Mode Voltage VDSL : Video Digital Subscriber loop V-I : Voltage-to-Current

18 List of Figures Figure 1-1 High-frequency Switched-Capacitor filters reported in CMOS 3 Figure 1-2 SDA multirate filtering for efficient analog front-end systems 4 Figure 1-3 (a) Non-optimum-class and (b) Optimum-class decimation and interpolation filtering 4 Figure 1-4 (a) Baseband (b) Frequency-translated interpolation filtering 6 Figure 2-1 Conventional analog L-fold interpolation (a) Architecture model (b) Time- and frequency-domain illustration 17 Figure 2-2 Improved Analog interpolation with reduced S/H effects (a) Architecture Model (b) Non-optimum SC implementation with a high-rate Bi-Phase filter 19 Figure 2-3 Improved analog interpolation with Optimum-class realization by Direct-Form polyphase structure (L=2) 21 Figure 2-4 (a) Canonic-form (b) Non-canonic-form ADB polyphase structures for improved 4-fold 12-tap FIR interpolator 23 Figure 2-5 Figure 2-6 Canonic-form R-ADB/C-DFII polyphase structures for improved 3-fold SC IIR video interpolator 27 SC circuit schematic for canonic-form R-ADB/C-DFII polyphase structures 28

19 xxiv Design of Very High-Frequency Multirate Switched-Capacitor Circuits Figure 2-7 Non-canonic-form R-ADB/C-DFII polyphase structures for improved 3-fold SC IIR video interpolator 31 Figure 2-8 SC circuit schematic for non-canonic-form R-ADB/C-DFII polyphase structures 31 Figure 2-9 Simulated amplitude response for improved 3-fold SC IIR video interpolator with Elliptic and ER transfer function 32 Figure 2-10 (a) R-ADB/P-DFII for Improved 3-fold SC IIR video interpolator (b) R-ADB/MCP-DFII for Improved 3-fold SC IIR video interpolator 35 Figure 2-11 SC circuit schematic for non-canonic-form R-ADB/MCP- DFII polyphase structures 36 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Equivalent continuous-time model of SC circuit during charge-transfer phase 42 (a) Amplitude sum-sensitivity (b) Monte-Carlo simulations with respect to all capacitors of an 18-tap improved SC FIR LP interpolating filter 45 Group-delay sum-sensitivity with respect to all capacitors of an 18-tap improved SC FIR LP interpolating filter 46 Amplitude sum-sensitivity with respect to all capacitors for improved 3-fold SC IIR video interpolating filter with different architectures and with (a) 4th-Order Elliptic & ER (N=9, D=2) and (b) 6th-Order Elliptic & ER (N=9, D=4) transfer functions 48 Opamp finite gain & bandwidth effects for improved 3-fold SC IIR interpolator with ER (N=9, D=2) transfer function (a) Passband (b) Stopband 50 Output signal spectrum of 4-fold, 18-tap SC FIR interpolating filter (1Vp-p input, offset σ OA =3.5 mv) 54 Output phase-skew sampling for polyphase-based interpolating filters 56 Spectrum of a 58 MHz signal sampled at 320 MHz with timing skew (M=8, σ=5 ps) 57 Mean value of SNR and SFDR due to the output phase-skew effects vs. signal frequencies and standard deviation

20 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xxv (sigma) of the skew-timing ratio r m for different interpolation factors (100-time Monte Carlo calculations) (a) L=2 (b) L=4 (c) L=8 58 Figure 3-10 Noise in the i th mismatch-free SC ADB in (a) sampling phase A and (b) output phase B 61 Figure 3-11 Noise in one of the L-path polyphase subfilter in (a) sampling phase A and (b) output phase B 63 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Virtual ground error voltage compensated by AZ or CDS techniques 70 Classification of Correlated-Double Sampling SC techniques 72 Different mismatch-free SC delay blocks with UC, AZ and CDS techniques 75 Simulated gain & phase errors for SC delay circuits in Figure 4-3 without parasitics (a) & (b) and with parasitics (c) & (d) (Parasitics: 10% & capacitor top & bottom plate, C opamp input node =C F ) 76 Different MF UC, AZ, CDS delay blocks with flexible delay implementation 81 Different SC accumulator architectures with UC, AZ and CDS techniques 83 Simulated gain & phase errors for SC accumulator circuits in Figure 4-6 without parasitics (a) & (b) and with parasitics (c) & (d) 85 (a) R-ADB polyphase structures and simplified SC schematic with CDS for a 4 th -order IIR interpolating filter for DDFS 86 Simulated amplitude response of 4 th -order IIR interpolating filter for DDFS 88 Figure 4-10 (a) Zero plots and (b) Simulated amplitude response of a 15- tap SC FIR interpolating filter with UC, H-CDS and P-CDS realizations (A=100) 89 Figure 4-11 Circuit configurations for different operation phases for UC, AZ and CDS SC circuits 90

21 xxvi Design of Very High-Frequency Multirate Switched-Capacitor Circuits Figure 4-12 (a) Feedback factor and effective capacitive loading (b) Current consumption for SR and linear settling versus C PI /C h for CDS circuits with employment of error-storage capacitor 93 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 (a) Traditional (b) Multirate alternative for digital video restitution system stage implementation of 8-fold interpolating filter for digital video restitution system 102 (a) One-opamp scheme (b) Double-sampling scheme (c) Autozeroing scheme for spread-reduced two-step summing technique 104 (a) Instantaneous-adding (b) Subsequent-adding SC subtraction branches using Coefficient- Sharing Technique 105 Figure 5-5 SC implementations for 3-stage video interpolating filter 106 Figure 5-6 (a) AZ (b) EC/P-CDS SC implementations for the 1 st -stage 108 Figure 5-7 Simplified SC implementations for the 2 nd - and 3 rd -stage 110 Figure 5-8 Figure 5-9 Multiple phase generation block diagram for multistage SC video interpolating filter 111 (a) Synchronize Submaster clock generation (b) Phase-width controls circuitry 112 Figure 5-10 SNR and SFDR Mean vs. timing-skew errors (100-time Monte-Carlo) ( f in =5.5 MHz, f s =108 MHz) 113 Figure 5-11 Circuit layout for 3-stage 8-fold SC interpolating filter (AC- Accumulator, PF-Polyphase Filter, MP-Multiplexer) 114 Figure 5-12 Monte-Carlo amplitude response simulation (500-time, σ = 0.5 %) 115 Figure 5-13 Periodic swept steady-state AC (PSS-AC) amplitude response from full transistor-level simulation 116 Figure 5-14 Spectrum of MHz output signal from the worst-case transistor-level simulation 116

22 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xxvii Figure 5-15 Impulse transient response from parasitic-involved layoutextracted simulation (a) 1 st -stage (b) 2 nd +3 rd stage (c) overall 3-stage 117 Figure 6-1 Figure 6-2 Figure 6-3 (a) Traditional ROM-based DDFS system (b) Proposed DDFS system with frequency-translated SC bandpass interpolation filtering and its signal spectrum 124 Zero-plot for multi-notch FIR system function by optimum zero-placement method 126 Time-interleaved serial ADB polyphase structure with autozeroing 128 Figure 6-4 Autozeroing, Mismatch-Free SC ADB with z -6 delay 129 Figure 6-5 Autozeroing SC accumulator for polyphase subfilter (a) m=0 (b) m=2 130 Figure 6-6 High-speed mismatch-free SC multiplexer 131 Figure 6-7 Overall SC circuit schematic for 15-tap FIR bandpass interpolating filter 132 Figure 6-8 Schematic of Telescopic opamp with wide-swing biasing 134 Figure 6-9 (a) Single-sampling SC CMFB for filter core and (b) Double-sampling SC CMFB for multiplexer 136 Figure 6-10 (a) SNR and (b) SFDR Mean vs. timing-skew errors and sampling rates (100-time Monte-Carlo) 139 Figure 6-11 Simplified structure for low timing-skew multirate clock generator 140 Figure 6-12 Equal-width non-overlapping clock phase generation 141 Figure 6-13 Rising-edge-synchronization buffer array 141 Figure 6-14 Spike current assignment by individual-on-chip VDD supply scheme 142 Figure 6-15 Layout of Telescopic op amp 143 Figure 6-16 Chip microphotograph for capacitor group for (a) Polyphase subfilter m=0 (b) z -6 ADB (c) Multiplexer 145

23 xxviii Design of Very High-Frequency Multirate Switched-Capacitor Circuits Figure 6-17 Chip microphotograph for polyphase subfilter m=0 146 Figure 6-18 Chip microphotograph for clock generator and output multiplexer 147 Figure 6-19 Spike-current flows for shared ground scheme with on-chip decoupling in (a) rising (b) falling edges 150 Figure 6-20 Die microphotograph 152 Figure 6-21 Opamp layout-extracted AC open-loop frequency response from corner simulations 153 Figure 6-22 Opamp layout-extracted DC gain and output swing from corner simulations 153 Figure 6-23 Histogram of a 500-run Monte-Carlo simulation to process variation (a) Unity-gain bandwidth (b) Phase Margin (c) DC Gain (d) DC 1.2Vp-p. 154 Figure 6-24 Scatter plot of a 500-run Monte-Carlo simulation to process variation (a) Unity-gain bandwidth vs. Phase Margin (b) Unity-gain bandwidth vs. DC Gain 154 Figure 6-25 Opamp layout-extracted loop-gain with / without switch resistance in feedback path 155 Figure 6-26 Monte-Carlo amplitude response simulations (σ e = 0.7 %) 155 Figure MHz output signal with a 1V p-p 22MHz input ( f s =320MHz) from top-view layout-extracted simulation 156 Figure 6-28 Spectrum of 58MHz output signal with a 1V p-p 22MHz input ( f s =320MHz) from worst-case top-view transistor-level simulations 157 Figure 6-29 Impulse transient response from top-view layout-extracted worst-case simulation 157 Figure 6-30 Buffered 58 MHz output signal waveforms (a) 22 MHz input and differential output (b) Positive and negative outputs from top-view layout-extracted simulations 158 Figure 7-1 PCB block diagram and experimental test setup 165 Figure 7-2 (a) Top-view (b) Bottom-view of the 4-layer PCB 166

24 Design of Very High-Frequency Multirate Switched-Capacitor Circuits xxix Figure 7-3 Figure 7-4 Figure 7-5 Characteristic impedance for conductor-backed coplanar waveguides versus track width and gap 169 View of laboratory testing instruments (Intermodulation distortion measurement) 170 Measured amplitude responses for different output sampling rates 171 Figure 7-6 Measured amplitude response for 10 samples with (a) 320 MHz (b) 160 MHz (c) 400 MHz output sampling rates 171 Figure 7-7 Measured 58 MHz output signal waveforms sampled at 320 MHz (a) 22 MHz input and differential output (b) Positive and negative outputs 173 Figure 7-8 Measured signal waveforms (a) 11 MHz input, 29 MHz output for 160 MHz sampling rate (b) 27.5 MHz input, 72.5 MHz output for 400 MHz sampling rate 173 Figure 7-9 Measured spectrum of 58 MHz output signal sampled at 320 MHz with (a) 1 V p-p and (b) 2.1 V p-p 22 MHz input 175 Figure 7-10 Measured signal spectrum (a) 29 MHz output for 160 MHz sampling rate (b) 72.5 MHz output for 400 MHz sampling rate 175 Figure 7-11 Measured spectrum of output signals sampled at 320 MHz with (a) 0.5 V p-p and (b) 0.85 V p-p two-tone inputs with 600 KHz separation 176 Figure 7-12 Measured output signals spectrum from 0.5 V p-p two-tone inputs with (a) 300 KHz separation for 160 MHz sampling rate (b) 800 KHz separation for 400 MHz sampling rate 176 Figure 7-13 Measured THD and IM3 vs. input signal level for different output sampling rates 177 Figure 7-14 Measured fixed-pattern noise with zero input for (a) 160 MHz (b) 320 MHz (c) 400 MHz output sampling rates 178 Figure 7-15 Measured output noise spectrum density for different sampling rates 179 Figure 7-16 Measured CMRR versus frequency for different sampling rates 180

25 xxx Design of Very High-Frequency Multirate Switched-Capacitor Circuits Figure 7-17 Measured off-chip digital power supplies (DVDD=2.5V) 181 Figure 7-18 Brief comparison of the state-of-the-art CMOS SC filters 182 Figure A1-1 Equivalent (a) IN-OU(IS) (b) IU-ON(SH) (c) IN-CON(SH) processes for Time-Interleaved ADC, DAC and Sampleddata Systems 194 Figure A1-2 FFT spectra of output sinusoid for (a) IN-OU, (b) IU-ON and (c) IN-CON processes with both IS and SH output (a=0.2, M=8, rm = 0.1%) 195 Figure A1-3 (a) Simulated SINAD & (b) absolute error between the simulated and calculated SINAD of IU-ON(SH) systems vs. normalized frequency a and standard derivation rm by 10 4 times Monte Carlo Simulations (M=8) 200 Figure A1-4 (a) Simulated SINAD & (b) absolute error between the simulated and calculated SINAD of IN-CON(SH) systems vs. normalized frequency a and standard derivation rm by 10 3 times Monte Carlo simulations 204 Figure A1-5 Absolute error between the simulated and calculated SINAD of IN-CON(SH) systems vs. (a) path no. M and standard derivation rm (a = 0.5) and (b) normalized signal frequency a and standard derivation rm (M = 2) by 10 3 times Monte Carlo simulations 205 Figure A1-6 A plot of variation of in-band SFDR of IN-CON(SH) system vs. timing-skew period M and rm 206 Figure A1-7 FFT of a 58 MHz signal sampled at 320 MHz for (a) IN- OU(IS) (b) IU-ON(SH) M=4, σ=20 ps) 207 Figure A1-8 (a) Mean SINAD for IU-ON(SH) and (b) Relative difference of Mean SINAD between IN-OU(IS) & IU-ON(SH) versus signal frequency, standard derivation of skew-timing ratio r m and the path number M 212 Figure A3-1 EC/P-CDS GOC MF SC delay circuit (i) 221 Figure A3-2 Differential-input, EC/P-CDS GOC MF SC delay circuit ( j) 225

26 List of Tables Table 2-1 Transfer function coefficients of 3-Fold SC LP IIR video interpolators: original (a i and b i ) and multirate-transformed (A i and B i ) for Elliptic and ER C-DFII structures 27 Table 2-2 Multirate-transformed coefficients of transfer function of 3- Fold SC LP IIR video Elliptic (D=4) interpolators in P-DFII and MCP-DFII structures 36 Table 3-1 Power comparison for 3-Fold SC LP IIR with ER transfer function 43 Table 3-2 Monte-Carlo Simulations of fixed pattern noise imposed by input-referred DC offset of opamps for 4-fold, 18-tap SC FIR interpolating filter (20-time, σ OA =3.5 mv) 54 Table 4-1 Gain & phase errors and offset-suppression factor for SC delay circuits in Figure 4-3 (a)-(j) 78 Table 4-2 Gain & phase errors and offset-suppression factor for SC accumulator circuits in Figure 4-6 (a)-(d) 84 Table 5-1 FIR Coefficients for 3-stage video interpolating filter 106 Table 5-2 Power comparisons for 1 st -stage in AZ of Figure 5-6(a) and EC/P-CDS of Figure 5-6(b) 109 Table 5-3 Power analysis for 2 nd - and 3 rd -stage 110 Table 6-1 Tap-weight for multi-notch FIR system function 127

27 xxxii Design of Very High-Frequency Multirate Switched-Capacitor Circuits Table 6-2 Normalized capacitance value (ff) for FIR tap-weight 130 Table 6-3 Device size for Telescopic opamp and wide-swing biasing circuitry 134 Table 6-4 Noise contributions 138 Table 7-1 Signals in different layer of PCB 164 Table 7-2 Testing equipment list 165 Table 7-3 Performance summary of the prototype SC filter with also a comparison with the state-of-the-art CMOS SC filters 183