Delivering VLSI chips to HEP experiments. A. Marchioro / CERN-EP Amsterdam - September 29, 2003

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1 Delivering VLSI chips to HEP experiments A. Marchioro / CERN-EP Amsterdam - September 29, 2003

2 Some undisputable statements 1. LHC experiments would just not be possible without ASICs 2. and this is true also for future HEP experiments 3. Total amount spent in DMILL is: 11 LHC magnet-euros (1) Total amount spent in 0.25 µm is: 6 LHC magnet-euros 4. If any improvements will be introduced in LHC+ experiments, ASICs will again play a major role Higher detector granularity and better resolutions power reduction higher speed higher density more radiation resistance (1) Data from 1997 until May LHC special monetary units is defined from corridor rumors LECC2003-Amsterdam A.Marchioro/CERN 2

3 Outline Introduction and Theme Benefits of ASICs History and Lessons learned Activity profile Relationships with suppliers Moving forward Technical challenges What are the expected costs Conclusions Reticle Reticle from from MPW8 MPW8 LECC2003-Amsterdam A.Marchioro/CERN 3

4 Theme of the talk The first years of VLSI design in the community was organized mainly as a fancy R&D activity Wish: Bring this activity to the level of a reliable, affordable and customer-oriented design service Question: How to organize the community of designers in the future within HEP as to provide: The best chips for experiments Higher performance Both in terms of physics results and electrical parameters More robust and reliable circuits Within the shortest design cycle But Without killing creativity and frustrating innovation Within budget LECC2003-Amsterdam A.Marchioro/CERN 4

5 Historical Comparison UA LEP LHC LHC+ Standard, dedicated and custom microprocessors Some Large utilization of first generation Pervasive Technology evolution Custom Integrated circuits Not used Few Large utilization of first generation Pervasive Technology penetration LECC2003-Amsterdam A.Marchioro/CERN 5

Fascination of The Small 0.8 µm 0.25 µm Contact in 1978 0.

25 um: um: Inverter @ 100 100 MHz: MHz: 5.5 5.5 uw uw 0.13 0.

6 Fascination of The Small 0.8 µm 0.25 µm Contact in µm Power Power consumption: um: um: MHz: MHz: uw uw um: um: MHz: MHz: uw uw P1262 SRAM Cell mm LECC2003-Amsterdam A.Marchioro/CERN 6

7 Summary of State-of-the-Art ADC (*) Tech # Bits Speed Power (**) Applic. Agilent 0.18 CMOS 8 20 GS/s 10 W Oscillo scope Stanford 0.25 CMOS 4 1 GS/s 70 mw Radar Broadcom 0.18 CMOS 6 2 GS/s 310 mw National 0.18 CMOS MS/s 69 mw Commercial Samsung 0.18 CMOS MS/s 123 mw UCB 0.35 CMOS MS/s 290 mw ChipIdea 0.25 CMOS MS/s 95 mw Radiation Tolerant (*) From ISSCC2003, (**)Analog core only LECC2003-Amsterdam A.Marchioro/CERN 7

8 Potential benefits The current limiting factor for many detectors is power dissipation Power (both Watts and Amperes) must be reduced using: New architecture New circuit design New technology All electronics related Material budget in CMS tracker LECC2003-Amsterdam A.Marchioro/CERN 8

9 Future areas of work Important Functional blocks Basic analog library All our designs are hand-made. Shorter design time requires parametrized models (Matlab etc.) Low power AD converters Very efficient and intelligent power regulators Simple chips: is a stock of 74XX compatible rad-tolerant chips desirable? Complex digital blocks Rad tolerant: DSP, FPGAs Memory/FIFO generator High speed (bi-directional) serializers Compact and efficient data compression modules Exotic chips/macros: RF transmission Optical modulation and switching Is CMOS the only technology we will ever need? Complex systems on chip Large Pixelated and monolithic detector Full calorimeter channel read-out with sophisticated signal processing Universal rad-hard control and monitoring chip-set for all detectors New flexible timing and trigger distribution system LECC2003-Amsterdam A.Marchioro/CERN 9

10 Outline Introduction and Theme Benefits of ASICs History and Lessons learned Activity profile Relationships with suppliers of HW and SW Moving forward Technical challenges What are the expected costs Reticle from MPW8 Conclusions Reticle from MPW8 LECC2003-Amsterdam A.Marchioro/CERN 10

11 Current service organization Supplier Tech Adm Other External Services (dicing, testing, packaging, etc.) Central Service CAD Service User 1 User 2 User LECC2003-Amsterdam A.Marchioro/CERN 11

MPW submissions (1) Total number of chips submitted: 184 Institutes involved: 20 MPWs statistics 25 20 10 9 8 N chips N Institutes N of chips per MPW 15 10 5 7 6 5 4 3 2 N of

12 MPW submissions (1) Total number of chips submitted: 184 Institutes involved: 20 MPWs statistics N chips N Institutes N of chips per MPW N of Institutes per MPW Reticle Reticle from from MPW9 MPW MPW1 MPW2 MPW3 MPW4 MPW5 MPW6 MPW7 MPW8 MPW9 MPW10 MPW11 (1) as of July 2003 LECC2003-Amsterdam A.Marchioro/CERN 12

13 MPW, Eng Run and Production Submissions "Project specific" engineering runs (red point: forecast) Number of runs Year Total different projects: 20 Institutes involved: 17 LECC2003-Amsterdam A.Marchioro/CERN 13

14 Production runs Total number of projects in production: 18 Institutes involved: 14 Production summary N of wafers produced N of wafers produced N of projects in production N of projects in production Y 2000 Y 2001 Y 2002 Y 2003 Y Forecast LECC2003-Amsterdam A.Marchioro/CERN 14

15 Prototyping vs. production needs prototype cycles needs (ASICs) Number of prototype cycles Number of ASICs needed 2 APV25 RAL_MGPA adc41240_full Atlaspix HPTDC CERN_gol IN2P3_HAL25 DTMROC-S CERN_LVDSBUF INFN-DCU PSI_CMSPIX RAL_Fenixv3 CERN_Alice_TOF CERN_LD2 PLL25 NEVIS_gainscore RAL-muxpll NEVIS_clkfo CERN_qxpll CERN_Delaychip CERN-CARIOCA Beetle Nikhef_Alcapone0 INFNCa_DIALOG INFNCa_SYNC CCU CERN_LVDSMUX Delta Paceam CERN_Pixel ATLASPIX-MCC INFNTo_pascal_v2 INFNTo_ambra_v2 Medipix CERN_OpAmp CERN_Analog_Mux OSSU_VDC4I5 OSSU_DORIC4I5 OSSI_OPTO NEVIS_scac CERN_RX40 otisdll LHCBPIX NIKHEF_ALABUF Kchip CERN_pilot CERN_Analog_pilot INFNBo_carlos CERN_na60_32_CH Rutgers_TBM RAL_CPR RAL-dfx RAL-apvb RAL_HEPAPS1 RAL_DSMBGN2 RAL_APVMUX3 RAL_CMSMUX1 RAL_Mdac40 Nikhef_pixadc2 CERN_rd49_nanopix SCT-test CERN_MONOPIX_1 CERN_apd CERN_asr1_b CPPM_T1XPAD Beetle1.2MAO bigpmos_chip Totem CERN_MIBEDO KIP_HDR CERN_CZTGE_17AC CERN_CZTGE_17DC60 CERN_CZTGE_17DC90 I2Cexpander Project 43 projects need more than 2000 pieces (20 more than 10000) 6 projects need between 100 and 2000 pieces 74 different chips integrated LECC2003-Amsterdam A.Marchioro/CERN 15

16 Lessons: Relationships with supplier Who are we? HEP is a technology driver in several areas: Magnets and cooling technology Particle detector technology IT (in some respect) But definitively not in semiconductor components Where are silicon foundries going? Are silicon ASICs generic commodity items In which areas do we need special relationships LECC2003-Amsterdam A.Marchioro/CERN 16

Capacity of semicon industry Capacity and Utilization Rates Worldwide IC Manufacturers 1999-2003 % Utilization 8 Wafer Starts %

17 Capacity of semicon industry Capacity and Utilization Rates Worldwide IC Manufacturers % Utilization 8 Wafer Starts % Utilization Capacity 8 Wafer Starts per week 1,000s Source: Semiconductor Industry Association LECC2003-Amsterdam A.Marchioro/CERN 17

18 Capacity of semicon industry (2) MOS Capacity by Dimensions WSpW x Q 00 3Q 00 4Q 00 1Q 01 2Q 01 3Q 01 4Q 01 1Q 02 2Q 02 3Q 02 4Q 02 1Q 03 >=0.7µ <0.7µ >=0.4µ <0.4µ >=0.3µ <0.3µ <0.3µ >=0.2µ <0.2µ <0.2µ >=0.16µ <0.16µ Source: Semiconductor Industry Association LECC2003-Amsterdam A.Marchioro/CERN 18

19 Why is it vital to have an excellent relationship with foundry? A very intimate knowledge of silicon manufacturing process is required for essentially all analog designs Example: monolithic pixel, ADC, APV25, bandgap, etc, etc Designs coming from our community have often special requirements : But often they are weak, or just about working with nominal process conditions Going from prototypes to production is NOT a smooth ride! Understanding yield issues requires strict collaboration with foundry LECC2003-Amsterdam A.Marchioro/CERN 19

Negotiation with foundry contacts at different levels to acknowledge the problem Negotiation on individual items (return of

20 Foundry interface (i.e. yield debugging) Example of debugging : yield issue Problems on several projects (APV25, Atlaspix, HAL25, Medipix) Negotiation with foundry contacts at different levels to acknowledge the problem Negotiation on individual items (return of material/replacement) Regular phone conferences Design of special test structures Visit to foundry Feed-back recommendation to users based on findings and learning CERN investment: ~ 6 man*months Foundry investment: >> 6 man*months LECC2003-Amsterdam A.Marchioro/CERN 20

21 Debugging chips Commercial Physical Analysis Lab Investment: Minimum equipment: > 2 M$ People: > 10 SEM Electron microscopy and metrology De-Layering Hot-spot analysis LECC2003-Amsterdam A.Marchioro/CERN 21

22 Relationship with tool supplier Two levels of additional complexity Analog: models (and transistors!) are increasingly more difficult Digital: Large number of gates Predominance of wires over transistor delays Well characterized digital library is absolutely necessary Tools were easy until ¼ micron generation, less than obvious for future generations Effort has been made on negotiating wafer costs, can we do the same for tools? LECC2003-Amsterdam A.Marchioro/CERN 22

23 Summary of lessons: What can go wrong (and should be avoided in the future!) Design stage Foundry Entire design done with out-of-date models Inappropriate selection of cells from library Wrong DRC set Insufficient/excessive layer filling Inexistent or insufficient circuit protections Inconsistent GDSII file (inconsistent cell naming) Wrong or forgotten masks Marginal process Wide Vt or other parameter spread Marginal metal planarization, etching Packaging Inappropriate pad opening, passivation choice Wafer dicing cut through chips Wrong mounting (rotated chips or empty packages) Wrong chip selection on MPW wafer LECC2003-Amsterdam A.Marchioro/CERN 23

24 Outline Introduction and Theme Benefits of ASICs History and Lessons learned Activity profile Relationships with suppliers Moving forward Technical challenges What are the expected costs Conclusions Reticle Reticle from from MPW8 MPW8 LECC2003-Amsterdam A.Marchioro/CERN 24

25 Moving forward ¼ micron technology is well established and well suited for first LHC generation 0.18 µm technology skipped due to lack of resources and marginal cost advantages 130 nm technology: significant benefits can be expected Need to evaluation Radiation Hardness design tools... understand costs LECC2003-Amsterdam A.Marchioro/CERN 25

26 Moore s Law was almost perfect Moore s Law in 1977 predicted a 57 wafer by 2003 LECC2003-Amsterdam A.Marchioro/CERN 26

27 Where is industry going Papers at ISSCC 50 Number of papers ISSCC 2002 ISSCC 2003 <90 nm 130 nm 150nm 180 nm.25 um.35 um.5 um.8 um Technology generation LECC2003-Amsterdam A.Marchioro/CERN 27

28 Complexity: extraction of parasitic C LECC2003-Amsterdam A.Marchioro/CERN 28

29 Increasing design complexity Example: Delay model in 0.8 µm technology = gate + Σ n δ load Delay model in 0.25 µm technology = gate + f(t rise ) + Σ n δ load + Σ k δ cap-wire Delay model in 0.13 µm technology and below = gate +f(t rise ) + Σ n δ load + Σ k δ cap-wire + Σ j δ Neighbors-activity n: number of nets in circuit k: number of capacitive cross couplings of nets in circuit j: number of cross-coupled switching neighbor nets LECC2003-Amsterdam A.Marchioro/CERN 29

30 Are HEP volume problems unique? $K per mask set ASIC/SoC MPU DRAM Mask Cost Wafer Cost Wafers per Mask Kind permission from: M. Rieger, Avant Corp. LECC2003-Amsterdam A.Marchioro/CERN 30

31 Relative cost of 130 nm proto run vs. ¼µ Comparison MPW prices (25 mm2) 500% 450% 400% 350% 300% 250% 200% 150% 100% 50% 0% 0.25 um Vendor A Vendor B Vendor C Vendor D MOSIS 0.25 Relative cost LECC2003-Amsterdam A.Marchioro/CERN 31

32 Are MOSIS/Europractice an option? Consider: What is the mandate of these services? Does it match the requirements for HEP experiments? Peculiar spectrum of requirements from our community Example: (1) CMS needs several circuits in quantities of 100,000+ at reasonably low cost (2) Alice needs 112 dedicated chips without which the Pixel readout would not work When you will have to repair/refit LHC in 2012(?), will MOSIS/Europractice still offer the same technology? If you have a yield problem, who will assist you? What if you want to deposit amorphous Si on a wafer? LECC2003-Amsterdam A.Marchioro/CERN 32

33 Macro-economy vs. micro-economy of chip design What are the economic deciding factors in the selection of a technology? Cost of wafers Cost of prototyping Cost of design System integration (what is the cost impact of a particular ASIC in a given system) How can one construct a formula that takes into account the real total costs of a design project for HEP? Can there be such a formula as to cover high and low volume projects? LECC2003-Amsterdam A.Marchioro/CERN 33

34 Where to focus our attention Importance of different cost contributions: Traditional HEP view Traditional industry view Future HEP perspective Cost of wafers Very High High (because of very high volume) Low Cost of prototypes Very High Low (irrelevant w.r.t timeto-market) High Cost of Design Low (in-house resources are almost free ) Medium (good engineers are expensive) Medium Integration of system Low Very high (the product is a system, not a chip ) Very high LECC2003-Amsterdam A.Marchioro/CERN 34

35 Next generation: What is needed Tools Design tools P&R tools at early stage of design P&R cost/license is in the 1M$ range Better verification tools: Electromigration, IR drop, substrate coupling, power analysis New well characterized Libraries Free from some vendor, RH (especially SEU) to be verified Submission At least 2-3 MPW runs per year People Expertise and know-how is exclusively in the mind of people Relationship with vendor This is not a commodity technology, don t select your supplier just on first order wafer cost!!! Coordination Much more coordination is needed among HEP Institutes LECC2003-Amsterdam A.Marchioro/CERN 35

36 Conclusions The future of instrumentation for HEP remains in microelectronics The last 5-6 years have shown that a good common service can be afforded if people in the community act coherently and with a long-range view In my mind, there is no way we can go beyond ¼ micron CMOS without a very special relationship with wafer and tool suppliers To continue to succeed in the future, we must master higher costs and complexities: Better system design prior to ASIC layout Shorter design time More reuse of common blocks Less NIH attitude Better architectural planning Sub-contracting to specialized design firms in one word: more collaboration LECC2003-Amsterdam A.Marchioro/CERN 36

37 Custom integrated circuits have profoundly changed the way front-end electronics systems are designed. Indeed, there is no other way to build most present high energy physics experiments A. Lankford, LECC 1999 LECC2003-Amsterdam A.Marchioro/CERN 37

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY