The MIT Communications Technology Roadmap Program

Transcription

1 The MIT Communications Technology Roadmap Program Silicon Platform Technical Working Group John Yasaitis & Mike Morse MIT Microphotonics Industry Consortium

2 Goal & Scope of the TWG The goal of this working group is to select the most important applications that could drive the development of an optically-enabled silicon platform, and flush out the challenges for achieving a successful market penetration. The scope of the effort will encompass both technical and economic analysis of the applications, but we will stay high enough to avoid competitive issues with specific process, device, or cost knowledge. Packaging issues will be not be addressed in any detail.

3 Transition to Optical Above 10GbpsxM Above ~ 10Gbps-M electrical losses limit useable SNR BW increases near transition zone possible but are increasingly expensive

4 Market Transition from Electrical to Optical Backplane and DVI/HDMI have interesting volumes and timeframe.

5 Volume Needed to Support Si Implementations Bandwidth Migration Current BW (hz) 1E12 1E11 1E10 1E9 Future BW 1E12 1E11 1E11 1E12 Interconnects 1E5 1E6 1E7 1E9 Wafers/week ,000 Volume drivers BW drivers High volumes are found at edge of the network

6 Initial Focal Topics Based on the team s size and skill set, we have decided to focus on 2 primary areas with a few other applications under consideration: DVI/HDMI/DisplayPort optical link between entertainment center and display (2-5 years out?). Data rates at 5 Gb/s potentially going to 40/60 Gb/s. Optical signaling for board and backplane communications (>5 years out?). Jerry s presentation will cover some more details on this. LAN products which could leverage lower potential cost and integration capabilities

7 Preliminary Roadmapping Discussions Opportunities To leverage the infrastructure of Si HVM to drive down the cost and potentially improve performance through integration. This would dramatically shift the supply and demand curves for the industry. Challenges Getting high enough optical performance from components Process integration of components Developing a reasonable business model for new opportunities Solutions If a solution was known, we wouldn t be here. Nevertheless Using the extra capacity of fabs that are already producing products profitably is an incredible strength that we can use for any solution that is found. Choice of Si platform and path of optical integration is key.

8 Vision for Research Key areas for technical work Understand high-level constraints of the applications under review for the silicon platform. Get consensus on key device structures that will drive the Si optical platform (i.e. optical couplers, modulators, Si-nc light emitters, WG s, Ge photodetectors, driver circuits, TIA s, etc.) High-level evaluation of processing complexity of individual devices and their integration. Evaluation of technical benefits of integration of electrical and optical components (i.e. PD+TIA or Demux+filters+PDs). Evaluation of relative merits and obstacles of monolithic vs. hybrid vs. 2-chip solutions ( and vs. time).

9 Division of Labor How the work will be broken up: Technical tasks will be done by the industrial participants and will include gathering benchmarks, and assessing the technical hurdles for both optical and electrical integration. Economical tasks would ideally be done by MIT students and would address economic aspects of the integration of components.

10 Participant Involvement Who should get involved? We need people with backgrounds in silicon processing, electrical and optical communications, and economic modeling. We would like to get a member from IBM and develop closer ties with the other groups to leverage their work. We are looking for additional members as well as guest speakers to address key Si optical integration issues.

11 Next Steps Where do we go from here: Gather more data on applications for 2-3 months and summarize conclusions. Start discussions on viable Si technologies to implement them in months 2-7. Engage with MIT student for economic analysis within the next 8 weeks. Evaluate technical aspects and barriers for optical integration in months Meeting times We will be meeting roughly every 4 weeks on Fridays at 3 pm EDT. Contact persons Mike Morse (Intel), and potentially Rick Thompson (BAE).

12 Delivering the Roadmap