Microphotonics: Hardware for the Information Age

Transcription

1 MIT Microphotonics Center Industry Consortium Microphotonics: Hardware for the Information Age 2005 by The Microphotonics Center at MIT. All rights reserved.

2 Acknowledgements Primary Authors Jerry Bautista Michael Morse Jeffrey Swift Intel Intel independent Participants * This report is based on the research of the MIT Technology Working group made up of the following members: Technology Working Group Chairs Jerry Bautista Michael Morse Jeffrey Swift Intel Intel Analog Devices / independent Participants Brian Lemoff Shrenik Deliwala John Yasaitis Jeffrey Kash Joseph Shmulovich Ed Murphy Richard Williamson Brent Little John Hryniewicz Bill Wilson Kevin Lee Alice White Roger Merel Elizabeth Bruce Luca Dal Negro Eugene Fitzgerald Clifton Fonstad Fuwan Gan Franz Kaertner Lionel Kimerling Frederick Leonberger Agilent Analog Devices Analog Devices IBM Inplane Photonics JDS Uniphase Lincoln Lab Little Optics Little Optics Little Optics LNL Technologies Lucent Technologies, Bell Labs Luxtera MIT MIT MIT MIT MIT MIT MIT MIT * Company names associated with participants are based on affiliation at the time of participation with the CTR program and may not reflect current affiliation. Microphotonics: Hardware for the Information Age Page 2 of 30

3 Jurgen Michel Rajeev Ram Harry Tuller Yiwen Emily Zhang Robert Hadaway Luciano Socci Edward Sargent Hank Blauvelt MIT MIT MIT MIT Nortel Networks Pirelli Labs University of Toronto Xponent Photonics Microphotonics: Hardware for the Information Age Page 3 of 30

4 Table of Contents Executive Overview...7 Scope and Definitions...7 Aim of this Roadmap Document...8 High Level Drivers for Silicon Photonic Integration...8 Why is So Much Bandwidth Needed at the Edge of the Network?...11 What About Copper?...12 Some Key Timeframes...14 Key Drivers Summary...14 Key Technologies for Silicon Photonics...16 Integrated Receiver Technologies...16 Technologies for Transmitters...18 Key Technologies for Modulators...18 Photon Source Strategies...20 Filter Technologies...22 Packaging and Interconnect Technology...23 Integration Technologies...26 Important Findings...27 Conclusions...27 References...30 Microphotonics: Hardware for the Information Age Page 4 of 30

5 List of Figures Figure 1. Distance bandwidth market map... 9 Figure 2. Exponential increase in clock frequency over time Figure 3. Basic architecture of personal computers Figure 4. Market transition from electrical to optical Figure 5. Key elements of an optical communications link Figure 6. Integrated silicon diode structure Figure 7. Diode structure for laterally-coupled germanium diodes Figure 8. Silicon plasma modulator approach and a Mach-Zehnder interferometer Figure 9. One approach to designing edge-emitting lasers mounded on a silicon platform Figure 10. Variation in transceiver cost versus volume Figure 11. Possible solutions for infrastructure reuse Figure 12. Low-cost interconnect system Figure 13. Proposed roadmap for silicon microphotonics List of Tables Table 1. Market transition from electrical to optical Table 2. Network bandwidth requirements and market volume Table 3. Key metrics for silicon microphotonic solutions to drivers Table 4. Hybridization and assembly-related laser sources Table 5. Silicon-compatible waveguide material options Microphotonics: Hardware for the Information Age Page 5 of 30

6 Definitions ASP CAD CMOS CODEC CPU CVD CWDM DARPA DVI, DV I/F FC FHD FLOP FTTx I/O I/P IC LAN MAN MAUI MBE MOSFET MOST MRAM MT MT-RJ MUX/DEMUX OADM PC PECVD POF QXGA ROADM SONET TBD TE TxRx VCSEL VLSI WAN WDM XFP Average Sales Price Computer-Aided Design Complementary Metal Oxide Semiconductor Coder-Decoder Central Processing Unit Chemical Vapor Deposition Coarse Wavelength Division Multiplexing Defense Advanced Research Projects Agency: Digital Video Interface Fiber Channel Flame Hydrolysis Deposition Floating-Point Operation Fiber-To-The-X Input/Output Internet Provider Integrated Circuit Local Area Network Metro Area Network Multi-wavelength Assemblies for Ubiquitous Interconnects Molecular Beam Epitaxy Metal-Oxide Semiconductor Field-Effect Transistor Media Oriented Systems Transport Magnetic Random Access Memory Mechanically Transferable Mechanically Transferable-Reinforced Jacket Multiplex/Demultiplex Optical Add/Drop Multiplexer Personal Computer Plasma Enhanced Chemical Vapor Deposition Plastic Optical Fiber Quad Extended Graphics Array Reconfigurable Optical Add/Drop Multiplexer Synchronous Optical Network To Be Determined Thermoelectric Transceiver Vertical Cavity Surface-Emitting Laser Very Large-Scale Integration Wide Area Network Wavelength Division Multiplexing 10 Gb small Form-factor Pluggable (transceiver) Microphotonics: Hardware for the Information Age Page 6 of 30

7 Executive Overview Silicon-based microphotonics has been under great scrutiny in recent years. The prospect of extending a massive, low-cost electronics manufacturing platform into the photonics domain is the subject of much research and debate. What has become clearer is that an important driver for the debate is the intrinsic distance bandwidth limitation of electronic communications links. In other application domains, photonic links are typically utilized once these electronic limitations have been encountered. Photonic link standards of many kinds have been developed to support such demands in the past. These standards represent a historical context for a silicon microphotonics roadmap and yet they may impede its development. A roadmap is starting to emerge focused not on how silicon microphotonics can implement existing standards, but rather on how silicon microphotonics supports the migration of network bandwidth in an important way. The key market driver for silicon microphotonics adoption will be significantly reduced cost, which will drive the transition from electronic to photonic interconnects. As was the case for VLSI, monolithic integration will be essential to reducing cost. Integration will achieve aggressive bandwidth scaling through both parasitic loss reduction and integrated functionality (e.g. WDM solutions). This roadmap reviews the fundamental strengths of silicon microphotonics, along with its questions and challenges, the likely fit in emerging applications, and the necessary infrastructure. This roadmap also discusses the importance of an industry roadmap for all participants. Scope and Definitions Silicon microphotonics seeks to build optical devices on the platform that has enabled Moore s Law: electronics-grade, single-crystal silicon. Beyond this, definitions diverge. At one extreme, hybrid integration on silicon involves the incorporation of non-silicon-based devices fabricated off-chip with microelectronic devices already integrated on a conventional CMOS silicon platform. At the other extreme, CMOS process-fabricated, monolithically-integrated silicon photonics achieves a complete set of microphotonic devices using processes available in existing CMOS fabrication facilities. The latter solution requires sources, detectors, and modulators, as well as passive components such as waveguides and filters, made from silicon and acceptable dielectrics and metals. Between the extremes, intermediate solutions span the spectrum. For example, CMOS-compatible, monolithically-integrated silicon microphotonics does not interfere with CMOS processing, but could involve post-processing outside of the accepted CMOS process flow. To provide a truly compelling solution, silicon microphotonics will likely need to achieve a high degree of monolithic integration with at most a small degree of hybrid integration (e.g. laser Microphotonics: Hardware for the Information Age Page 7 of 30

8 sources) in order to offer low cost and increased functionality. This will probably involve new photonic materials, (e.g. Ge, BaTiO 3, SiON, and so on) near the process backend. Although this adds manufacturing complexity, this trend is also occurring in advanced CMOS to allow Moore s Law scaling and new functionality, such as high-k gate dielectrics and MRAM s. Aim of this Roadmap Document The purpose of this document is to concisely identify technological drivers, barriers, and potential timelines to pervasive implementation of. It is not the intent of this Roadmap to identify which of the solutions are most likely to be adopted, nor to focus attention on potential solutions at the expense of other concepts. It is hoped this Roadmap will inspire additional innovative solutions. High Level Drivers for Silicon Photonic Integration Electronic communication links are impeded by fundamental physical loss mechanisms. These include dielectric losses and skin effect losses (all a function of distance and bandwidth). Near/far-end crosstalk and process technology noise limits aggravate these loss mechanisms. Shannon s law predicts that for any given signal strength (governed by process technology) there will be a maximum communication rate governed by losses and noise levels. As industries move to ever higher bandwidths, they also approach Shannon s limitations. Moving close to a fundamental limit usually involves ever-increasing costs. To ease cost pressure, many industries have chosen to find alternative technology platforms that do not suffer from the same physical limitations. For many industries, this choice has been to switch to photonics. Figure 1 shows a dividing line between industries currently operating in the electronics domain and industries that have switched to the photonics domain. A red zone is proposed to highlight the practical distance bandwidth limits of electronics. It is purposely made to indicate financial tradeoffs of technological solutions. For example, when Shannon s limit is reached in any given marketplace, bandwidth increases can continue by utilizing parallel channels, changing to lower loss interconnect material systems, or using repeaters. Each of these solutions changes the cost/performance curve, however, becoming increasingly expensive. Microphotonics: Hardware for the Information Age Page 8 of 30

9 1 THz 100 GHz 10 GHz 1 GHz RapidIO PCI- Express Backplane DV I/F Storage Area Free Space Metro Area Net Long Haul Net Photonic Domain 100 MHz 10 MHz 1 MHz Electronic Domain Cable 0.1 M 1 M 10 M 100 M 1 KM 10 KM 100 KM Figure 1. Distance bandwidth market map. Figure 1 clearly illustrates the reason the Long-Haul industry switched from electronics (over 25 years ago!). Long-haul distance bandwidth needs are well above the limits of electronic solutions. The Metro Area Network industry switched from electronics over 10 years ago, and the Storage Area Network industry switched from electronics over 5 years ago. Less clear are the points when Cable, DVI (Digital Visual Interface for computer displays), Backplane, and serial computer busses such as Rapid I/O or PCI-Express will switch over. What is clear, though, is that each of these industries is increasing demand for bandwidth, and that the demand will ultimately exhaust the practical capabilities of electronic solutions. If history is our guide, Table 1 can be used to estimate when electronic limitations will be reached utilizing standard PC board materials and likely signal processing techniques. Table 1. Market transition from electrical to optical. Industry Current BW Doubles every: Electrical Limit Transition Year Serial Computer Bus 2.5 GHz 4 Years GHz 12 Years Backplane 3.6 GHz 4 Years GHz 8 Years DVI (Display I/F) 8 GHz 4 Years 10 GHz Soon! Cable 200 Mhz (Shared with up to 50 subscribers) TBD ~200 Mhz (Shared with up to 50 subscribers) TBD Microphotonics: Hardware for the Information Age Page 9 of 30

10 Nontrivial reapplications of silicon manufacturing infrastructure will likely require a significant volume driver. Modern silicon fabrication facilities cost $1B or more. A volume driver will be needed to justify any significant process modification or material set change. Volume is also needed to sustain normal manufacturing process controls. Table 2 highlights volume opportunities seen in certain areas of the communications network chain. An assumption of 1000 devices/wafer is used in the calculations for wafers/week. Table 2. Network bandwidth requirements and market volume. Bandwidth Migration Current BW (Hz) Future BW Interconnects Wafers / week ,000 Volume Drivers BW Drivers Table 2 shows that attractive silicon wafer volumes may come from bandwidth increases at the edge of the network. Volumes are far less attractive away from the edge where the network is primarily optical now. Edge bandwidth increases will increase pressure for optical solutions and back up that pressure with volume potentials capable of sustaining an industry of silicon fabrication facilities. The potential market drivers here will be links within the box (rightmost column in Table 2) and to a lesser extent FTTx, where predictions of home passed by fiber in the US exceed 6.5M in 2008, with another 10M in Japan alone. For the latter application, a fragmented market, varying government regulations, and a large number of competitors will make this a very competitive environment. It is therefore highly desirable for any silicon photonics supplier to amortize investment in this and smaller markets across the very high volumes of the processor-scale distance applications. If this assumption is made, then the tighter specifications of the processor world will apply across the silicon photonics industry. In this case, we can see that attractive silicon photonic technologies will need to support data rates starting at 10 GHz (Figure 1). This implies that only today s latest silicon technologies (and therefore expensive fabs) will be suitable for photonic modification enabling fully integrated products. Microphotonics: Hardware for the Information Age Page 10 of 30

11 MHz 10,000 1, Microprocessor Clock Frequency Pentium 4 Processor Pentium II Processor Pentium III Processor 486 Processor 286 Pentium Processor Processor Figure 2. Exponential increase in clock frequency over time [1]. Why is So Much Bandwidth Needed at the Edge of the Network? It may be hard to say whether today s processing power is keeping up with today s applications or whether today s applications are only those enabled by today s processing power. What can be said is that processing power is following an exponential trend and is being consumed by friendlier computer interfaces and more intricate applications. New applications will likely continue to increase demand for processing power. I/P delivery of high definition video and speech recognition will continue trends already well established in the industry. Video and audio content processing ( Which of my videos has grandma and me? ) are currently well beyond the capability of current processing power. Utilizing the internet as one s hard drive will increase edge bandwidth demand significantly. Although continued demand for processing power is envisioned, there is a physical constraint emerging which will limit microprocessor clock speed increases: heat. Processor heat dissipation scales with clock frequency. With today s processors already dissipating 100 s of watts of power, continued increases in clock speed will become increasingly difficult and expensive to package and cool. The solution for the heat constraint is to change to parallel computing architectures. This technique has long been utilized in supercomputers, and is already becoming apparent in today s PC s. Figure 3 shows a basic architecture for today s popular personal computers. Although processing power is mainly contained in the CPU, the graphics display processor and memory management are already offloaded, along with other I/O control. This separation of computation creates significant interconnect bandwidth demands. Already bandwidths well into the red zone (Figure 1) are expected within the next 5 years. Microphotonics: Hardware for the Information Age Page 11 of 30

12 Estimated High Level costs AGP4X Graphics bus CPU Memory Controller Hub MCH Front side bus * Memory bus * Memory Requirements for : Data rates > 15 Gb/s per channel BER < 10^ -13 Voltage < 5 V Low power consumption ideally <100mW Distances <25 inches Cost/link < $5 Monitor Hard Drives PCI Express ATA LAN I/O Controlle ICH r Hub USB Peripheral 2.0 Devices Computer Interconnect Figure 3. Basic architecture of personal computers [1]. Beyond 5 years, processing power will continue to divide, with separate processing units expected for video CODECs, math processors, speech CODECs, and many more. An example of this multi-processor architecture is the Sony/IBM/Toshiba Cell processor in which several compute elements called synergistic processors (clocked at roughly 4 GHz) are interconnected with a high-speed bus architecture. The interconnect bandwidth is a significant challenge and ultimately may limit the number of processing elements that can be assembled. As in the architectures of Figure 3, there are severe bandwidth implications for this new architecture, with memory requirements for each processing element of 100 s of Gb/s. The bandwidth needed between the processing units scales directly with processing power (FLOPs). It is estimated that one byte needs to be moved for every equivalent FLOP that is executed. A 1- Tflop personal computer (only a few generations away!) will need 1000 Gb/s bandwidth. The graphic processor alone is expected to need > 80 Gb/s! Also of note is that today s QXGA video display standard (already > 8 Gb/s at 1 2 meters) is already in the red zone of Figure 1. What About Copper? Copper interconnect solutions set a baseline governing the key metrics of the red zone conversion. Copper bandwidth increases, through either parallel interconnect or through loss reductions, are subject to both economic and physical limitations. To achieve 10-Gb/s performance, FR4 board interconnect material will likely be replaced with much lower loss (and higher cost, roughly 4x) materials such as Nelco-6000, Rogers 4350, or similar. When this material substitution is made for FR4, initial estimates indicate optical versus Cu-based board-based interconnects are roughly on cost parity. Increased volume will drive Microphotonics: Hardware for the Information Age Page 12 of 30

13 down costs for both the optical and Cu platforms, but it is too early to determine which will be the eventual cost leader at these higher interconnect bandwidths. Loss reduction in these materials is not infinitely scalable, and crosstalk scales directly with increasing frequency. Most experts feel that copper interconnect limits will be reached in the GHz range for PC board materials at < 1 m distances. Analysis shows these limits imply a cost/link limit for copper interconnects at approximately $0.38 $1.5 per Gb/s. Photonic links will likely need to be competitive with these copper costs. This cost analysis does not take into account, however, the cost of re-tooling the PC board infrastructure and supply chain to produce new boards that incorporate optical waveguides and suitable connectors. Specifically, FR4 will likely remain as a substrate for traditional traces to distribute power and low level speed signaling. Ideally, an optical layer would be added that would provide high bandwidth pathways. In addition, the optical backplane should ideally be entirely passive. This necessitates that the electrical-to-optical conversion occur on the cards inserted into the backplane. An optical blind mate connector must then be developed to allow the easy and repetitive insertion of cards into the optical backplane. Standards, de facto or otherwise, must be put in place in order to amortize the large cost of retooling the infrastructure to allow for optical backplanes on FR4. Another potential advantage of optical backplanes is that optical waveguides can be crossed, while obviously electrical pathways cannot. This would allow interesting (and probably more compact) board layouts. Enterprise Distance: km Rack-Rack Distance: 1-100m 1 100m 10G Silicon >= 40G Photonics? 3.125G 10G 40G OPTICAL Board-Board Distance: cm Chip-Chip Distance: 1-50cm G 5-6G5 ELECTRICAL 3.125G 5-6G5 10G Cu Technology (B/W) Optical Costs 20G Transition Zone 10G 15-20G Figure 4. Market transition from electrical to optical [1]. Microphotonics: Hardware for the Information Age Page 13 of 30

14 Some Key Timeframes Figure 4 shows an estimate of when certain marketplaces may switch from electrical solutions to optical solutions. This estimate depends strongly on lowering the cost of optical solutions. The chart shows a transition zone where the costs of electrical solutions will cease to scale favorably and the timeframes when this inefficiency will occur. The advent of an optical replacement of suitable cost during this transition zone will enable earlier conversion. The absence of such a suitable optical replacement will delay conversion until the electrical costs become much higher. Key Drivers Summary In summary, the key drivers for silicon microphotonics can be listed as; 1. Bandwidth Cost: Key applications are entering the red zone where copper interconnect technology loses bandwidth scaling efficiencies. 2. Bandwidth Volume: Several applications entering the red zone (such as personal computing, display interface, and backplane) are dramatically increasing bandwidth and are capable of sustaining significant wafer production volumes of > 20K wafers/week. Some key metrics for silicon microphotonic solutions to these drivers are captured in Table 3. The columns highlight bandwidth (Gbd), cost, and power of some currently available solutions. The rows capture current capabilities of copper interconnect, serial optical interconnect (XFP standard), parallel optics (from Xanoptics web page), and the DARPA sponsored MAUI parallel interconnect research project. Red text indicates proposed targets for silicon microphotonic- based links. The purpose of proposing these targets is not to gauge the marketability of any particular product, but rather to draw some important conclusions about the high-level drivers. First, silicon microphotonics is likely to require latest generation silicon technology. This was not true, for example, when micromachining technology first appeared in the late 1980 s. While micromachining technology could take advantage of older generation fab technology, silicon microphotonics will probably need to deal with very high speed circuitry and therefore very fine line lithography (whether or not the photonics portion needs this capability!). Whether this circuitry is separable (hybridization) or not remains to be seen, but it is fairly clear that it will be present in microphotonic communication solutions. The Multiwavelength Assemblies for Ubiquitous Interconnects (MAUI) program is a DARPA-sponsored collaboration between Agilent Laboratories, Palo Alto, CA, and the University of Southern California, Los Angeles, with the goal of enabling fiber-to-the-processor by developing very-high-density optical interconnects and complementary metal oxide semiconductor (CMOS) interface electronics. It utilizes VCSEL/detector array and parallel fiber technology. Microphotonics: Hardware for the Information Age Page 14 of 30

15 Table 3. Key metrics for silicon microphotonic solutions to drivers. Gbd Cost/Gbd Power/Gbd Copper 20 $ mw XFP 10 $ mw Parallel Optics 245 to > 1T n/a 36 mw MAUI 240 n/a 3 mw Targets > 40 < $1 < 25 mw Second, it is likely that applications that have sufficient volume to drive the necessary process development will also require a low-cost structure. This cost structure is not apparent in today s state-of-the-art commercial optical links such as XFP ($5 10/Gbd). Such a cost structure is commonly found in monolithic silicon products packaged in molded enclosures (by default, because this is the status quo). The high level drivers for silicon microphotonics will not only increase pressure for monolithic integration, but also for a low-cost volume optical packaging and interconnect infrastructure. This infrastructure does not appear to exist today. There are, however, some emerging examples of volume optical markets with low-cost targets. The automotive industry appears to be embracing optical interconnects through plastic optical fiber (POF) and molded optical transceivers mounted on simple metal lead frames. Infineon has been quite active in the arena offering products in the $3 5 range capable of roughly 25 Mb/s over plastic fiber rings. The motivation for optical transmission in the automotive industry (known as telematics ) is primarily rooted in improved reliability/maintainability as well as simpler routing at significantly lower weight relative to complex wiring harnesses. Today, several high-end German luxury cars have optical rings carrying traffic associated with entertainment, safety, traction control, and engine monitoring systems with 10 s of low-cost transceivers per automobile. A standard has also been implemented among various vendors known as Media Oriented System Transported (MOST). The roadmap indicates bandwidths approaching 400 Mb/s, as well as up to 64 transceiver elements per ring. Deployment is likely to follow the path of advanced systems such as anti-lock brakes, with deployment broadening to mid-level cars and beyond with a commensurate dramatic increase in overall volume. Third, it is important to note that these key drivers contain no historical photonic context that is, there are few (if any) photonic standards or prior art governing the form and function of any particular solution in these new markets. This is possibly a significant asset over those industries with a great deal of reverse compatibility or standards proliferation (for example, current 2.5- GHz photonic links come in over 640 different flavors!). The nature of this advantage will be determined by how well the industry can work together to leverage common platforms, interfaces, and techniques. Microphotonics: Hardware for the Information Age Page 15 of 30

16 Key Technologies for Silicon Photonics The drivers highlighted in the previous section imply that the key technologies are those that implement a communications link, namely: Receivers (optical coupling, light guiding, detector, Ckt) Transmitters (optical coupling, light guiding, modulator/source, Ckt) Filters Packaging and interconnect strategy Source strategy Integration strategy Figure 5 illustrates these elements. In the following sections, this chapter will explore advances, feasibility, and key issues of silicon microphotonics to implement these functions. Transmitter Receiver DATA Laser Filter (adds tunability) Modulator (improved encoding) Optical Fiber Photo Receiver Drive Electronics + Transimpedance Amplifier (TIA) Figure 5. Key elements of an optical communications link [1]. Integrated Receiver Technologies Research is uncovering a variety of ways to utilize silicon platforms in receiver technology. Hybridization (mounting a detector on a silicon circuit platform) has already been commercialized by several vendors. Although silicon itself is a rather poor absorber at most popular communication frequencies (> 1 µm wavelength), its absorption depths at 650 nm and 850 nm (popular short range communication frequencies) allow lateral diode absorbers to be built, yielding reasonable results. Figure 6 shows an integrated silicon diode structure. Light is coupled from a fiber to waveguides deposited directly on the silicon substrate. These waveguides channel the light to the lateral diode, where the light is evanescently absorbed. This lateral diode Microphotonics: Hardware for the Information Age Page 16 of 30

17 structure insures sufficient distance for good light coupling efficiency, yet still provides high electrical response speeds. Speeds over 10 Gbd have been demonstrated, at coupling efficiencies > 50%. Optical Fiber Input p/n Diode Interface Optical Fiber Light Coupler Light Flow Waveguide Detector Silicon Circuitry Mode Transformer Waveguide Hydrex waveguide integrated to detector on Si substrate Figure 6. Integrated silicon diode structure [2]. Much work is being reported on processing germanium on silicon platforms for the purposes of building integrated receivers. Short germanium absorption depths open the possibility of normal incidence coupled diodes, and the responsiveness of germanium extends into longer popular communication wavelengths, including 1300 and 1500 nm. Under strain (relatively easy to accomplish given the 4% lattice mismatch between silicon and germanium) absorption extends to 1600 nm, capturing most, if not all, of the long range communication wavelengths. Germanium diodes can also be laterally coupled, as indicated by the diode structure of Figure 7. The higher mobility of germanium allows even faster response, with > 15 GHz being reported. Figure 7. Diode structure for laterally-coupled germanium diodes [1]. Microphotonics: Hardware for the Information Age Page 17 of 30

18 Key Questions for Integrated Receivers Some of the questions about integrated silicon receivers relate to how they will be packaged and interfaced. Interfacing to multimode fiber, for example, will likely favor normal incidence diode structures due to the difficulty of integrating very thick waveguide topology (>> 10 µm) on the silicon platform. Normal incidence will also likely require Ge due to its favorable short absorption depths and will have implications on packaging costs, which can play a major role in the overall solution cost structure. Single mode coupling, on the other hand, may favor lateral lithographically-defined coupling structures and be compatible with silicon diode detectors. Both of these may have favorable implications to cost. Germanium diode structures would still be needed, however, for longer wavelength (> 1 µm) detection, where telecommunication is today. An additional question for germanium is whether the intrinsic silicon lattice mismatch (4%) can be managed such that resulting defects do not unacceptably impair diode noise performance. In summary: 1. Will the interface to the diode detector be single mode, or multimode? 2. Will the wavelength be < 1 µm, > 1 µm, or both? 3. Can a low noise Ge diode be built on a silicon platform? Technologies for Transmitters Silicon s poor electro-optic material properties have made silicon-based transmitter technologies particularly difficult. Although hybridization techniques (mounting VCSELs on a silicon platform) have been commercially demonstrated, fully integrated transmitters are still viewed as many years away. Promising solutions for integrating transmitter elements will be discussed. Key Technologies for Modulators Several different integration schemes for silicon-based modulators are currently being researched. Perhaps the purest form is the silicon plasma modulator approach. This approach, highlighted in Figure 8 floods a silicon waveguide channel with carriers, altering the channel s refractive index. This refractive index change can be utilized in Mach-Zehnder interferometer structures to create light amplitude modulation. Bandwidth results to 1 GHz have been demonstrated. Higher bandwidth becomes increasingly difficult, as the plasma cavity size needed for high bandwidth operation starts to conflict with the waveguide core size needed for significant optical modulation. Analysis shows that small amounts of modulation (~1%) may be possible at 30 GHz or higher. Microphotonics: Hardware for the Information Age Page 18 of 30

19 oxide Silicon oxide Silicon Figure 8. Silicon plasma modulator approach (left) and a Mach-Zehnder interferometer (right) [3]. Other modulator technologies of interest include processing electro-optic materials onto a silicon platform. Materials such as barium titanate deposited on a buffer layer of magnesium oxide have shown some compatibility with standard silicon processing techniques. If successful, these techniques promise true optical modulation bandwidth scalability well beyond hundreds of GHz. The practical bandwidth limit of such electro-optic modulators will likely be governed by available electronics. Additional modulator research concerns quantum well structures in materials which might be compatible with silicon processing techniques. Silicon nanocrystals on silicon dioxide, for example, have shown electroluminescence and electroabsorption. Although still early in the research phase, this technology is worth watching, both as a possible modulator and as a possible silicon light source. Key Questions for Modulators As with receivers, some of the driving questions for modulator technology have to do with what the modulator interfaces with. Silicon plasma modulation and silicon receivers, for example, are probably incompatible. Light frequencies which can be absorbed by a silicon diode will also be unacceptably absorbed in a plasma modulator. Conversely, frequencies that are efficient in a plasma modulator may not be sufficiently absorbed in the silicon diode. Plasma modulators may need germanium diode processing capability to solve this dilemma. Electro-optic materials such as barium titanate do not have the same wavelength-driven requirement for germanium processing and also easily meet bandwidth scalability market drivers. The ability to integrate these materials with standard silicon processing is still very much in question, however. Quantum confined structures also have processing compatibility questions, but such questions are probably best held until demonstration vehicles with suitable performance capability have been shown in the lab. Microphotonics: Hardware for the Information Age Page 19 of 30

20 In summary: 1. Can hybridization of VCSELs on a silicon platform meet industry cost targets? 2. Will plasma modulation scale sufficiently in bandwidth and will germanium detector processing be compatible? 3. Can electro-optic materials such as barium titanate be integrated into a standard silicon processing flow with sufficient film quality? 4. Techniques 2 and 3 (above) probably require single mode light and lateral coupling. How will multimode be addressed? Photon Source Strategies Two classes of technologies for active optoelectronics are emerging in research laboratories. Each involves semiconductor particles controllably made on the nanometer length scale. One of these can be processed entirely from the solution phase, just as photoresist is spin-coated onto any substrate. Colloidal quantum dots have been synthesized in solution and processed, often in combination with a semiconducting polymer, to realize active optoelectronic devices compatible with any substrate. There are no lattice-matching constraints since the infrared emitters are fabricated prior to device fabrication. Materials such as InAs, PbS, and PbSe have been used in recent prototypes. This technology has been demonstrated to produce infrared active optoelectronic devices as reviewed in [4]. Electroluminescent devices have been shown with emission selectable between 1.2 and 1.6 μm and with quantum efficiencies exceeding 1%. Optical gain has recently been demonstrated at 1.3 μm at room temperature based on these solution-processed devices. Photodetectors with 3% quantum efficiencies have been reported, spanning the CWDM band, as has optical modulation at telecom wavelengths. A complementary emerging technology for active silicon optoelectronics is in the area of silicon nanocrystals. These consist of nanometer-sized crystals of silicon in a oxide matrix. They can be processed using existing CMOS-compatible technologies such as PECVD. They have been demonstrated to produce photoluminescence and electroluminescence, typically around 800 nm, but, through doping, this can be extended to 1.5 μm with the silicon nanocrystals acting as sensitizer. Net modal optical gain was reported in this materials system in 2000 [5]. Coherent sources capable of high speed modulation have, to date, only been demonstrated through hybridization. In these cases, VCSELs or edge-emitting lasers are mounded on a silicon platform and coupled into appropriate waveguides. Figure 9 illustrates one such technique. Cost-sensitive applications may benefit from locating the source off-chip, however. It may be more cost effective in many applications to have a central photonic power source analogous to an electronic power supply. This photonic source could feed many integrated circuits, without having the need for each chip to have its own laser. This architecture is similar to today s electronic integrated circuits where each chip is not required to carry its own battery! Benefits of such a source could include higher reliability, higher photonic power (to accommodate higher system losses), and increased functionality (multi-wavelength photonic sources). These benefits may not be substantial in a single optical link application such as a DVI display interface, but Microphotonics: Hardware for the Information Age Page 20 of 30

21 Laser Attach Laser 45 Facet Figure 9. One approach to designing edge-emitting lasers mounded on a silicon platform [1]. may become increasingly substantial in multi-link applications such as backplane and computer servers. Table 4 captures hybridization and assembly-related laser sources. Laser sources can either be very near, or even on, the IC (near source), or they can be centrally located (far source). Near source implies diode lasers which can be either direct modulation or continuous wave. Far source lasers will likely be continuous wave, or mode locked. Each of these possibilities creates different combinations of issues to be addressed. Direct modulation diode lasers will run at higher energy densities and are likely to have lower reliability. Continuous wave lasers will need to be compatible with on-chip modulation technology, implying polarization, mode, loss, and wavelength control. Centrally located sources have the additional constraint of being compatible with a mode maintaining distribution network. Key Questions for Sources 1. Will hybrid on-chip lasers be cost effective, reliable, and fast enough? 2. Can central photonic supplies be cost effective and efficiently interfaced? 3. Will silicon sources emerge with the required bandwidth, processing compatibility, and power? Microphotonics: Hardware for the Information Age Page 21 of 30

22 Table 4. Hybridization and assembly-related laser sources. Location Source Modulation Questions Near Source Diode Laser Direct Low Loss Lower Reliability Near Source Diode Laser External Low Loss Higher Reliability Polarization Control Mode Control Wavelength Control Far Source Solid-State Laser External Higher Loss Higher Reliability Polarization Control Mode Control Distribution Network Filter Technologies Although not strictly a requirement for a simple optical communications link, optical filters may play a vital role in interfacing and in bandwidth scalability. Since many modulation and detection schemes mentioned thus far are mode-dependent (polarization mode and/or propagation mode), mode filtering, or at least mode control, is probably needed at the inputs of receivers and at the optical source input of modulators. Additionally, bandwidth scalability is commonly achieved through the use of WDM (combining different wavelengths onto one channel). Such bandwidth scalability requires wavelength filters to both combine, as well as separate, the wavelengths in the channel. Fortunately, silicon-compatible waveguide materials have been readily demonstrated. A variety of material sets such as silicon oxinitride, Hydex TM, silicon/silicon dioxide, polymers, and more have demonstrated efficient optical waveguiding properties with index contrast ratios sufficient to build area-efficient structures. Ring resonator filters, grating filters, polarization splitters, arrayed waveguide filters, polarization converters, splitters, combiners, Mach-Zehnder interferometers, and more have all been demonstrated with success. Erbium doping has also been demonstrated to allow optical gain mechanisms. Commercialization of this technology (not yet combined with silicon transistor circuitry) is already well underway. Table 5 captures many of the options available. Since the required structures for filters and mode control seem readily feasible, the key drivers will be found in material attributes. Key attributes for a robust platform, demonstrated on several of the material sets mentioned above, include: Low intrinsic losses Index contrast that is adjustable in the range of 0 25% contrast Long term stability (changes smaller than 1 10 ppm) Compatibility with IC industry processing tools Processes which avoid annealing steps Microphotonics: Hardware for the Information Age Page 22 of 30

23 Table 5. Silicon-compatible waveguide material options [6]. Material ΔN (%) Propagation Loss (db/cm) Process Ge-SiO to 0.25 FHD, CVD SiON to > 25 CVD Ta 2 O 5 SiO to 1 Sputter Si:SiO 2 > to > 100 CVD InGaAsP 0 10, > to 5, 10 to 100 MBE Polymers to 5 Spin Hydex 0 25 < 0.15 CVD Key Questions for Filter Technology An integration strategy will drive the choice of material sets. Placement of the waveguide material in the resulting wafer stack will be likely be driven by the demands of the detector technology, modulator technology, and external interface technology. In summary, a key question is: 1. What is a compatible combination of detector, modulator, and interface elements, and what waveguide technology best interconnects them to each other and to the outside world? Packaging and Interconnect Technology Existing optical transceiver packaging technologies involve modular and hybridization techniques. Figure 10 shows the dramatic variations in the cost of these transceivers versus their volume. Although significant cost reduction progress has been made, the average selling prices of the lowest cost modules is leveling out at approximately $20. A significant portion of this cost is in the cost of assembly. Since we have identified cost requirements more than an order of magnitude lower, it is clear that a significantly different packaging and assembly infrastructure will be needed. Key attributes of this infrastructure are: Low cost (< $1) Uncooled package Non-hermetic Pick-and-place compatible Reflow compatible Edge and surface coupling Large lead count capable 2 12 fibers capable Microphotonics: Hardware for the Information Age Page 23 of 30

24 To achieve the cost structure, existing high volume infrastructure reuse is highly desirable. Concept pictures such as those in Figure 11 highlight possible solutions. These concepts seek to share standard I/C packaging infrastructure along with low-cost optical interface standards such as MT-RJ. Figure 10. Variation in transceiver cost versus volume [7]. Figure 11. Possible solutions for infrastructure reuse [8]. Microphotonics: Hardware for the Information Age Page 24 of 30

25 Figure 12. Low-cost interconnect system [9]. Such concepts only address a portion of the problem, however. A low-cost interconnect medium analogous (or compatible) to FR4 will be needed. Figure 12 shows an example of such a system from US Conec. This system features circuit sizes up to 1.8 m 0.9 m without splices, ribbonized legs for easy termination of multifiber connectors, and optional pre-termination of MTP, MT-RJ, and other MT-based connectors. Of course, electrical interconnects are also needed in the final system. Key Questions for Packaging and Interconnect Technology There is no universal package interface analogous to an electronic bond wire in photonics. As such, the design of the photonic interface of the package must be tied very closely to the design of the photonic interface on the integrated circuit. The same thing is true regarding the interface on the outside of the package. Additionally, there is no photonic equivalent to electronic solder. The design of the external package photonic interface must also be tied very closely to the design of the photonic interconnect. The individual costs of the IC, packaging, and interconnect will likely be influential in the final solution. Packaging decisions, such as hermeticity, normal or parallel light entry, mode management, and polarization management will probably interact strongly with IC processing decisions of waveguides, mode converters, detectors, and modulator structures. Likewise, package interconnect decisions of fibers, polymers, mirrors, and so on, will likely interact strongly with external photonic packaging interface decisions such as socketing, connector type, solder type, and electronic compatibility. In summary: 1. What combination of interconnect, packaging, and IC technology will achieve the required cost structure? 2. How will photonic interconnect strategies mate with electrical interconnect strategies? 3. How will packaging, interconnect, connector, and photonic IC companies work together to create the necessary infrastructure of the future? Microphotonics: Hardware for the Information Age Page 25 of 30

26 Integration Technologies The holy grail of silicon microphotonics is arguably all of the functions previously mentioned available on a high speed CMOS foundry process. Such a solution would find an ideal combination of compatible detectors, modulators, filters, sources, packaging, and chip interfaces that meet the demands of major market drivers. Different researchers are trying various angles of attack to achieve this objective. Perhaps the most enticing is to hold constant an available high speed CMOS process and see whether the necessary structures can be fabricated. This approach is being pursued by several companies and universities. Some of the problems of this approach involve the conflicting demands of receiver and transmitter technology. The optical wavelengths at which silicon can provide suitable detection (through absorption) are unlikely to be those which are best suited for silicon modulation. Additionally, silicon plasma modulation (a front runner for CMOS compatible silicon modulation) appears to have bandwidth scalability limitations which may miss major market drivers. These and other reasons have lead researchers to explore silicon material augmentation. Germanium deposition on silicon is perhaps a front runner for expanding the silicon detector spectrum. Germanium will detect well at optical frequencies at which silicon plasma modulators function. This does not, however, solve the problem of bandwidth scalability in plasma modulation. Electro-optic materials such as barium titanate on silicon are being explored to expand modulator bandwidth scalability. These electro-optic materials seemingly have orders of magnitude of bandwidth scalability beyond current market drivers. Silicon material system augmentation may have a significant impact on standard CMOS processing. Foundry availability of silicon microphotonics will be very limited until this process impact is fully understood. Work to determine the specific impact of each materials change on CMOS continues. If multiple materials need to be introduced, the combinational impact may also be unique (non-orthogonal) and exponentially complex. These combinations of materials need to be understood with respect to their positioning in a CMOS layer stackup, and consequently with the demands of the structures necessary to channel, filter, and interconnect the light on and off the chip. All of these interdependencies will likely require a concerted effort between materials, process, structure, packaging, and photonic interconnect centers of excellence. Key Questions for Integration 1. What integration roadmap will guide foundry development? 2. How will such a cross-functional roadmap be developed? 3. What infrastructure will foundries need to perform a silicon microphotonics service (i.e. design tools, metrology, etc.)? Microphotonics: Hardware for the Information Age Page 26 of 30

27 Important Findings In light of the questions raised in the preceding sections, there are a few things we do know. Copper interconnect will continue to dominate at lower frequencies. Even short range interconnect below 10 GHz will likely be copper for mainstream applications. This means that silicon microphotonics will need to be compatible with very high speed silicon circuitry (> 40 GHz). Older generation silicon fab capacity is unlikely to be usable in mainstream silicon microphotonic applications except for hybrid solutions. Market drivers for short reach interconnect do support the volumes necessary to support research and development on these latest generation silicon platforms. Conclusions Figure 13 shows a proposed roadmap for silicon microphotonics. The steps in the roadmap illustrate a natural, but not necessarily unique, progression. Each block sets the foundation and justification for the subsequent block. Unfortunately, subsequent blocks may uncover technology that impacts previous blocks. For example, identifying key market drivers (speed, cost, volume, wavelength, etc.) is a necessary prerequisite to determining suitable technology elements (transmitters, detectors, filters, etc.).certain element discoveries (e.g. all CMOS solutions) can greatly impact what we would consider suitable market drivers, however. Although Figure 13 shows a linear path, it is also re-entrant. Work must continually take place both upstream and downstream of where you believe your current location is. In this fashion, key interdependencies can be identified early and backtracking in the roadmap can be minimized. Identify Key Market Drivers Roadmap Discover / Demonstrate Suitable Elements Identify Integration Path Identify Package & Interconnect Infrastructure Develop Trial Products Develop Foundry Interface Grow Silicon Microphotonics Industry Today Time Figure 13. Proposed roadmap for silicon microphotonics. Microphotonics: Hardware for the Information Age Page 27 of 30