Envisioning the Future of Optoelectronic Interconnects: Production Economics of InP & Si Platforms for 100G Ethernet LAN Transceivers

Transcription

1 Envisioning the Future of Optoelectronic Interconnects: Production Economics of InP & Si Platforms for 100G Ethernet LAN Transceivers Communications Technology Roadmap MIT Microphotonics Center Shan Liu & Erica Fuchs

2 Table of Contents 1. Introduction: 1.1 Emerging Technologies: 100Gb Ethernet Application 1.2 Roadmap Motivation 1.3 A Case Study: 100Gb Ethernet LAN Transceiver 2. Competing Technology Solutions for 100GbE Transceiver 2.1 Material Platforms 2.2 Design Architectures 2.3 Current Modeling Effort 3. Methods 3.1 Previous Cost Modeling 3.2 PBCM Architecture and Capability PBCM on InP PBCM on Si 4. Design and Analysis 4.1 Phase I, Three Design (low to medium degrees of integration) Design Design Design Phase II, Si Data Collection (advanced integration) Two Chip One Chip 5. Cost Analysis 5.1 Phase I, Cost Modeling of Design 1, 2, and Phase II, Cost Modeling of Design 4 6. Summaries and Conclusion 7. Appendix Sematech Modeling Results for the Two Chip Design 8. Reference 2

3 1. Introduction 1.1 Emerging Technologies in 100Gb Ethernet Application The demand for bandwidth is increasing in many communication market segments. Advanced media applications, such as interactive TV and on-line gaming, enable higher user interaction and system interoperability, and therefore drive large demand for upstream and downstream channel bandwidth. According to Comcast, the shift from Broadcast to Unicast (personalized and interactive) services 1 would drive core network capacity. The current forecasts project that by year 2011 narrowcast and unicast services will be greater than 20% of all service offered. With the emergence of Web 2.0 and new interactive services on the horizon, enterprise, service and content providers have begun to search for the next generation Ethernet technology. (Saxena, 2007) In meeting these higher bandwidth demands, the current generation of high speed Ethernet technology, 10GbE, which was only widely deployed as of 2005, is already considered obsolete to satisfy future bandwidth-intensive applications. A new IEEE Higher Speed Study Group (HSSG) formed in the summer of 2005 is aiming to have a 100GbE specification by (Wirbel, 2006) The industry is focusing on what comes after aggregating 10GbE pipes. Parallel nx10gbps links have limitations on balancing load distribution. Questions have been raised on how many parallel 10Gbps links do you need to match usable bandwidth on one 100Gbps link. (Saxena, 2007) If there is a market for 100GbE, the industry is seeking a standardized and cost effective solution to facilitate its development and adoption. Commercializing 100GbE could be much more difficult than the 1 to 10 G transition. Our early interviews during Fall 2006 confirm that a common direction has not yet emerged. Everything is on the table at this point. Component companies have shown diverse approaches to design architecture, ranging from: We currently still are considering all options 10x10, 4x25, 2x50, and 1x100 We have decided some sort of photonic integrated circuit (using some amount of monolithic integration) is definitely the way to go. In the short-term, we believe a hybrid solution combining InP and Si will need to be used in our product. Whether in the long-term we will turn to all-silicon is still up in the air. The answer is clear. InP has already demonstrated low cost manufacturing of 100Gb parts. The IEEE HSSG January 2007 Interim Meeting further confirms that a consensus on a low cost, technologically feasible design has not yet been reached. 1 Broadcast services include analog video, digital broadcast, and digital simulcast. Narrowcast and Unicast services include DOCSIS, and Video-On-Demand. 3

4 1.2 Roadmap Motivation In contributing to the M.I.T. Communications Technology Roadmapping (CTR) effort, this study seeks insights into the long-term competitiveness of alternative 100Gb Ethernet technology and design strategies in the optoelectronics industry. The work aims to provide insights into strategic decision-making through quantifying the economic viability and operational hurdles to InP verses Si materials platforms and varying levels of integration. Process-based cost modeling is used to shed insights into the following three areas: a. Cost structure of InP and silicon technology design architectures. b. Technological requirements necessary to make each of these designs cost competitive in the 100Gb Ethernet market. c. Economic competitiveness of each design against its technological alternatives. 1.3 A Case Study: 100Gb Ethernet Transceiver This research investigates the manufacturing cost of emerging silicon and InP designs for a 1310nm, single mode, CWDM, 100Gb Ethernet LAN transceiver. There are a variety of 100GbE solutions being considered in industry. This paper provides an overview of 100GbE transceiver design in Section Two. To better understand the impact of integration on production costs, four designs are investigated: (1) a discretely packaged InP transmitter with 10 TO-CAN & a discretely packaged receiver, (2) a discretely packaged InP transmitter with 10 by 10G directly modulated laser (DML) array & a discretely packaged receiver, (3) a single package, hybrid transceiver with InP DML and detector array, and (4) a monolithically integrated optical die & InP DFB laser array. The details of these designs are explained in Section Four. A cost analysis of these four alternatives is presented in Section Five. Within this document, the scope of analysis for all four designs is limited to the front-end production of functionally equivalent 100Gbit per second devices. The backend assembly of each of these designs will be addressed in a subsequent study. 4

5 2. Competing Technology Solutions for 100GbE LAN Transceiver 2.1 Material Platforms Two key materials alternatives for optoelectronic device fabrication are silicon and III-V materials (Al, Ga, As, In, and P). Material selection is highly dependent upon a material s optical property, device performance, and level of component integration. At the two extremes, 100GbE transceiver designs involving advanced integration are: 1) An monolithically integrated photonic circuit in InP 2) A monolithically integrated silicon photonic circuit containing both active and passive optical components, using processes available in existing CMOS fab. (MPC, silicon, 2005) Many intermediate design choices are currently under development. Material options for each transceiver component are provided in Table 1: Table 1. Material Alternatives for Transceiver Components Key Component Light Source (Laser) Modulator Laser Driver Modulator Driver Mux/Demux, Waveguide PIN/APD detector TIA Material InP/GaAs, InP/GaAs, Si Si InP/GaAs InP, Si InP/GaAs, Ge, SiGe InP/GaAs, Si Transmitter Receiver III-V Group According to the 2005 CTR, out of the III-V group, InP was the optimum optical solution for device performance. (Clayton and Dudley, p 13) Several devices on an InP platform have already used integrated designs. These devices includes the following: -Tunable lasers and Mach-Zehnder modulators -DFB laser and Electro-absorption modulators -Photodetector diodes and TIAs -Waveguide mux/demux and laser, modulator -Waveguide mux/demux and detectors Despite a history of integration in InP, the current high cost of manufacturing integrated InP devices could be an obstacle for using this technology in commodity compute applications. At the time of the last CTR roadmap, and still today, there are few InP fabs capable of high volume manufacturing of integrated optoelectronic chips. (Clayton and Dudley, p 12) Major obstacles to high volume InP manufacturing include low 5

6 process yield, small wafer size (50 mm, 2 inch), and liberating engineers from the production line. However, if III-V technologies continue to demonstrate superior lasing performance over silicon, integrating in InP will need to be advanced to either compete with or be able to integrated with the necessary electronic components that can be done in CMOS Silicon Many traditional players in the compute industry believe that silicon photonics will have cost advantages over III-V technologies by leveraging the existing CMOS infrastructure. The cost of fabricating Si photonics can be reduced by achieving high yield on integrated devices, and machines capable of handling large wafer size (200 to 300 mm). Some of the key components contending to use Si photonics are modulator, light guiding components, and detectors. Much research is currently being done on processing Ge on Si platforms for building integrated receivers, as well as a Si plasma modulator. (MPC Silicon, p 17) Today, monolithic integration of photodetectors, mux/demux capabilities, tapers, and modulators, directly inserted at the CMOS gate level is an area of rigorous research in university labs and industry (see Design 4 & 5). 2.2 Design Architectures Numerous design solutions are proposed for 100GbE LAN transceivers. Two key design parameters are level of integration and system architecture. This section presents several technology and design choices widely discussed in industry. In our current study, we model three of these designs and at least one of the two more radical designs with higher levels of integration Technology Solution The current industry debates focus on what viable technology should be chosen for each transceiver component (Table 2), as well as what is the appropriate technology and architecture match (Table 3). Table 2. Technology Alternatives Component Technology Design Light Source (Laser) DFB, DML, EML, VCSEL, Edge Emitter 1. Direct modulation or continuous wave 2. On-chip or off-chip 3. Discrete TOSA or array x 10G, 4 x 25G, 5 x 20G, or 1 x 100G. Modulator EAM, MZI Mux/Demux, Waveguide, Filters AWG, Reflective echelle grating, ring resonator filters, splitters, combiners, thin film filters Receiver Surface PD/TWPD ROSA or flip chip 6

7 Table 3. Technology-Architecture Match Proposed by industry (APIC, Khodja, 2007) Architecture Function 4x25 Gbps 5x20 Gbps 10x10 Gbps Laser Array DFB/DBR 1300/1550 nm DFB/DBR 1300/1550 nm DFB/DBR 1550 nm Modulator Array External Modulation EAM/MZI External Modulation EAM/MZI DML/ EAM/MZI Mux/Demux Combiner/Interleave Combiner/Interleave/AWG PD/APD PD Array Traveling Wave PD Traveling Wave PD PS/APD CWDM/WDM CWDM CWDM WDM, 200GHz Integration Scheme There are many ways to integrate key components for 100GbE transceiver. Possible integration scheme include (see Figure 1): -Laser and modulator -Modulator, Mux/Demux, waveguide, and detector. -Mux/Demux, detector, and TIA - Modulator, Mux/Demux, waveguide, detector, and driver Laser + Modulator + Mux/Demux Waveguide + Detector + TIA + Driver Isolator Transceiver Integration Figure 1. Possible levels of integration for 100GbE transceivers. Different companies currently offer and/or propose different 100GbE solutions in the market. Finisar and CyOptics are considering discrete designs. The most discrete solution would be a separately packaged transmitter and receiver. In this case, the TOSA transmitter is created using multiple TO-CANs. The ROSA receiver is made of PIN diodes, with an AWG or PLC. (See Table 4 and 5) 7

8 Table 4. Discrete 100GbE Optical Solution (CyOptics, Hartman, 2007) Table 5. Discrete 100GbE Optical Solution (Finisar, Cole, 2007) Photonics integrated circuits (PIC) are commercialized in InP by Infinera (Figure 2). 8

9 Figure 2. a) A DWDM solution b) Photonic Integrated Circuit, transmit and receive chip c) Discretely packaged 100GbE transmitter and receiver (Infinera, Jaeger, 2007) As seen in Figure 2, Infinera offers separately packaged transmitter and receiver, each containing a PIC in InP. A DWDM scheme is achieved by integrating 10 by 10G lasers and modulators with mux in the transmitter, and 10 by 10G detectors with demux in the receiver. On the other hand, Luxtera and Kotura are currently considering hybrid-integrated solutions. An integrated 100GbE transceiver using CWDM technology has been proposed in the following scheme (Figure 3). The laser array and detectors are bounded on top of an optical die. Figure 3. Photonic Integrated Circuit, a CWDM solution; 100GbE transmitter in a single package (Kotura, Clairardin, 2007) 9

10 2.3 Current Modeling Efforts The CTR s current cost modeling efforts focuses on three representative designs in industry ranging from low to high level of integration. Two additional advanced integration schemes will also be discussed, and modeling efforts are in progress for the fourth design. A detailed discussion and analysis will be presented in Section Four and Five of the paper. 10

11 3. Methods 3.1 Previous Cost Modeling COO originated at Intel Corporation in the 1980 s during an examination of the total cost of acquiring, maintaining, and operating purchased equipment for semiconductor device fabrication. COO matured and was introduced to the mainstream through SEMATECH in the 1990s. SEMI E35 defines COO as the full cost of embedding, operating, and decommissioning, in a factory and laboratory environment, a system needed to accommodate a required volume (SEMI 1995). COO related the cost of acquiring and using a tool to the number of units produced over the life of the tool. (Sandborn, 2004) The basic concept of conventional COO is shown in the following equation (Nanez and Iturralde, 1995): Cost of Ownership = (Fixed Costs + Recurring Costs + Yield Costs)/ (Tool Life x Throughput x Composite Yield x Utilization) Which is simplified to: Cost of Ownership = (Cost To Produce Wafers)/(Number of Wafers Produced) In addition to commercially available cost of ownership software, such as the TWO COOL(R), which was commercialized through a joint SEMATECH/Wright Williams &Kelly project in 1994, SEMATECH also developed a Cost Resource Model (CRM). The CRM takes process flow from SEMATECH workshops, tool parameters, and fab rates as inputs, and outputs equipment requirements, fab costs, and wafer processing costs. The model assumes global factors such as building cost (construction, occupancy, and space), process cost (yield, silicon cost, depreciation rates, and operation hours), and personnel cost (manager, engineers, operators, technicians, and maintenance). Process flows (logic/dram/asic) are varied with technology nodes, ranging from 100nm to 250nm, and with wafer size. Starting with a defined wafer amount per month, the model calculates a total wafer cost and a total capital cost by summing tool capital, and cost associated with process step specific throughput, personnel per tool, and consumables. Conventional COO, has the advantage of helping a company understand funds required to purchase, run, maintain, and dispose of an investment. By incorporating equipment reliability, utilization, and yield factors, the COO method accounts for those irregularities that can ultimately determine economics. When the costs of all equipment are allocated to individual products according to the time increment used by a single product, there is, however, a problem of aggregation assuming that all processes are equally capital intensive. Furthermore, COO is based on historical data, like pure accounting methods. Assuming that future costs are similar to past costs is not a very good assumption when new product architectures, processes, and materials are the very thing under consideration. In comparison, the PBCM method was specifically developed for projecting cost for emerging product designs and processes. 11

12 3.2 PBCM Architecture and Capability The CTR PBCM allows the user to project and analyze for emerging technology prior to costly investments. The model, using basic engineering principles and industry data, first estimates required processing conditions. These estimates are used to project the resource requirements capital, labor, materials, and energy needed to meet specified production targets. These resource requirements can be mapped to corresponding operating and investment expenses and, then aggregated into unit cost figures (Figure 4). Ultimately, the model projects the minimum efficient fabrication line that is capable of producing a defined annual volume of good devices and then calculates the cost of installing and operating that line. The scale of the line is determined by the gross devices (both acceptable and rejected), which must be processes to achieve the desired annual volume of good units. (Fuchs & Kirchain, 05) Figure 4. PBCM Architecture The underlining equation for PBCM is: Cost per good device = Annual Cost of (material + labor + energy + equipment + tooling + building + overhead) / (annual good device produced) Each cost element is aggregated from per-process cost PBCM on InP Previous CTR modeling effort on InP focused on a transmitter - including an InP based laser and modulator. This model contains data in process modules describing 53 distinct processes. These 53 modules are shown, classified by process function, in Tables 6 and 7 below. 12

13 Table 6. Front-End Process Modules in the InP Transmitter PBCM Table 7. Back-End Process Modules in the InP Transmitter PBCM Each process module has sub-modules that are variants of the same process. For example, under Clean, sub-modules are incoming wafer clean and post-lapping clean. Each of these sub-modules can take in 26 inputs shown in Table 8. Table 8. Process Sub-Modules Inputs The current research effort builds on this existing PBCM with a new round of data collection. Since the last study, additional process modules are created to model the new 13

14 designs. Additional front-end modules include: Holography, Scribe/Wafer Cleave, and Bar Test. Back-end modules include Code and Label, Lens Staking, Adhesive Dispense, Lead Tinning, Lead Forming, Mount, Weld, Leak Test, DC Test, and Filter Assembly. Table 9. Front-End Process Modules in the Si Transceiver PBCM Front-end Back-end Holography Code and Label Scribe/Wafer Cleave Lens Staking Bar Test Adhesive Dispense Lead Tinning Lead Forming Mount Weld Leak Test DC Test Filter Assembly PBCM on Si This section also adds new Si process modules to PBCM in modeling an optical CMOS design (Design 4). Table 10 lists these new Si modules. Table 10. Front-End Process Modules in the Si Transceiver PBCM Surface Treatment Growth/Deposition Etch Lot Start Epi Growth (SiGe) Resist Strip Clean Ion Implantation a. 10:1(H2S04:H2S2O8) a. Epi Pre-Clean/ Deposition Pre-Clean a. High energy c. Plasma Asher b. Ozone/Anhydrous HF Clean b. Low Energy Oxide Strip c. Clean Megasonic Deposit Oxide Etch Si d. Post CMP Clean Deposit Taper Etch Oxide (Plasma Etch) CMP Sputter (metal) Etch Taper a. Polishing/Planarization PECVD Etch Apoly Laser Scribe Etch Metal Lithography Thermal Test Vapor Prime Anneal CD Measure Coat Resist Densification Measure Final CD Expose Deposit PolySi Inspection Develop Oxidation Ellipsometry Overlay Measure 14

15 4. Design and Analysis 4.1 Phase I, Three Design Phase I of this project models the front-end fabrication cost of three designs. These designs were chosen to represent low to medium degree of integration Design 1 The transmitter is made of ten 10G TO-CAN, individually aligned with thin film filters. The hybrid receiver is consisted of an AWG, 10 photodetectors and TIA. The transmitter and receiver are discretely packaged first, and then combined into an outer package. Figure 5. Design 1, TO-CAN Design 2 The transmitter is made of a DML array (InP monolithically integrated 10 by 10G lasers), and aligned with thin film filters deposited on triangular prisms. The hybrid receiver is consisted of an AWG, 10 photodetectors and TIA (same receiver as in Design 1). The transmitter and receiver are discretely packaged first, and then combined into an outer package. 15

16 Figure 6. Design 2, DML Array Design 3 A hybrid transceiver with a DML array chip (10 by 10G DML, same as in Design 2), 10 monitoring diode (MPD), and 10 detectors (III-V), all mounted on top of an integrated Si die with waveguide (including mux/demux). Figure 7. Design 3, Hybrid Transceiver 16

17 4.2 Phase II, Si-Platform Data Collection The flowing two designs are deploying advanced integration of photonics circuit, as well as photonic/electronic integration. Development efforts are underway at MIT s material science department. Early design ideas are also exchanged at the MIT Microphotonics Consortium Two Chip Figure 8. Design 4, Two-Chip The Two-Chip Solution refers to an optical chip and an electronic chip, separately packaged. The optical chip is a monolithically integrated photonic circuit comprised of waveguide, taper, Si modulator, and Ge photodetector. The light source would still be an InP DFB laser array, flip chip on top of the Si die. Process flow for this device is at 0.18 micron technology node. Cost modeling effort for the optical die is in progress. Early analysis is presented in Section 5.2. Data collection is underway to build up PBCM process modules mentioned in Table 9, Section Three One Chip The one chip solution uses the most advanced integration technique and is possibly the most suited for the compute space. The optical components are monolithic integrated with CMOS logic. The photonic single devices are only microns in size, including all of the required elements including waveguide routing, filters, modulators and detectors. 17

18 Some people believe this is the only viable approach for serious consideration for integration in CMOS electronics. Microprocessors are on the order of 10mm x15mm at 150nm (single core) and shrinking rapidly with node. The one chip solution is most likely to be sized about the same. The starting flow is based on 180nm using Al/Cu interconnect. Migration of the flow will be to 150nm and lower. Practical insertion for photonics is most likely at the 90nm CMOS node, depending on application performance. If 90nm does become the real insertion point, the real interesting application would be supporting communication requirements at even higher levels of electronic integration like multicore processors. (Beals, 2007) 18

19 5. Cost Analysis 5.1 Phase I, Cost Modeling of Design 1, 2, and 3 Section Three discussed the insights that can be gathered from the use of process-based cost models. The following figures and discussions give examples of these insights based on the PBCM of a 100GbE transceiver. The reader should note that the receiver (photodetectors, AWG and TIA) in Design 1 & 2 are not modeled by PBCM and only included in this analysis as a part cost. The cost modeling team is continuing to collect data on the processes being analyzed. As such, while the following analyses are demonstrative of the application of cost modeling, the cost figures should be considered preliminary. Quantify Impact of Economy of Scale Total Cost Comparison (front-end only) vs. APV Unit Cost Design 1 TO-CAN Design 2 DML Design 3 Hybrid Delta Graph of Design 1 & 2 using Design 3 as the baseline Unit Cost Difference Design 1 TO-CAN Design 2 DML Design 3 Hybrid APV 19

20 Total Cost Comparison (front-end only) vs. APV Unit Cost Design 1 TO-CAN Design 2 DML Design 3 Hybrid Figure 9. a) Cost Sensitivity to Annual Production Volume b) Unit cost difference between Design 1, 2, and 3, using Design 3 as the baseline c) Cross-over Sections As can be seen in Figure 9 a), production of all three designs show strong economies of scale up to annual production volumes of approximately 30,000 units. At annual volumes above 30,000 units, the production costs of all three devices level out: The TO-CAN design at just above $220 per unit, the DML array design at just below $150 per unit, and the hybrid transceiver at around $115 per unit. Figure 9 b) shows Design 2 is always more costly than Design 3, but Design 1 has a crossover with Design 3 around 5,000 units. Figure 9 c) shows two cross-over points of the three designs in low production volume of 5,000 and 6,000 annual units. Design 1 starts with the lowest cost but gradually surpasses Design 2 and 3. Assumed final product yields are 3% for the TO-CAN device in Design 1; 0.26% for the DML array device in Design 2; and the same 0.26% for the DML array and 90% for the waveguide grating in Design 3. With the laser yields in the single digits and lower, even slight improvements or digressions within individual process steps can have significant consequences. 20

21 Cost Components Breakdown The cost model has the ability to isolate the dominant drivers of production cost. This information allows stakeholders to focus development efforts on these areas, leading to an efficient progression toward lower costs. The next two figures give examples of these insights in the model s early state. Figure 10 provides an aggregate breakdown of costs for the three designs at a production volume of 60,000 units per year. In this figure, costs are grouped into the following categories: Materials, Labor, Energy, Equipment, Tooling, Building, Maintenance, Overhead, and Other Purchased Components. For Design 1 and 2, Other Components include thin film filters, lens, monitoring diode (MPD), prisms, TIA, detector, and AWG. For Design 3, these components are MPD, detectors, and TIA. These components are a purchased cost in the model. Cost Breakdown Comparison at 60,000 (100GE components) Annually. Front-end Only Unit Cost Design 1 TO-CAN Design 2 DML Design 3 Hybrid Other Components Fixed Overhead Cost Maintenance Cost Building Cost Tooling Cost Auxiliary Equipment Cost Main Machine Cost Energy Cost Labor Cost Material Cost Figure 10. Cost Breakdown of the Three Designs According to Cost Elements Figure 10 shows how the cost breakdown by cost element differs for the three alternative levels of integration studied. Notably, the relative contribution of both the fixed (equipment, fixtures, building, maintenance, and overhead) and the variable (material, labor, and energy) is remarkably similar across the different devices. The focus of III-V component development has been on discrete active devices such as lasers and detectors, followed by development of passive devices, to include modulators, isolators, attenuators, and AWGs. Missing elements for fully integrated solutions include optical isolators, temperature control elements (such as Peltier cells), and filters with the performance of thin film dielectric filters. (Clayton and Dudley, 2005) For discrete solutions such as Design 1 & 2, eliminating discrete, costly components such as isolator and TIA would benefit from monolithic integration. Figure 11 displays a breakdown of device components across the three designs. 21

22 Cost Breakdown Comparison at 60,000 (100GE components) Annually. Front-end Only Unit Cost Receiving Components Isolator Light Guiding Components Laser 0 Design 1 TO-CAN Design 2 DML Design 3 Hybrid Figure 11. Cost Breakdown of the Three Designs According to Device Components The current assumptions on isolators are Design 1 deploying one isolator within each TO-CAN, 10 in total; Design 2 deploying one isolator in total; and Design 3 deploying none. Please note that these assumptions affect the final outcome of cost comparison and are subject to modification, depending on design requirements. Without considering the isolator cost, both lasers and light guiding components (filters, lens, MPD, prisms, AWG, and waveguide grating) account for the majority of the device costs. Laser Analysis The strongest comparison should be studied at the laser level, since all laser costs are outputs of the PBCM (no purchased component cost). Figure 12 shows the modeled cost for both the DML array and discrete laser. The DML array is modeled as consistently more costly than the discrete laser, at above $50 compares to $32 for the discrete laser at 60,000 annual units. Laser Cost Comparison (Front-End only) vs.apv Unit Cost APV-number of 100G components 10 discrete laser DML array Figure 12. Laser Cost Sensitivity to Annual Production Volume (front-end) 22

23 Laser Cost Comparison at 60,000 annual 100 GE components 60 Fixed Overhead Cost unit cost DML array 10 discrete laser Maintenance Cost Building Cost Tooling Cost Auxiliary Equipment Cost Main Machine Cost Energy Cost Labor Cost Material Cost Figure 13. Laser Cost Breakdown According to Cost Elements Figure 13 shows that material plays a larger role in the 10 by 10G DML array than in the discrete laser. This is due to lower device yield incurring additional waste of raw wafer inputs. The DML device also requires more costly equipments. The top two costs equipment followed by material remain the same for both designs. Top Cost Driver Although an aggregate breakdown begins to identify the cost drivers, to truly focus research and development efforts it is necessary to further isolate the causes of cost. Figures 14 compares the cost of each process group in the discrete laser and DML array production. Figure 15 and 16 show a breakdown of cost elements within particular groups of processes of each product. It is interesting to note that the top two cost drivers were lithography and other front processes. The DML array requires higher expense on lithography but lower expense on cleaving (breaking wafer to individual die) compared to discrete lasers. 23

24 Cost Comparison by Process Unit Cost Discrete Laser DML Array Lithography Other Front Test Cleaving Growth/Deposition Figure 14. Laser Cost Comparison by Process Discrete laser Top Cost Drivers by Process Unit Cost Other Front Lithography Test Cleaving Growth/Deposition Oth Fixed Equipment Oth Var Materials Figure 15. Discrete Laser Cost Comparison by Process DML Array Top Cost Drivers by Process Unit Cost Lithography Other Front Test Growth/Deposition Cleaving Oth Fixed Equipment Oth Var Materials Figure 16. DML Array Cost Comparison by Process 24

25 5.2 Phase II, Cost Modeling of Design 4 We are currently modeling Design 4, the Two Chip Si CMOS photonics solution in Phase II of this study. The process flow for this design has 150 process steps, including 9 layers of lithography steps. Progress has been made in the following area: 1) Identified thirty unique process modules for PBCM. See Table 9, Section Three. 2) Conduct on-going interviews with equipment manufacturers to understand equipment capabilities for new processes. 3) Identified necessary tool characteristics and possible tool for each process step with industry counter-parts. Worked with SEMATECH to identify initial tool costs, throughputs, consumables, footprint, downtime, maintenance, and labor for 200 mm and 300 mm tools. 4) Acquired from Cannon and ASML data on equipment cost, cycle time, load/unload time, floor space, labor, energy, downtime/maintenance, and yield for each of the 9 lithography steps. 5) Preliminary cost results are modeled with Sematech s data using Sematech s Cost Resource Model. Final wafer costs are $1712 for 300 mm wafer, and $1332 for 200 mm wafer. Detailed analysis is included in Appendix One. (Wright, 2007) Although these preliminary results provide interesting analysis and a first peak behind cost structures of fabricating the Two Chip solution, they are not robust under close examination. The following assumptions are made in CRM 1) Starting wafer amount = 20,000 per months; High Volume 2) Global yield = 95% 6) Assuming a global yield of 95% for an untested process flow may be highly optimistic. Early yield impact assessment for the photonics CMOS flow indicated two types of yield losses, systematic yield impact and defect driven yield loss. High-risk impacts of the new photonics operations are new Ge CMP process and the high thermal treatment impact to the CMOS performance. The impact on yield would depend on the temperature used and transistor capability requirement. In the worst-case scenario, large yield impact would result from transistor degradation alone. Estimates for defect driven yield loss were also assessed for the new operations based on historical experience with the 0.18um node manufacturing health. Estimate of the increased real estate required for integration on yield is made. (Haubensak, 2007) These potential per-process yield impacts will affect equipment utilization, material usage, and throughput for each process, thus changing the topology of the entire production line. This will change the product s process cost drivers as well as the final unit cost. 25

26 6. Summaries and Conclusion Ultimately, which material platform will be the future of optical interconnects is dependent on high performance and low cost. Reduced costs should open new markets and make existing optoelectronic applications resilient against new entrants. The modeling efforts to-date within the Communications Technology Roadmapping project have proven the ability to provide key insights into the potential for cost reduction within key devices and components. In particular, the process-based cost models which have been developed have served to quantify the impact of two important levers on production cost: 1) production scale, and 2) technological development in the form of device integration and processing differences across material platforms. Key insights from the current case study: I. The most expensive front-end process is lithography across all four designs, TO-CAN, DML, hybrid, and Two Chip. Other top cost drivers are raw wafer cost and machine cost. II. Production volumes above 30,000 units per year are critical to reaching economies of scale for TO-CAN, DML, and hybrid design. III. Yields are likewise essential to meeting cost targets. Below single digit yield in InP laser array can be an important concern for high volume manufacturing in the compute space. The interesting question lies in if Si photonics can achieve a mature yield in the 90 percentile as in standard CMOS process with the introduction of new material and processes. IV. The benefits of integration are drastic if integration can lead to the eliminations of costly, discrete components. For example, although the TO-CAN design uses cheap discrete lasers, it is the most costly design due to the needs of multiple isolators and other separate light guiding components. Furthermore, integration will lead to savings on back-end packaging and assembly cost. Moving forward this project aims to continue to explore these questions by modeling the front-end production of Si photonics Two Chip solution for 100Gbits Ethernet LAN transceiver. Particular focus will be given to inputting per-process yield, equipment cost, cycle time, load/unload time, downtime/maintenance, floor space, labor, energy, and material in PBCM, and then compare the model outputs with the first three designs, as well as benchmark with Sematech s model outcome. The last stage of the project will incorporate cost associated with back-end packaging and assembly. A final cost comparison of the four designs will be presented. In the end, this set of analyses will provide insights into the most productive strategies scale, material platform, and integration technology for pushing down optoelectronics production cost. Firms should be able to both identify those most effective strategies as well as quantify the necessary changes in performance necessary to reach key cost targets. 26

27 7. Appendix Sematech Modeling Results for the Two Chip Design This section presents the cost modeling results on Design 4, the Two Chip solution from Sematech s Cost Resource Model. These results are not yet accurate for a rigorous cost comparison. As discussed in Section 5.2, the number of good die/wafer can vary greatly with per-process yield. Most importantly, these results cannot be directly compared with the previous PBCM results of the three designs in section 5.1 due to different assumptions made in PBCM and CRM. The next stage of this study is to input process data into the CTR PBCM for Design 4, then benchmark the new results with Sematech s outputs. Sematech Cost Results, 200 mm Cost/Wafer Clean CMP Dielectric Etch Etch Scribe Implant Litho Metrology Litho_248 Metal Thermal Metrology Indirect Material Direct Material Indirect Space Direct Space Indirect Personnel Direct Personnel Tool Maintenance Process Tool Depreciation Sematech Cost Model Results, 300 mm Cost per Wafer Clean CMP Dielectric Etch Etch Scribe Implant Litho Metrology Litho_248 Process Metal Thermal Metrology Indirect Material Direct Material Indirect Space Direct Space Indirect Personnel Direct Personnel Tool Maintenance Tool Depreciation Figure 17. Sematech Cost Model Result for Design 4 (excluding raw wafer cost) a) 200 mm wafer b) 300 mm wafer 27

28 Figure 17 shows a breakdown of cost elements within particular groups of processes for both 200mm and 300mm wafer size. The top two cost drivers were lithography and etch. Other trends are consistent in both wafer sizes, with 300 mm being the more costly choice. Sematech Model Results (excluding raw wafer cost) Cost per Wafer mm 300mm Tool Depreciation Tool Maintenance Direct Personnel Indirect Personnel Direct Space Indirect Space Direct Material Indirect Material Cost Element Figure 18. Cost Breakdown by elements, Sematech (excluding raw SOI wafer cost) Figure 18 shows a breakdown of the cost elements. They are ranked in Table 11: Cost Ranking 300 mm 200 mm 1 Tool Depreciation Tool Depreciation 2 Tool Maintenance Direct Space 3 Direct Space Indirect Material 4 Indirect Material Tool Maintenance 5 Direct Material Direct Material 6 Direct Personnel Direct Personnel 7 Indirect Personnel Indirect Personnel 8 Indirect Space Indirect Space Table 11. Cost Ranking Comparison The 300 mm machines require a higher tool maintenance cost. Table 12 provides final wafer costs from CRM s outputs. Cost Wafer Size 300 mm 200 mm SOI substrate cost $950 $750 Wafer Cost $1712 $1332 Table 12. A Rough Estimation of Wafer Cost from the Sematech Model. 28

29 8. Reference Bautista, Jerry, Michael Morse, and Jeffrey Swift. Microphotonics: Hardware for the Information Age Silicon Microphotonics. MIT Microphotonics Center Industry Consortium, 2005, MIT. Beals, Mark, message to author, March 6, Clairardin, Xavier. Roadmap to 100 GbE, a CWDM Solution. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Clayton, Richard, and Thomas Dudley. Microphotonics: Hardware for the Information Age Integration in III-V Materials. MIT Microphotonics Center Industry Consortium, 2005, MIT. Cole, Chris. Technical Feasibility of SMF & MMF 100GE Transceivers. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Fuchs, Erica, Bruce Ram, and Randolph Kirchain. Process-based Cost Modeling of Photonics Manufacture: The Cost Competitiveness of Monolithic Integration of a 1550-nm DFB Laser and an Electroabsorptive Modulator on an InP Platform. Journal of Lightwave Technology, Vol. 24, No.8, August Fuchs, Erica, and Randolph Kirchain. Consolidate? Integrate? Go East? Or Get Out? Mapping the Cost Drivers in Optoelectronics Production. MIT Microphotonics Center Industry Consortium, 2005, MIT. Fuchs, Erica, and Randolph Kirchain. Understanding the Economics of Integration: Process-based Cost Modeling of Optoelectronics Production. MIT Microphotonics Center Industry Consortium, 2005, MIT. Hartman, Robert. Photonic Integration Circuit (PIC) Alternative s for 100GE. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Haubensak, Frederick, presentation to author, April 8, Jaeger, John, and Drew Perkins. 100G Ethernet, Technical Feasibility & Reliability Support for WDM SMF PHY Approaches. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Khodja, Salah. IEEE High Speed Study Group 100GbE Silicon Photonics Platform Considerations. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Nanez, Raul, and Armando Iturralde. Development of Cost of Ownership Modeling at a 29

30 Semiconductor Production Facility. Paper presented at IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Ragona, Sid. Cost of Ownership for Optoelectronic Manufacturing Equipment. Paper presented at Microsystems Conference, April 24, Sandborn, Peter. A Material Cost of Ownership Approach to Product Cost Estimation with Direct Application to Performing Life Cycle Assessment Concurrent with Cost Analysis. Proposal to the National Science Foundation Number , Saxena, Vik. Bandwidth drivers for 100 G Ethernet. Presented at the IEEE HSSG, Monterey, CA, Jan 17-19, Wirbel, Loring. Long Way from Lab to Real Life for 100G. Electronic Engineering Times, October 2, Wright, Robert, presentation to author, April 8, Wright, Williiams, and Kelly Applications of Cost-of-Ownership. (accessed November 20, 2006) 30

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