The Intimate Integration of Photonics and Electronics for Computing and Switching Systems

Transcription

1 The Intimate Integration of Photonics and Electronics for Computing and Switching Systems A. V. Krishnamoorthy Acknowledgements: - My colleagues at: - Bell Laboratories - AraLight - Sun Microsytems 1

2 Outline Applications > Architectures that challenge electrical interconnects > Parallel optical interconnects in the marketplace Technology > Intimate integration of lasers, detectors, and VLSI electronics > Progress and Performance First Product: High-density Transceivers > Challenges > Performance & Reliability Interconnects to the chip: optoelectronic switching > Architecture > System Integration 2

3 Penetration of optics into communications 1Mbps 10Mbps 100Mbps 1Gbps 10Gbps 100Gbps Bandwidth per fiber 10cm SM, DWDM or MM, Parallel Multi-mode, Parallel 1m SM or MM, Serial or Parallel SM, CWDM To the chip/package $3 Link Distance 10m 100m 1km 10km 100km SM, DWDM $10 To the box $30 Across central office, data centers $100 $300 Metro, access, cross-campus $1,000 Transceiver Cost (per Gbps) 1000km 10,000km Cross-country Trans-oceanic $3,000 $10,000 Year of Introduction

4 Data Firehoses stress the interconnect sub-system Where do data firehoses exist in systems today? What types of data firehose are difficult to implement with electrical interconnects? Journal of Parallel & Dist. Processing, Vol. 41, pp ,

5 External data firehose Terabit/s Terabit/s > Gather Data Directly from Sensors e.g., digitized radar, fusion of multiple data sources, memories, > Combine Multiple Smaller Tributary Streams Telecom switching systems Datacom switching (10m -to-5km Fiber home-runs ) Terabit/s Terabit/s Distribute Tributaries throughout the system (e.g. multistage switching networks) 5

6 Internal firehose Terabit/s O[N] O[N 2 ] O[N] > Replicate Input Data for Parallel Internal Distribution and Processing e.g., matrix-vector multiplication with fixed (or infrequently changing) matrix switching (with fanout - crossbar) matrix inversion artificial neural networks clock distribution 6

7 Recirculating firehose Terabit/s > Compare input data to internal database with fast repetitive processing recirculating internal fixed or slowly varying database modest input and output data rates incoming data matched to contents of recirculating data e.g.,content-based search, information retrieval, data mining 7

8 Electrical signaling favors small aspect ratios D. A. B. Miller and H. Ozaktas, J. Par. Dist. Comp., Vol. 41,

9 System architecture Conventional interconnect hierarchy is designed to minimize aspect ratio Chip-to-Chip MCM-to-MCM Board-to-Board Frame-to-Frame Cabinet-to-Cabinet (Optical interconnects in use today) Certain applications (e.g switching) are naturally characterized by large aspect ratio Chip-to-Chip Board-to to-chip Frame-to to-chip Cabinet-to to-chip (Increasing System Aspect Ratio) 9

10 Point-to-point fully-connected system processors or boards duplex optical fiber 16-node ribbon System links, probably 32 wide 10

11 Switched interconnection system processors or boards duplex optical 16-node fiber ribbon System links, probably 32 wide fiber bundle Optoelectronic/VLSI switching chip 11

12 Optics in the box today Line Card Applications Switch Card Applications Current Products: Smart Transceivers Future Products: Optics to the chip Transceiver Overhead Transceiver Backplane SerDes Processing SerDes Parallel CDR Framer/Mapper CDR Optics 600m Optical interconnect Backplane CDR Parallel Optics Switching Fabric Client Side Serial/Parallel Optics (VSR) Network Processor Line Card Switch Card 12

13 Photonics integrated with CMOS DISCRETE via Wire Bonding (Traditional Vendors) VLSI Communications and Switching Chips 2-Dimensional Array Integration Technology Platform Potential Benefits to Direct Integration: Higher speed interconnect (capable of >40 Gbps) Lower power consumption Smaller form factor Better performance jitter, crosstalk, EMI More reliable/higher yield process than wire bonding Only Proven method to integrate III-V materials with Silicon VLSI circuits 13

14 Opto-electronic integration choices Monolithic Hybrid Fusion Bonding Silicon Monolithic GaAs + Silicon GaAs devices on Si Wafer Si transistor, process GaAs GaAs Monolithic InP Monolithic Epitaxial Lift Off Epoxy/Polyimide Bonding Flip Chip Bonding Superstrate Bonding III - V EPI Si Electronics 14

15 Opto-electronic integration examples Process R&D Teams Description Challenges Silicon SOI GaAs + Si Univ. Rochester, UCLA, UCSD, MIT, Intel, Cornell, Columbia, Luxtera, Kotura, IBM, HP, Sun European Union Research Teams, Bell Labs, Optical emitters, detectors, modulators, and WDM components in SOI silicon Deposit GaAs photonic devices on Si VLSI wafer. Push wafer through Si Foundry. Or make Si first and then go through GaAs fab. CMOS compatibility of devices, process integration, and electronics integration Si Foundry must accept GaAs impurities into its lines. High temperature processing of GaAs devices GaAs Monolithic MIT, Bell Labs, FET-PIN detector (field effect transistor + PIN detector) yield and uniformity LEDs demonstrated, not demonstrated in lasers InP Monolithic Several Startups HBT PIN detector Very low yield. Not demonstrated in lasers. Epitaxial Lift Off Georgia Tech, UCSB, ASU Remove active membrane of photonic device and bond to circuit chip How to manipulate very thin membranes. Need large (high capacitance) bonding areas Superstrate Bonding Honeywell, Sanders, Martin Marrieta Bond photonic device to glass slide through which light emits after flip chip Two bonding operations. Glass slide induces stress. Need vias through GaAs substrate high parasitics (advantage use top emitters) Epoxy/Polyimide Bonding NTT, CSU Flip Chip bond GaAs epitaxial layers to silicon circuits using polyimide or epoxy, then remove substrate, finish processing VCSEL mesa, then process contacts Many processing steps after attachment of GaAs VCSEL to Silicon; yield; limited ability to optimize VCSEL characteristics Fusion Bonding UCSB, Agilent Labs, Bell Labs Process optical and electronic devices separately; integrate by heating to 400 deg. Small size of integration can t manufacture with a full wafer scale integration Flip Chip Bonding to Silicon on Sapphire Peregrine Semiconductor Flip-chip Bonding to transparent Sapphire substrate containing circuits (SOS process) Thermal characteristics. Custom silicon foundry. Flip Chip Bonding Plessey, GEC Marconi, Aralight, Teraconnect, CSU, ASU, Vixel Flip Chip Bonding to Silicon circuits, then substrate removal III-V substrate removal process. Must remove heat through Silicon chip 15

16 Example: Flip-chip photonics-on-silicon integration Before Bonding GaAs substrate p AlGaAs i MQW Optical Chip Stop Etch n + GaAs silicon Micro-bump Electronic Chip After Bonding & Substrate Removal Anti-Reflection coating epoxy K. W. Goossen et al., IEEE PTL, Vol. 5,

17 A unique flip-chip technology A. Thermal Compression Bonding 1) low bond temperature 2) Smaller CTE effects 3) Increased choice of materials 4) No reflow solder steps (flux high, temperature, self alignment) 5) lead free bumps : Arbitrary bond materials B. 10µm bump diameter 1) Lower capacitance and inductance 2) parasitic > 80 ghz 3) can contact individual device geometries 4) no limit to pitches > 10 µm 5) use of multiple dummy bumps local thermal management 17

18 Multiple flip-chip attachments are possible Flip chip bonding followed by substrate removal Multiple operations enable interleaved arrays Laser and photodetectors can be separately optimized 144µm 18

19 Advantages of integration 2-Dimensional Array Technology Platform Micro-bump technology with 4X reduction over conventional C4 Higher speed interconnect (capable of >40 Gbps) due to inherently lower electrical parasitics RC time constants <10 femtosec Lower power consumption due to removal of wire-bond pads and reduction of off-chip parasitics Smaller form factor single optoelectronic die versus multiple dies wire-bonded to each other Integration of 2-D array of lasers versus single row Integration of additional electronic functionality into optoelectronic die Better performance jitter, crosstalk, EMI removal of inductive wire-bond from integration (no antennae pick up) More reliable/higher yield process than wire bonding single step wafer-level integration versus individual die-level wire-bond Potential to use guided-wave or free-space optical communication VCSELs and Photodetectors directly attached to arbitrary VLSI circuits 19

20 Micro-bump flip-chip roadmap 10 1 Si Scaling Bump Diameter C4 process 10 2 Linewidth (microns) Line width ( µ m ) Si LineWidth Aralight Bump Bump Diameter (microns) Bump Diameter ( µ m ) Time (year) Can efficiently contact VCSELs, modulators, and PiNs Only interconnect solution that follows Silicon VLSI trends 20

21 Manufacturing platform III-V Wafer Wafer-Level Photolithographic Micro-bump Bonding Results in a Wafer-Level Single-Step Single Chip and/or Array: opto-electronic integration, optical alignment and packaging, and testing Silicon Wafer (diced) which enables a lower cost manufacturing platform for single channel, linear array, and 2-D array optoelectronics 21

22 Bell labs flip-chip OE-VLSI mini-foundries Foundry 1 Used 0.8x0.8 cm die each containing 16 2x2 mm chips having 10x20 diode array Delivered 160 chips to various users in research community Foundry 2 Used 1x1 cm die each containing 21 2x2 mm chips having 10x20 diode array, and 1 4x4 mm chip having 25x48 diode array Delivered 110 chips to various users in research community 22

23 Reticle from 1 st foundry - 0.8um CMOS - 6 wafer devices 23

24 Reticle from 2 nd foundry prior to bonding Partial reticle shown - 0.5um CMOS - 8 wafer - >6000 devices 24

25 Batch fabrication for manufacturing Removal of Substrate Exposes Dicing Lanes 25

26 Mixed-signal VLSI chip with >1000 optical I/O 26

27 Device yield can be over 99.9% Forward bias illumination of 1024 modulator diodes 27

28 Process compatible with memory circuits 0.8µm CMOS 2mm x 2mm Die 11,500 transistors 1200Kbit/cm 2 t read = 6.2ns =>160MHz ns t write =8ns 2.5ns 28

29 High-speed dual-intra cavity contact design DEPOSITED MIRROR P-CONTACT N-CONTACT P + - LAYER STOP-ETCH LAYER N-LAYER L. Chirovsky et al., IEEE PTL, Vol. 11,

30 Early Work : 16x16 VCSEL array bonded to CMOS 256 VCSELs integrated with 0.5um CMOS chip Coplanar intra-cavity contacts w/ dielectric mirror 980nm VCSELs with through-substrate emission ARcoating III-V Substrate hυ Bottom Mirror N Layer Contact Solder Metalization Top Mirror Epoxy Active Layer P Layer insulation insulation metal 2 metal 3 insulation metal 1 polysilicon gate field oxide n+ n+ p+ p+ 980nm Emission through Substrate gate oxide p-substrate n-well 30

31 16x16 flip-chip bonded 850nm VCSEL array Response (db) mA 11.1GHz G 4.0G 6.0G 8.0G 10.0G 12.0G 14.0G 16.0G Frequency (GHz) 31

32 First product: ARL-36 optical backplane interconnect modules 240 Gbit/s O/E TX, RX Pair Product Features 36 parallel channels per module Total capacity 120 Gbps per module Data rate 155 Mbps to 3.3 Gbps per channel Designed for multimode fiber ribbon, 850 nm Transmission distance at least 300m Pigtail connectorized MTO/MTP options System level monitoring tools Single connector option reduces fiber-congestion Field-pluggable electrical interface Integrated fiber management C. Cook et al., IEEE JSTQE, Vol. 9,

33 ARL-36 Noise Floor 33

34 ARL-36 Rx 2.5Gbit/s No Neighbors Cross Talk Penalty 4 Neighbors 2.5Gbs, 2 23 Word Bit Error Rate -LOG (BER) Near Neighbors Next Near Neighbors BER = dbm dbm Attenuated Optical Power (dbm) (dbm) 34

35 ARL-36 Fiber Link: Bathtub Curve 2.5Gb/s PRBS 400m Fiber 1.00E E E E E E E-06 BER 1.00E E E E E-11 Eye opening: BER= E E E-14 Delay (ps) 35

36 ARLARL-36 Link Eye Diagrams (36 channels) Channel 1 Channel 2 Channel 3 Channel 4 Channel 13 Channel 14 Channel 15 Channel 16 Channel 5 Channel 6 Channel 7 Channel 8 Channel 17 Channel 18 Channel 19 Channel 20 Channel 9 Channel 10 Channel 11 Channel 12 Channel 21 Channel 22 Channel 23 Channel Gb/s OC48 Mask Channel 25 Channel 26 Channel 27 Channel 28 Channel 29 Channel 30 Channel 31 Channel 32 Channel 33 Channel 34 Channel 35 Channel 36 PRBS 36

37 Switching system reference design ARL-36 TX ARL-36 RX AraLight Daughtercard Vitesse switch board 37

38 Potentials for VCSELs-on-Silicon For Top Emitters 10 µm VCSELs have thermal impedance of 2300 C/W Measured thermal impedance of 10 µm aperture VCSELs when flip chip bonded to be 1000ºC/W Enables higher output powers and avoids thermal roll over Improved high frequency response above 10 Gbps Lower junction temperatures at a given drive current => improved reliability 38

39 Bottom-emitting VCSELs on ASICs at 3.3Gbps Difference = 6.3 C 1-channel on 36 channels on (ASIC power 100mW) (ASIC power 3.3W) 39

40 R&D Challenges for OptoElectronic-VLSI Switching Optics-to-the-Switch Architecture Dual integration Optical interconnect packaging Opto-mechanical packaging 40

41 Optoelectronic CMOS Crosspoint Switch Line Interface Switch Interface Fast, Memoryless Switch Fabric TARGET: 256 channels, <10Watts Sch OC-x Input Optoelectronic-VLSI CMOS Switch 16 Line Interface 4 3 GbE PHY SRI SRI SRI Line SRI 2 1 Interface GbE PHY GbE PHY GbE PHY GbE PHY x16 x16 Scheduler 41

42 Implementation: a bit-sliced switch Parallel Optics Transmitter P1 P2 Parallel Optics Receiver Bit1 Bit1 Bit K 1 K K Bit-Sliced Crossbars Bit K Multimode Fiber Ribbons OE-VLSI Switch Switch Output N x N Crossbar PN - Functions as a 16x16(x16) crossbar optical inputs, 256 optical outputs - 64 switch control lines (4 per channel) 42

43 Switch-on-a-chip architecture 1 N K Receivers... K Receivers K 32 x 32 x 1 32 x 32 x CrossBar N 1 x N CrossBar Switch CrossBar Switch Switch 1 N K Transmitters... K Transmitters Asynchronous Bit-rate Transparent Format Independent 2-R or 3-R modes Control Processor Non-blocking Scheduling/Arbitration Out-of-Band Control Fast switching (per packet) 43

44 Fiber bundle 1 16 Fiber Bundle Front View (facing bundle) hexagonal closepack multimode 50micron-core fiber terminated to MTP connectors on other end

45 System 512 fibers (256 in, 256 out) terminated into fiber MTP connectors 45

46 Penetration of optics into communications 10cm 1Mbps 10Mbps 100Mbps 1Gbps 10Gbps 100Gbps SM, DWDM or MM, Parallel Multi-mode, Parallel? Bandwidth per fiber 1m SM or MM, Serial or Parallel SM, CWDM To the chip/package $3 Link Distance 10m 100m 1km 10km 100km SM, DWDM $10 To the box $30 Across central office, data centers $100 $300 Metro, access, cross-campus $1,000 Transceiver Cost (per Gbps) 1000km 10,000km Cross-country Trans-oceanic $3,000 $10,000 Year of Introduction

47 Acknowledgements Jack Cunningham.. VCSELs and link Helen Kim Circuits and testing Keith Goossen.. Devices and integration William Jan... Processing Chris Cook... Optomechanics & packaging.. And many others. 47