III-V on Si for VLSI. 200 mm III-V on Si. Accelerating the next technology revolution. III-V nfet on 200 mm Si

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1 III-V on Si for VLSI Accelerating the next technology revolution 200 mm III-V on Si III-V nfet on 200 mm Si R. Hill, C. Park, J. Barnett, J. Huang, N. Goel, J. Oh, W.Y. Loh, J. Price, P. Kirsch, P, Majhi, R. Jammy Copyright 2010 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline Motivation Module level challenges Heterointegration Junctions/contacts Gate stack III-V on 200 mm Si VLSI compatible process flow

3 Application Spectrum Power and performance trends Lower Power Higher Performance Power (a.u.)

4 New materials and architectures Addressing the application requirements Ion Id Bulk CMOS SiO 2 /poly gate With Highk and Metal Gate Ioff Ig (gate leakage) Ij (junction leakage) Ioff Vg=0 Vg=Vdd Same Ion at lower Vdd Higher Ion at same Vdd Ion With high mobility channels Ioff With fully Depleted Si

5 MOSFET Tech. Gen. scaling trends Possible insertion point for III-V Planar 45nm High-K 32nm New materials 22nm? 16nm? Si-Ge Device III-V Device 12nm+ SEMATECH, VLSI 2009 Intel, IEDM 2007,9 SEMATECH, IEDM 2010 (Production) Intel IEDM Non planar (Production) Intel IEDM 2009 IBM, IEDM nm Length B. Doris IEDM III-V Insertion can be non-planar Intel Tri-Gate, VLSI 2006 NXP FINFET, VLSI 2007 SEMATECH, IEDM 2009 Nano-wire (LETI IEDM 08)

6 Module challenges for III-V on Si Gate Stack EOT< 1 nm, D it < 1e12, V th, ) Pitch ~55nm Contacts -CMOS Metals, ρ c < 1Ω.um -2 Wide-bandgap/dielectric barrier Hetero buffer for nfet STI Wide-bandgap/dielectric barrier Hetero buffer for pfet Junctions - shallow for SCE control and low R - X j <10nm, R sh < 100 ohm/sq Si substrate Hetero-buffer - µ n > 6000 cm 2 n s ~ 5e12 cm -2 ; defect density ~ < 1e6 cm -2 ; thickness < 0.5 µm

7 Modules - Heterointegration Options for III-V Planar Buffer Bonding ART ELO Metamorphic GaAs 0.5 µm Si substrate III-V III-V SiO 2 Si Img: 'E _130137B4AA_03_blanket_rot_s.dm3' MAG: 5kX Pro Process simplicity Ultra-thin buffer Potentially defect free solution using bulk wafers Thin buffer Con Buffer thickness Substrate cost Complexity Best results from 111 substrate literature results / T = 2 µm D = 1.3x10 8 cm -2 µ = 7800 cm -2 /V rms = 7.5 nm T = 0.01 µm D = NA µ = 7000 cm -2 /V rms = NA [Yokoyama, APE 2009] T = 0.2 µm D = defect free µ= NA rms = NA [Li, APL ] T = 0.1 µm D = NA µ= NA rms = NA [Hoshii, PSS DOI ]

8 Modules - Heterointegration SEMATECH planar buffer development Planar buffer development for rapid feasibility, infrastructure, module/device optimization Developing approaches including selective epi/bonding for CMOS in VLSI

9 Modules - Heterointegration QMSA characterization of HEMT buffer layers SEMATECH Confidential Standard Buffer Strain release Interlayers Reduction in peaks indicate high resistivity buffer Strong multiple peaks indicate parallel conduction and leaky buffer Little improvement in peak µ from 300 K to 77 K indicates defect scattering dominant 300 K to 77 K peak µincreases by 2x indicating phonon scattering dominant

10 Modules - Heterointegration TEM/AFM characterization of buffer layers SEMATECH Confidential Standard Buffer Strain release Interlayers 9.5 nm rms 7.5 nm rms Cross hatching evidence of strain relief by misfit dislocation

11 Modules Junctions Options for III-V FETs Beam line Epi S/D MLD Plasma Pro Industry standard process High Nd Abrupt junctions Zero damage Elegant Zero damage USJ Conformal Lower damage than beam line. Low energy for USJ Conformal Con Damage Profile Activation Process complexity Doping of S/D extension Under development Activation Under development SMT Results X j = 57nm R sh = 38 Ω/sq N d =1.5x10 19 cm -3 X j = 30 nm R sh =37 Ω/sq N d =3.5x10 19 cm -3 X j = 15.6nm R sh = 115 Ω/sq N d = 1.3x10 19 cm -3 X j = 9.4nm R sh = 36 Ω/sq N d = 6.4x10 19 cm -3

12 Modules Junctions Advanced junction technology for 11 nm tech. gen. Target for ~12-15 nm node Self aligned junction formation (without regrowth) meeting specifications for 11nm. Novel, Scalable and Manufacturable technology

13 Modules Contacts VLSI compatible metal contact down selection Down-selected Metals for evaluation Target SEMATECH actively evaluating [with encouraging results] Si process compatible metals for contacts to III-V in VLSI scheme

14 Modules Gatestack Optimization of HK and architecture N. Goel et.al., SEMATECH, IEDM 2008 Huang et.al., SEMATECH, IEDM 2009 HEMTs, Intel, IEDM 2007 [no High-k] μ Degradation w/ HKMG Modified MOSHEMT structures D it (10 12 ev-1cm -2 ) VB CB P-sub. 300K 200K N-sub. ZrO 2 1nm Al 2 O 3 /ZrO 150K 2 1nm LaAlO 3 /ZrO Energy in bandgap(ev) conventional surface channel MOSFETs SEMATECH developing low EOT, low Dit, high mobility gate stacks 12 October

15 200 mm VLSI compatible III-V on Si Processed on Si line at SEMATECH III-V on 200 mm Si wafer Fully processed transistor flow Systematic materials evaluation and process development on industry standard tool set

16 Summary Successfully developed a III-V on Si planar buffer technology with µ n = 7800 cm 2 /Vs. Excellent baseline for feasibility/infrastructure study, and module/device development. Demonstrated a fully VLSI compatible III-V process flow using industry standard Si toolsets without cross-contamination of the Si processing line.