Assessment of Technological Device Parameters by Low frequency Noise Investigation in SOI Omega gate Nanowire NMOS FETs

Transcription

1 15th UL Conference, ween, tockholm, April 7-9, 014 ession 5: Device characterization 11:50 1:10 Wenesay, April 9, 014 Assessment of Technological Device Parameters by Low frequency Noise nvestigation in O Omega gate Nanowire NMO FETs M. Koyama 1,3, M. Cassé 1,. Barrau 1, G. Ghibauo, H. wai 3, an G. Reimbol 1 1 CEA LET, MEP LAHC, 3 Tokyo nstitute of Technology

2 ntrouction - Low-frequency noise in MOFETs efect (charge trap) carrier (electron) chematic of planar MOFET Noise intensity (a.u.) Frequency (Hz) (a) M. von Haartman an M. Östling: Low-frequency noise in avance MO evices, pringer, 007. Noise sources in MOFET: Carrier number fluctuations (CNF) Mobility fluctuations (MF) n recent evices: CNF prevails nterface properties LFN measurement in MOFETs: Efficient iagnostic tool of interface properties ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014

3 ntrouction - licon nanowire MOFETs nanowire (NW) MOFETs High immunity against negative effects CE, DBL Gate ource Drain Better electrostatic control Lower OFF, teeper Tri-gate nanowire FET Avantages in further ownscaling an power consumption Aggressively scale FET (channel area) size Difficulty of etaile measurement/characterization (split C-V, charge pumping ) LFN measurement is applicable in scale MOFETs: Powerful iagnosis tool for ultra-scale nanowire evices ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 3

4 Purpose of this work Recent reports of LFN Application to scale multigate evices Double-gate, Tri-gate, Gate-all-aroun but few reports for Contribution of multiple surface orientation Technological evice parameters Tri-gate NWs W. Feng, et al., EDM 011. GAA-NWs Our stuy: O omega-gate NW MOFETs Contribution of surface orientation (N vs. sie-wall surfaces) Technological evice parameters (aitional H anneal, stressor impact) Detaile properties of LFN C. Wei, et al., Electron evice Lett., 009. J. Zhuge, et al., Electron evice Lett., 009. ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 4

5 Outline ntrouction & Motivation O starting omega-gate nanowire evices Experimental results LFN ( / ) behavior in 1ch-omega-gate NWs Flat-ban voltage noise Vfb Gate ie trap ensity N t N t separation: N surface vs. sie-walls - mpact of technological evice parameter - Conclusions ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 5

6 O Omega-gate nanowire MOFETs Technological splits: Channel material: or s [001] Ch. Orientation: [110] or [100] w/ or w/o H anneal process [110] poly H NW 5nm TiN HfON O [100] Gate Gate [001] ource ource [110] [010] Drain Drain C gc [F/m ] PMO EOT~1.5nm =10µm =10nm 50-channel =10µm V g [V] NMO High-k/metal gate stack: HfON/TiN (EOT~1.5nm) Technological splits of -gate NW NMO FETs NW height H NW Narrowest NW top with Gate length O ([110]-oriente) 11nm 13nm 113nm O with H anneal 10nm 11nm 107nm [100]-oriente O 10nm 10nm 108nm traine-o (so) 11nm 11nm 107nm ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 6

7 O Omega-gate nanowire MOFETs poly H NW 5nm -gate NW O ([110]-) with H anneal [100]- O so TiN HfON O V t 0.46V 0.4V 0.48V 0.40V [110] Gate [001] ource DBL (mv/v) ~3 [110] Drain (mv/ec) [100] Gate [001] ource gain on O 34µA/µm (V g =V t =0.9V) +13.7% +4.8% +98.8% [010] Drain (µa/µm) Normalize with W tot = +H NW V =0.9V = nm Narrowest NW V g (V) V =40mV O H anneal [100] -oriente so eal properties; ~60mV/ec & DBL<5mV/V traine-o (so) NW effectively enhances ON ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 7

8 LFN measurement in O -gate NW MOFETs Drain current noise PD measurement Expecte 1/f noise moel: Carrier Number fluctuations with correlate mobility fluctuations (CNF+CMF) moel 1 C eff C g m Vfb g m / vs. frequency shows 1/f noise in 1ch--gate NWs / (/Hz) =13nm, =113nm G. Ghibauo, et al., Phys. tat. ol.(a), vol.14, pp , V g =V t =0.46V V g =0.9V O -gate NW 5 evices V =40mV 1/f Average Frequency, f (Hz) ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 8

9 Normalize rain current noise / vs. 1/f noise moel: CNF+CMF moel 1 C eff C g m Vfb g m W tot / (µm /Hz) O [110]-oriente ( =113nm) =13nm =3nm [100]-oriente ( =108nm) =10nm =0nm /W tot (A) f=10hz V =40mV W tot (g m / ) (µm /V ) W tot = +H NW Goo agreement between / plots an the corresponing (g m / ) curves Our evices own to NW can be interprete by CNF+CMF moel ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 9

10 W tot / (µm /Hz) Normalize rain current noise / vs /f noise moel: CNF+CMF moel H anneal O ( =113nm) =13nm =3nm with H anneal ( =107nm) =11nm =1nm /W tot (A) f=10hz V =40mV W tot (g m / ) (µm /V ) 1 Goo agreement of / plot vs. (g m / ) curve in all technological splits Geometrical ifference between NW an wie FETs is not clearly visible W tot / (µm /Hz) C eff C g so m O ( =113nm) =13nm =3nm so ( =107nm) =11nm =1nm Vfb g m /W tot (A) f=10hz V =40mV W tot (g m / ) (µm /V ) ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

11 Flat-ban voltage noise Vfb : origin & extraction V fb fluctuations correspon to charge fluctuations in gate ie NMO TiN Traps HfON Flat-ban conition for NMO Flat-ban voltage: Carrier (electron) V fb ms V fb is equivalent to Q Q V fb Q C E c E f =E i E v Q C C V fb W tot / (µm /Hz) O [110]-oriente ( =113nm) =13nm =3nm [100]-oriente ( =108nm) =10nm =0nm /W tot (A) f=10hz V =40mV Vfb is carrier number fluctuations (CNF) component W tot (g m / ) (µm /V subthreshol (plateau) region 1 C g m g m Vfb eff C g m Plateau region Vfb g m ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

12 Extracte flat-ban voltage noise Vfb Vfb is carrier number fluctuations (CNF) component Vfb (V /Hz) f=10hz V =40mV = nm O H anneal [100]-oriente so 1/W tot W tot (µm) W tot = +H NW Vfb vs. W tot tren is similar in all technological splits Vfb simply epens on W tot (proportional to ~1/W tot ) ession 5: Device characterization, 11:50 1:10, Wenesay, April 9, 014 1

13 Gate ie trap ensity N t Flat-ban voltage noise Vfb Physical carrier trapping/e-trapping mechanism between ie charge traps an channel surface Tunneling process Vfb q fw ktn t L C tot g (McWorther moel) N t (ev -1 cm -3 ) ~0.1nm: Tunneling attenuation length A.L. McWorther: emiconuctor surface physics, University of Pennsylvania Press,1957. ~4kT Tunneling transitions of electron (i) Direct tunneling (ii) nirect tunneling via interface traps M. von Haartman an M. Östling: Low-frequency noise in avance MO evices, pringer, 007. ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

14 Extracte gate ie trap ensity N t N fw L tot g t q C kt Vfb N t (ev -1 cm -3 ) f=10hz V =40mV = nm W tot (µm) O H anneal [100]-oriente so W tot = +H NW No large alteration by both geometrical (NW vs. wie FET) an technological parameter impacts milar values to state-of-the-art Hf-base high-k/metal gate stack reports (10 17 ~10 19 ev -1 cm -3 ) ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

15 eparation of N t : N vs. sie-wall surfaces Assessment of contributions to ie/channel interface properties between N an sie-wall surfaces (W tot /H NW ) N t ( ev -1 cm -3 ) Oxie trap ensity N t W tot = +H NW ntercept: N t_sie-wall O H anneal [100] -oriente so (µm) N t_top /H NW N t _ tot W H [110] tot NW Gate [001] N W W ource top tot t _ tot N [110] Drain t _ top W H H W top NW [100] N Gate [001] Expecte simple moel NW tot t _ top ource N t _ siewall N [010] Drain t _ siewall Our moel for N t separation can be well emonstrate ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

16 [110] eparation of N t : N vs. sie-wall surfaces Gate [001] ource [110] Drain [100] Gate [001] ource [010] Drain N t ( ev -1 cm -3 ) (100) All (100) planes show constant value Our simple moel is reliable O N t_top N t_sie-wall so [100]-oriente H anneal (110) sie-walls are slightly better than (100) top surfaces Aitional H anneal process an tensile strain (so) slightly egrae (100) top surfaces M. Cassé et al., Appl. Phys. Lett., 96, 13506, 010. ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

17 Conclusions CNF+CMF moel can escribe 1/f noise behavior in all our evices Gate ie trap ensity N t is NOT altere by both geometrical an technological parameters The N t values are in the same orer as values reporte for state-of-the-art Hf-base high-k/metal gate stack N t separation (N vs. sie-walls) can be reliably performe: (110) sie-walls exhibit slightly better property than (100) top surface Aitional H anneal process an tensile strain (so) slightly eteriorate (100) top surfaces ession 5: Device characterization, 11:50 1:10, Wenesay, April 9,

18 Thank you for your attention 18