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1 IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Drain-Current Flicker Noise Modeling in nmosfets From a 14-nm FDSOI Technology Eleftherios G. Ioannidis, Christoforos G. Theodorou, Theano A. Karatsori, Sebastien Haendler, Charalabos A. Dimitriadis, Member, IEEE, and Gérard Ghibaudo, Fellow IEEE Abstract Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation CNF with correlated mobility fluctuations CMFs model accurately and continuously describes the 1/ f noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density S Vfb,eff and CMF factor eff, the CNF/CMF noise model can predict the transistor 1/ f noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations. Index Terms Low-frequency noise LFN, UTBB fully depleted silicon-on-insulator FDSOI MOSFETs. I. INTRODUCTION THE scaling down of the device area is essential for faster and better performance electronic circuits. In order for the CMOS technology to meet these requirements, new architectures were introduced to mass production, such as fully depleted silicon-on-insulator FDSOI, FinFET, and so on, to replace the planar bulk one [1], [2]. FDSOevices offer better control of the channel and have significantly lower threshold voltage variability, while maintaining compatibility with standard planar CMOS technology [3] [6]. On the other hand, low-frequency noise LFN is considered to be a very powerful tool to characterize the quality of the Manuscript received December 8, 2014; revised February 27, 2015; accepted March 7, This work was supported in part by the ENIAC Places 2 Be European Project, in part by the French NANO2017 Program, and in part by ARISTEIA II under Project 4154 within the Greek General Secretariat for Research and Technology through the European Social Fund and National Fund. The review of this paper was arranged by Editor Z. Celik-Butler. E. G. Ioannidis, C. G. Theodorou, and G. Ghibaudo are with the Laboratoire d Hyperfréquences et de Caractérisation, Institut de Microélectronique Electromagnétisme et Photonique, MINATEC, Grenoble Institute of Technology, Grenoble 38016, France ioannidis1980@gmail.com; christoforos.theodorou@imep.grenoble-inp.fr; ghibaudo@minatec.inpg.fr. T. A. Karatsori is with the Laboratoire d Hyperfréquences et de Caractérisation, Institut de Microélectronique Electromagnétisme et Photonique, MINATEC, Grenoble Institute of Technology, Grenoble 38016, France, and also with the Department of Physics, Aristotle University of Thessaloniki, Thessaloniki 54124, Greece tkarat@physics.auth.gr. S. Haendler is with STMicroelectronics, Crolles 38920, France sebastien.haendler@st.com. C. A. Dimitriadis is with the Department of Physics, Aristotle University of Thessaloniki, Thessaloniki 54124, Greece cdimitri@physics.auth.gr. Digital Object Identifier /TED gate interface, which is directly related to the performance of the electronic circuits [7], [8]. In addition, since the LFN level increases with the device area shrinking, excessive noise can lead to serious limitation of the analog and digital circuit functionality [9] [11]. Therefore, in order to improve the circuit design process, it is essential to understand and properly model the 1/f noise behavior of the newest technology nodes. In MOSFETs, it is generally accepted that the flicker 1/f -like noise originates either from carrier number fluctuations CNFs [12] or from Hooge mobility fluctuations [13]. The CNF noise is due to carrier exchange between the near-interface gate dielectric traps and the channel. The charge fluctuations in the gate dielectric could also induce fluctuations of the carrier mobility, giving rise to the so-called correlated mobility fluctuations CMFs [14], [15]. In thin-film transistors [16], as well as in single-gate MOSFETs, double-gate MOSFETs, and FinFETs [17], [18], it has been established that the 1/ f noise mostly originates from the CNF due to trapping detrapping of channel carriers into slow gate dielectric traps. A drain-current noise sources analysis in research-oriented FDSOI samples and an approximate extraction method have been presented in [19]. Nevertheless, a simple compact 1/f noise model valid for all operation regimes and bias conditions has not yet been developed for advanced FDSOI technology devices. In this paper, a detailed investigation of LFN in n-channel MOS devices from a 14-nm FDSOI CMOS technology node is carried out in all regions of operation, from weak to strong inversion and from linear to saturation. Based on measured data behavior, we constructed a simple front gate inputreferred noise model, which reflects the impact of the back interface to the front using certain coupling parameters. It is demonstrated that such generalized CNF/CMF model provides an accurate and continuous description of the 1/f noise for all operation regions in a single-piece formulation. An analytical CNF/CMF model has been developed, which enables the flicker noise level prediction of transistors with any channel dimensions, making it suitable for SPICE simulation tools. II. RESULTS AND DISCUSSION The devices measured in this paper are nmos transistors issued from a 14-nm FDSOI CMOS technology with channel width from 60 nm to 1 μm and gate length varying IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 IEEE TRANSACTIONS ON ELECTRON DEVICES Fig. 1. Ten dies-average drain current versus front gate for V b = 3 3V and V d = 50 mv for nmos W/L = 1/0.08 μm. from 1 μm downto20nm.

2 2 IEEE TRANSACTIONS ON ELECTRON DEVICES Fig. 1. Ten dies-average drain current versus front gate for V b = 3 3V and V d = 50 mv for nmos W/L = 1/0.08 μm. from 1 μm downto20nm.thegatelengthusedforthis analysis was the designed length in all cases. The front gate-stack consists of TiN/Hf-based oxide dielectric with equivalent oxide thickness t ox = 1.2 nm, while the silicon film thickness is 7 nm and the BOX thickness is 20 nm [20]. Static characterization was performed in order to obtain the transfer V g and output V d characteristics for front- and back-gate mode of operation and then extract typical MOSFET parameters such as transconductance g m. Time-domain sampling measurements of the drain current t were performed in the linear and nonlinear operation region as described in [21]. The spectra were obtained using an fast Fourier transform of the time-domain current measurements. The drain voltage V d was fixed to 50 mv for measurements in the linear region and the gate voltage varied from weak to strong inversion. In the nonlinear region, the gate voltage was fixed below and above threshold and the drain voltage varied from linear to saturation regime. The measurements frequency bandwidth obtained by the combination of three different sampling rates is from 0.5 up to Hz. It should be noted that all the spectra presented in this paper are the average of at least ten dies, thus suppressing the impact of RTS-induced Lorentzian-like spectra in small area devices. The analysis procedure is divided in three parts. First, we present the impact of back-gate bias on the device static characteristics and LFN, followed by a model approach proposal. Then, we examine the LFN in different operation regions of transistor, i.e., for different drain bias. Finally, we present the dependence of the two model parameters on the channel geometry. A. Impact of Back-Gate Bias In Fig. 1, the input characteristics of an nmos with W/L = 1 μm/0.08 μm in the linear region of operation, for various back-gate biases, are plotted. Note the change of the threshold voltage of the device for different backgate biases, both negative and positive. Same results were obtained for the transconductance values of the front- and back-gate interface Fig. 2. The transconductance of the front interface and back interface was calculated from the following equations, respectively: = / V g for a constant V b and g m2 = / V b computed for V b and V b 100 mv at agivenv g. Fig. 3 shows the drain-current spectra versus frequency for various back-gate bias values, from V b = 3upto3Vforthe Fig. 2. Ten dies-average transconductance versus front gate for V b = 3 3VandV d = 50 mv for a front and b back gate for nmos W/L = 1/0.08 μm. Fig. 3. Ten dies-average drain-current power spectral density versus frequency for a V b = 3VandbV b = 3 V back-gate bias and various front-gate biases for nmos W/L = 1/0.08 μm. Fig. 4. Normalized drain-current noise at f = 1 Hz versus drain current for V b = 0V,±3 VfornMOSW/L = 1/0.08 μm. The drain-current noise measurements were made in such a way to have the same region of drain current for all bias conditions. linear regime of nmos device with W/L = 1/0.08 μm. The shape of the spectra is clearly 1/f -like for all the bias conditions. Same behavior was observed for all back-gate and drain biases. The normalized drain-current noise versus drain current extracted at f = 1 Hz is plotted in Fig. 4 for V b = 0, ±3 V. The noise level variation seems negligible in the weak inversion region, while for high drain-current values, the noise level appears to be lower for positive back-gate voltage values. Since the dominant noise in the weak inversion region originates from the CNF and the CMF become important mainly in the strong inversion, we can assume that the backgate voltage is affecting only the CMF-related LFN. The standard LFN model used to explain the noise behavior in FDSOI technology node originates from the CNF model considering the two interfaces, the front one between gate/channel and the back one between channel/box S 2 2 Id gm1 gm2 = S Vfb1 + S Vfb2 1

3 IOANNIDIS et al.: DRAIN-CURRENT FLICKER NOISE MODELING IN nmosfets 3 Fig. 5. Transconductance to drain-current ratio of a front, / and b back, g m2 /, interface for various back-gate bias V b. where S Vfb1,2 is the flat-band voltage power spectral density of the front and back interface, respectively. If we consider the CMFs from the two interfaces, 1 is becoming S 2 Id gm1 = S Vfb S Vfb2 gm g m2 2 2 with S Vfb1,2 = q 2 kt λ N t1,2 / f W L Cox1,2 2, λ is the tunneling constant in the dielectric 0.1 nm, kt the thermal voltage, f the frequency, μ eff the effective mobility, 1,2 = α sc1,2 μ eff C ox1,2, α sc1,2 the Coulomb scattering coefficients 10 4 Vs/C, N t1,2 the volumetric oxide trap density, and C ox1,2 the oxide capacitance per unit area of the front 1 and back 2 interface, respectively. From 1 and 2, it is clear that the transistor gain g m / of both interfaces plays a crucial role on the total noise level, and it is necessary to investigate its behavior. Fig. 5 shows the transconductance to drain-current ratio of the front / and the back interface g m2 / for the same device. Both front and back g m / remain almost unchanged over drain current with the back-gate bias. In addition, they follow the same dependence on the drain current indicating a nearly constant coupling factor C 21 = g m2 / as a function of both drain current i.e., V g and back bias V b. However, for practical reasons and simplicity of use in SPICE simulation, it is better to transfer all the noise sources to the front-gate electrode, including the back interface component. To this end, one could define front-gate input-referred effective values of S Vfb,eff and eff as follows: S 2 Id gm1 = S Vfb,eff 1 + eff 3a where S Vfb,eff can be obtained from weak inversion region limits where the CNF dominates as S Vfb,eff = S Vfb1 1 + C21 2. S Vfb2 3b S Vfb1 and eff can be obtained from strong inversion region limits where CMF prevails as eff S / Vfb C21 2 S SVfb2 3c Vfb1 S Vfb1 where S Vfb2 /S Vfb1 = tox2 2 N t2/tox1 2 N t1 revealing the effect of the front- and back-gate oxide thickness and volumetric trap density ratio on the total noise level. Fig. 6. Normalized drain-current noise versus drain current symbols for nmos W/L = 1/0.08 μm, V b = 0 V, and corresponding CNF and CNF/CMF models dotted lines of the front interface. Fig. 7. Square root of input-referred gate voltage noise versus / for nmos W/L = 1/0.08 μm for various back-gate bias symbols and the corresponding linear fit straight lines. These equations indicate that the effective parameters S Vfb,eff and eff are univocally related to both front and back interface parameters and coupling factor. Fig. 6 presents the ability of the single-interface model of 3 to reproduce the normalized drain-current noise from weak to strong inversion region of operation versus drain current for back-gate bias grounded. For application purpose, following [17], it is worthwhile dealing with the square root of the front inputreferred gate voltage noise, which can be calculated from S Vg = S Id /gm1 2 as SVg = S Vfb,eff 1 + eff. 4 It is obvious from 4 that S Vg is a linear function of the ratio / and if our model approach is correct, the measured data should follow this trend. Indeed, as shown in Fig. 7, for all values of back-gate voltage V b, S Vg is proportional to /, exhibiting a slope that depends on V b.thevalues of W L S Vfb,eff and eff extracted through 4 are plotted versus V b in Fig. 8. The gate-area-normalized S Vfb,eff can be considered as constant for all back-bias conditions [Fig. 8b], which is in agreement with a constant coupling factor C 21 versus V b Fig. 5. Instead, it is found that eff increases for negative back-gate bias and tends to very small values for positive ones [Fig. 8a]. This behavior cannot be interpreted using constant Coulomb scattering coefficients α sc1,2 occurring in 2 and 3. Based on the carrier centroid dependence of α sc1,2 as in [22] and combining both the remote Coulomb scattering for each interface, we propose to generalize the CMF coefficients under

4 4 IEEE TRANSACTIONS ON ELECTRON DEVICES Fig. 8. a eff and b W L S Vfb,eff dependence for various back-gate biases for nmos W/L = 1/0.08 μm, respectively. Fig. 10. Normalized drain-current noise versus drain current symbols for nmos W/L = 1/0.08 μmandv b = 0 V for different drain and front-gate biases. Fig. 9. Average drain-current noise versus frequency for nmos W/L = 1/0.08 μm and for different drain and front-gate voltage bias but for a constant drain current 50 μa. The back-gate voltage was grounded. the symmetric forms 1 = α sc1 μ eff C ox1 X c1 + α sc2 μ eff C ox2 1 X c1 5a and 2 = α sc1 μ eff C ox1 X c2 + α sc2 μ eff C ox2 1 X c2 5b where X c1,2 are the normalized carrier centroid positions for front and back interface, respectively X c = 1 at front interface and X c = 0 at back interface. Using these expressions with 3c and extracting the centroid position by solving Poisson s equation with TCAD simulations allow obtaining the simulated trend of Fig. 8a, justifying reasonably well the experimental data behavior. B. Impact of Drain Voltage Bias We expanded the previous analysis in the nonlinear region of operation to investigate the LFN behavior. Fig. 9 shows the drain-current spectra versus frequency for nmos device with W/L = 1 μm/0.08 μm in different operation regions, i.e., various drain and front-gate voltage. Once more the spectra are 1/f -like for all biases. Same results were obtained for all drain voltage biases. The corresponding normalized drain-current noise versus normalized drain current is plotted in Fig. 10 for different regions of operation. It can be clearly seen that the different drain voltage bias data perfectly follow the linear region operation trend. In addition, Fig. 11 shows that the generalized model of 4 also allows explaining the linearity between the square root of input-referred gate voltage noise and / for Fig. 11. Square root of input gate voltage noise versus / for nmos W/L = 1/0.08 μm for various drain and front-gate bias symbols and the corresponding linear fit straight line. Fig. 12. Square root of input gate voltage noise versus /g m for two areas nmos devices symbols and the corresponding linear fit straight line. both the linear and the nonlinear regions of operation, meaning that eff is not drain-bias dependent, as already stated in [17]. C. Impact of Channel Geometry As shown in Fig. 12, where we present an example of two different gate area devices, the CMF noise component seems to depend on the channel geometry. The values of eff and S Vfb,eff were extracted for every device area measured. The extracted values are plotted versus gate width and gate length in Figs. 13 and 14, respectively. As expected, the normalized flat-band voltage spectral density remains constant for all the gate lengths and widths. However, the CMF factor eff is increasing as the gate length of the device becomes larger, while remaining constant over the channel width. This behavior indicates that the CMF influence

5 IOANNIDIS et al.: DRAIN-CURRENT FLICKER NOISE MODELING IN nmosfets 5 in the channel. The effective flat-band voltage power spectral density S Vfbeff is not dependent on either the channel length or the back-gate bias, thus it can be calculated using Fig. 13. a eff and b W L S Vfb,eff versus device width for nmos. Fig. 14. a eff and b W L S Vfb,eff versus device length for nmos, respectively. Fig. 15. eff dependence on back-gate bias for various channel lengths. is decreased in small gate lengths compared with the large ones. This trend is primarily related to the strong mobility dependence with channel length [23] that also follows a similar tendency, as shown in Fig. 14. III. NOISE MODEL UNIFICATION The final step to obtain a functional compact model is to put together in a single empirical equation the impact of every parameter on the device noise level: 1 back-bias voltage; 2 drain voltage; and 3 channel width and length. Regarding the drain voltage and the channel width, we have shown that their variation has no impact on the noise parameters eff and S Vfb,eff Figs. 11 and 13, respectively. As for the effect of V b Fig. 8 and L Fig. 14 on eff, we have found a unified empirical equation that can fit of all our data, as shown in Fig. 15 eff V b, L = 0 e V b/v L 0 /L where 0 = 6.5 V 1, V 0 = 3.42 V 1,andL 0 = 0.12 μm for the 14-nm FDSOI technology node devices that were measured. The exponential dependence of eff on V b is in agreement with the centroid modeling approach of 5 and of [24], verifying that eff is related to the carriers position S Vfbeff = q2 λkt N t,eff fwlcox,1 2 7 where N t,eff is the effective slow oxide trap volumetric density, related the front and back interface trap densities via the coupling factor of 3b as N t,eff = N t1 + C21 2 N t2. Therefore, the drain-current noise can now be modeled for all operation conditions and channel geometries as S Id = S Vfb,eff eff 8 where eff and S Vfb,eff are given by 6 and 7, respectively. The model in 8, combined with 6 and 7, can be easily used to fit drain-current noise data from other wafers of the same batch as well and extract eff and N t,eff. IV. CONCLUSION A thorough experimental study of LFN in a 14-nm FDSOI MOSFETs has been performed. The 1/f noise was found to be well described by the CNF/CMF model, for all bias conditions and channel geometries. An empirical two-parameter front-gate input-referred noise model has been developed considering only the front-interface transconductance and the dependence of the two parameters on the channel length and the back-gate bias voltage. It has been demonstrated that this new compact model is accurate in all regions of operation and for all device dimensions. Thus, it can be easily used in SPICE noise modeling for circuit simulations. REFERENCES [1] G. K. Celler and S. Cristoloveanu, Frontiers of silicon-on-insulator, J. Appl. Phys., vol. 93, no. 9, pp , [2] D. Hisamoto, T. Kaga, and E. Takeda, Impact of the vertical SOI DELTA structure on planar device technology, IEEE Trans. Electron. Devices, vol. 38, no. 6, pp , Jun [3] C. Fenouillet-Beranger et al., Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring μm 2 6T-SRAM bitcell, in Proc. IEEE IEDM, Dec. 2007, pp [4] Q. Liu et al., Ultra-thin-body and BOX UTBB fully depleted FD device integration for 22 nm node and beyond, in Proc. Symp. VLSI Technol., Jun. 2010, pp [5] F. Andrieu et al., Low leakage and low variability ultra-thin body and buried oxide UT2B SOI technology for 20 nm low power CMOS and beyond, in Proc. Symp. VLSI Technol., Jun. 2010, pp [6] C. Fenouillet-Beranger et al., Impact of a 10 nm ultra-thin BOX UTBOX and ground plane on FDSOevices for 32 nm node and below, in Proc. Eur. Solid-State Circuits Conf., Sep. 2009, pp [7] B. K. Jones, Electrical noise as a measure of quality and reliability in electronic devices, Adv. Electron. Electron Phys., vol. 87, pp , [8] C. Claeys and E. Simoen, Noise as a diagnostic tool for semiconductor material and device characterization, J. Electrochem. Soc., vol. 145, no. 6, pp , [9] K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai, and Y. Hayashi, Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude, in Proc. Symp. VLSI Technol., Jun. 2009, pp [10] K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. Onodera, The impact of RTN on performance fluctuation in CMOS logic circuits, in Proc. IEEE IRPS, Apr. 2011, pp. CR.5.1 CR.5.4.

6 6 IEEE TRANSACTIONS ON ELECTRON DEVICES [11] E. G. Ioannidis et al., Low frequency noise variability in high-k/metal gate stack 28 nm bulk and FD-SOI CMOS transistors, in Proc. IEEE IEDM, Dec. 2011, pp [12] A. L. McWhorter, Semiconductor Surface Physics, H. Kingston, Ed. Philadelphia, PA, USA: Univ. Pennsylvania Press, 1957, p [13] F. N. Hooge, 1/ f noise is no surface effect, Phys. Lett., vol. 29, no. 3, pp , [14] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors, IEEE Trans. Electron Devices, vol. 37, no. 3, pp , Mar [15] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini, Improved analysis of low frequency noise in field-effect MOS transistors, Phys. Status Solidi A, vol. 124, no. 2, pp , [16] C. A. Dimitriadis, F. V. Farmakis, G. Kamarinos, and J. Brini, Origin of low-frequency noise in polycrystalline silicon thin-film transistors, J. Appl. Phys., vol. 91, no. 2, pp , [17] E. G. Ioannidis, C. A. Dimitriadis, S. Haendler, R. A. Bianchi, J. Jomaah, and G. Ghibaudo, Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs, Solid-State Electron., vol. 76, pp , Oct [18] C. Wei, Y.-Z. Xiong, and X. Zhou, Investigation of low-frequency noise in n-channel FinFETs from weak to strong inversion, IEEE Trans. Electron Devices, vol. 56, no. 11, pp , Nov [19] C. G. Theodorou et al., Low-frequency noise sources in advanced UTBB FD-SOI MOSFETs, IEEE Trans. Electron Devices, vol. 61, no. 2, pp , Apr [20] O. Weber et al., 14 nm FDSOI technology for high speed and energy efficient applications, in Proc. Symp. VLSI Technol., Jun. 2014, pp [21] E. G. Ioannidis, S. Haendler, C. G. Theodorou, N. Planes, C. A. Dimitriadis, and G. Ghibaudo, Statistical analysis of dynamic variability in 28 nm FD-SOI MOSFETs, in Proc. 44th ESSDERC, Sep. 2014, pp [22] C. G. Theodorou et al., Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs, in Proc. ESSDERC, 2012, pp [23] M. Shin et al., Magnetoresistance mobility characterization in advanced FD-SOI n-mosfets, Solid-State Electron., vol. 103, pp , Jan [24] T. A. Karatsori et al., Analytical compact model for lightly-doped nano-scale ultra-thin body ultra-thin box SOI MOSFETs with back gate control, IEEE Trans. Electron Devices, to be published. Authors photographs and biographies not available at the time of publication.

Reliability of deep submicron MOSFETs

Invited paper Reliability of deep submicron MOSFETs Francis Balestra Abstract In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature