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1 Copyright 2009 Year IEEE. Reprinted from 2009 IEEE ELECTRON DEVICE LETTERS. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics products or services. Internal of personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to

2 668 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009 Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region Chengqing Wei, Yong-Zhong Xiong, Senior Member, IEEE, Xing Zhou, Senior Member, IEEE, Navab Singh, Subhash C. Rustagi, Senior Member, IEEE, Guo Qiang Lo, and Dim-Lee Kwong, Fellow, IEEE Abstract The low-frequency noise (LFN) in the subthreshold region of both n- and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated. The measured drain current noise spectral density shows that the LFN in this regime can be well described by the mobility-fluctuation model due to the volume-inversion conduction behavior, and the Hooge parameter is extracted. The LFN in the SNWTs with channels oriented in 010 and 110 directions is compared. It shows that the observed mobility enhancement in the 010 direction for p-type transistors leads to a corresponding increase of the LFN level in the 010 direction compared with that in the 110 direction. Index Terms Gate-all-around (GAA), low-frequency (1/f) noise, silicon nanowire, volume inversion. I. INTRODUCTION DUE to its better gate control, the gate-all-around (GAA) silicon nanowire transistor (SNWT) [1] [4] is considered an important candidate for future CMOS scaling beyond the 32-nm node. The GAA NW CMOS inverter logic gates and ring oscillators (ROs) have been fabricated and characterized in the literature [5] [8]. The noise margin and the inverter threshold voltage depend on the transitions between the subthreshold and strong-inversion regions. High noise levels in the subthreshold region (close to the threshold voltage) may disturb the normal switching behaviors and circuit performance. SNWTs have also been widely studied as chemical and biochemical sensors [8] [11]. Biosensing by SNWTs is based on the pronounced conductance changes induced by the depletion of charge carriers in the silicon body when the charged biomolecules are bound to its surface. The high noise level in the depletion (subthreshold) region may lead to reduced signal-to-noise ratios in these sensors. Manuscript received February 4, 2009; revised March 17, First published May 12, 2009; current version published May 27, This work was supported in part by the Scholarship of Chartered Semiconductor Manufacturing, Singapore, and in part by Nanyang Technological University, Singapore. The review of this letter was arranged by Editor M. Ostling. C. Wei is with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore ; the Institute of Microelectronics, A Star, Singapore ; and also with the Chartered Semiconductor Manufacturing Ltd., Singapore ( weic0002@ntu.edu.sg). Y.-Z. Xiong, N. Singh, S. C. Rustagi, G. Q. Lo, and D.-L. Kwong are with the Institute of Microelectronics, A Star, Singapore ( yongzhong@ime.a-star.edu.sg; navab@ime.a-star.edu.sg; subhash@ime.a-star. edu.sg; logq@ime.a-star.edu.sg; kwongdl@ime.a-star.edu.sg). X. Zhou is with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore ( exzhou@ntu. edu.sg). Color versions of one or more of the figures in this letter are available online at Digital Object Identifier /LED Fig. 1. (a) Schematic view of the SNWT. (b) Transfer characteristics of both the n- and p-type SNWTs with L = 90 nm at V ds = 50 mv and with channels oriented in the 010 and 110 directions, respectively. The zoom-in view of the PMOS subthreshold current from = to Aisshown in the inset. So far, only a few publications on low-frequency noise (LFN) in GAA SNWTs have been reported [12], [13]. In [12], the random telegraph noise (RTS) of p-type SNWTs in the ohmic region has been investigated. In [13], the LFN in n-type SNWTs is investigated mainly in the ohmic region, and the impact of source/drain extension is discussed. This letter concerns the LFN in GAA SNWTs biased in the subthreshold region for both n- and p-type devices. Different noise generation mechanisms from [13] are observed, and the Hooge parameter is extracted based on the mobility-fluctuation model. The impact of channel orientations ( 110 and 010 directions) on the LFN performance is also studied, and it further confirms the dominance of mobility-fluctuation LFN in the subthreshold region. II. DEVICES AND MEASUREMENTS Si-fin of 60-nm width with different gate lengths (L) defined on 8 -(100) silicon-on-insulator wafers were used as starting materials. The details of the fabrication process were presented in [4], and the schematic view of the device is shown in Fig. 1(a). The thickness of the thermally grown SiO 2 gate dielectric is 4 nm. The Si core has a cross section of rectangular shape with a height of 120 nm and width of 30 nm. For calculation purposes, the cross section of the device is treated as a circle with an equivalent radius of 40 nm. The gate lengths of the investigated devices are 90, 130, and 180 nm. Prior to noise analyses, the NW dc characteristics were measured with an HP4156C Semiconductor Parameter Analyzer. The transfer characteristics of both n- and p-type transistors with 90-nm gate length at V ds = 50 mv with channels oriented in the 110 and 010 directions are shown in Fig. 1(b) /$ IEEE

3 WEI et al.: INVESTIGATION OF LOW-FREQUENCY NOISE IN SILICON NANOWIRE MOSFETs 669 The typical device characteristics investigated have threshold voltages of 0.13 V for n-type and 0.27 V for p-type and subthreshold slopes of 60 mv/dec for n-type and 66 mv/dec for p-type transistors. LFN measurements were then performed using two battery-powered SR570 Low-Noise Current Preamplifiers and one HP35670A Dynamic Signal Analyzer to obtain the frequency spectrum. The background noise at corresponding gate voltages with all other terminals grounded was also measured and subtracted from measurements at nonzero drain biases to obtain the device LFN. III. RESULTS AND DISCUSSION In the subthreshold region, the current-conduction behavior in the SNWT is very different from that in bulk transistors. In the subthreshold region of a lightly doped GAA SNWT, the drain-current level is proportional to the area of the cylindrical cross section for a given bias condition, and volume inversion takes place [4], [14]. The carriers flow through the whole silicon body and, thus, can be considered as bulk conduction compared with the surface conduction in bulk-cmos transistors. The interaction between the oxide traps and the conduction channel is thus suppressed due to the large separation of most carriers from the interface and the oxide traps. Moreover, in the ultrascaled SNWTs with gate areas below 0.1 μm 2, only several traps, or a single trap, or even no trap would be active in the trapping and detrapping process near the Si/SiO 2 interface [13], [15]. Hence, the generation of the exact 1/f noise in a single ultrascaled SNWT biased in the subthreshold region through the carrier trapping and detrapping process and its correlated mobility scattering becomes less probable. However, the typical 1/f noise was observed in the currently studied SNWTs in the subthreshold region with no RTS noise on top of it. This may be due to the fact that, for the volume-inverted SNWTs in this regime, the Fermi level is not crossing the bandgap at the depletion layer as in the case of bulk MOSFETs and about half of the traps are full or empty and inactive in the trapping/detrapping process, or as described previously, this noactive-trap situation is due to the ultrascaled device dimension. Thus, the number-fluctuation noise is completely eliminated. However, the mobility-fluctuation noise still remains. This is evident from experiments of RTS noise in small devices, where the residual signal after the subtraction of the RTS noise still exhibits a 1/f spectrum [15]. Fig. 2(a) shows the frequency dependence of the measured drain-current noise spectral density S Id of six samples of 90-nm p-type SNWTs with channels oriented in the 110 direction, biased at V ds = 50 mv and = 3.1 na. The S Id extracted at f = 10 Hz of each curve is shown in the inset. A typical 1/f γ behavior with γ = 1.03 was obtained. The dispersion of the noise spectral density is around half decade [see the inset of Fig. 2(a)], which is significantly lower than that reported in [13], in which randomly distributed oxide traps introduce up to five orders of S Id dispersion. For volume-inverted SNWTs with the same subthreshold current, the lattice quality and mobility variations of the ultrascaled dimension of SNWTs may be the main reason for the noise magnitude dispersion. In order to obtain the average noise spectrum, 20 samples for each SNWT with the same gate length were measured. The average results of the noise spectral density are used in the following discussion. Fig. 2. (a) Drain current noise spectral density S Id of six individual p-type SNWTs in the 110 direction with L = 90 nm biased at V ds = 50 mv at constant = 3.1 na. Measured S Id dispersion at f = 10 Hz is shown in the inset. (b) Average normalized drain current spectral density at V ds = 50 mv and f = 10 Hz versus drain current for both n- and p-type SNWTs with L = 90, 130, and 180 nm, respectively. For the L = 90 nm devices, we have channels oriented in both 010 and 110 directions. The noise data of 90-nm n- and p-type SNWTs in the 110 direction are compared with the corresponding (constant (g m/ ) 2 ) in the inset. Open symbols: p-type. Solid symbols: n-type. Solid line: Fitted by (10). Fig. 2(b) shows the average normalized drain-current noise spectral density S Id /Id 2 at f = 10 Hz as a function of the drain current when sweeping the gate voltage V gs while keeping V ds constant at 50 mv for both n- and p-type SNWTs with different gate lengths and channel orientations. The normalized variations S Id /Id 2 versus exhibit a slope close to 1, which shows that the mobility-fluctuation model is involved. If the 1/f noise is due to the carrier-number fluctuations, S Id /Id 2 is independent of the drain current, and the proportional correlation between S Id /Id 2 and (g m/ ) 2 (g m is the transconductance / V gs ) should be obtained. However, as shown in the inset of Fig. 2(b), a large slope deviation between S Id /Id 2 and (g m/ ) 2 is observed in the subthreshold region, which further confirms the mobility-fluctuation mechanism. Moreover, the relative noise S Id /Id 2 at a fixed drain-current level is almost inversely proportional to L 2, which is a strong indication that the noise contribution from series resistances is negligible [16]. The empirical relation of the mobility-fluctuation model [17], [18] is given by fn with α H being the Hooge parameter and N the total number of carriers under the gate. For the studied SNWTs in the (1)

4 670 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009 subthreshold region, N is generally smaller than 20. This is the first time that the empirical relation (1) is tested for such a low N. The subthreshold current of lightly doped GAA SNWTs can be expressed as [14] = μ πr2 L n ie q(vgs ΔΦ) ( 1 e qv ds where μ is the effective mobility, R is the radius of the GAA SNWT, L is the channel length, n i is the intrinsic carrier concentration, and ΔΦ is the work function difference between the gate electrode and the almost-intrinsic silicon body. From both the surface-potential expression ψ s and Gauss law applied at the Si/SiO 2 interface, a β-dependent expression f(β) is defined as [14] f(β) = q (V gs V o V (y)) (3) with V o =ΔΦ+ ( ) q ln 8εSi q 2 n i R 2 where V (y) is the electron quasi-fermi potential at y along the channel and β is a parameter related to R and ψ s.inthe subthreshold region, β 1, f(β) ln(1 β) [14], together with (3), 1 β can be derived as ) (2) (4) 1 β = e q (V gs V o V (y)). (5) Q i (y), the carrier charge density per unit area in the channel at y, is derived in [14] as Q i (y) =4 ε Si R q 1 β β. (6) Since β 1 in the subthreshold region, substituting (4) and (5) into (6), we have Q i (y) 4 ε Si R q (1 β) =qn ir 2 e q (V gs ΔΦ V (y)). (7) Following the approach described in [19] with the help of (2) and (7), the final expression of S Id /Id 2 in the subthreshold region from the mobility-fluctuation model for SNWTs is exactly the same as that for their bulk-mos counterpart fn = α qv ds H 2μ 1 e f L e qv ds 1. (8) Since the subthreshold slope of p-type SNWTs is not as ideal as n-type ones, two ideality factors m and m related to the gate and drain biases, respectively, are added into (2) as = μ πr2 L n ie q( Vgs Δφ ) ) m (1 e q V ds m (9) which leads to the final mobility-fluctuation model in the subthreshold region as fn = α q V ds m H 2μ 1 e m f L e q V ds m 1 (10) where m = 1 and 1.1 and m = 1 and 1.03 for n- and p-type SNWTs, respectively. For devices working in the ohmic region Fig. 3. Variations of average S Id / at f = 10 Hz versus V ds for n- and p-type SNWTs in the subthreshold region with L = 90 nm oriented in the 110 direction. Symbols: Experimental data. Solid line: Fitted by (10). The normalized noise S Id /Id 2 at the same bias range is shown in the inset in the respective case. with very low drain biases V ds, (10) can be simplified as fn qμ f L 2 V ds 1. (11) The effective mobility μ is approximated from the I V data of the long-channel SNWTs and is around 150, 45, and 90 cm 2 /V s for n- and p-type SNWTs in the 110 direction and p-type SNWTs in the 010 direction, respectively, and from variations in Fig. 2(b), α H following (10) or (11) has been extracted to be α H and for the n- and p-type SNWTs, respectively, and the α H of p-type SNWTs is the same in the 110 and 010 directions, which means that α H is independent of the channel orientations. The extracted Hooge parameters are within the range reported for conventional silicon CMOS bulk devices (SiO 2 /polysilicon gate stack) and are close to the value predicted from ITRS roadmap for the 45-nm technology node [20]. S Id / versus V ds for n- and p-type devices in the subthreshold region is shown in Fig. 3. A linear increase at low V ds values is observed, and a plateau is reached for high V ds values (S Id / = and A/Hz for n- and p- type devices, respectively). The computed values of S Id / using (10) are also reported. Good agreement is observed. The normalized drain-current noise S Id /Id 2 versus V ds shown in the inset of Fig. 3 shows a similar behavior. The SNWTs with L = 90 nm have channels oriented in 110 and 010 directions, respectively. As shown in Fig. 1(b), for a fixed bias, there is no significant difference of subthreshold current (or mobility) for n-type SNWTs in two different orientations. However, the subthreshold current (or mobility) for p-type devices in the 010 orientation is found to be 2.1 times that in the 110 orientation. The extrapolated at V gs = 0.1 V and 0.22 V for n- and p-type transistors, respectively, are shown in Fig. 4(a). From (10), it is seen that S Id is proportional to μ in the channel for a given V ds and ; hence, as shown in Fig. 2(b), the magnitude of S Id for n-type transistors is almost the same in 010 and 110 orientations, whereas the S Id for p-type transistors in the 010 orientation is about twice that in the 110 orientation. This actually confirms that the mobility-fluctuation noise generation mechanism is dominant in the subthreshold region, since in the number-fluctuation model, there is no dependence of S Id on mobility at a fixed drain-current level [21]. Moreover, at a fixed-bias condition,

5 WEI et al.: INVESTIGATION OF LOW-FREQUENCY NOISE IN SILICON NANOWIRE MOSFETs 671 Fig. 4. Effect of silicon NW orientation on (a) drain current and (b) average drain-current spectral density S Id at V ds = 50 mv and f = 10 Hz. Gate voltage is fixed at 0.1 and 0.22 V for n- and p-type transistors, respectively. The devices are oriented in both 010 and 110 directions with L = 90 nm. S Id is proportional to μ 2 [from (9) and (10)]; hence, as shown in Fig. 4(b), S Id in the 010 direction is almost four times that in the 110 direction for p-type devices. Hence, stronger current and mobility enhancement in certain orientations may also cause a higher LFN level in the corresponding orientation. This will be a tradeoff for future NW applications. IV. CONCLUSION The SNWT is volume inverted in the subthreshold region, and carriers travel through the whole silicon channel body; thus, the device exhibits 1/f noise, in agreement with the mobilityfluctuation model. Moreover, if the channel orientation has an impact on the dc characteristics of the device, the LFN will also have the corresponding changes. Like in the present case, the LFN in the p-type transistor is higher for an NW channel oriented in the 010 direction than that in the 110 direction, which is consistent with the observed impact of channel orientation on its drain-current level. REFERENCES [1] F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, and S. D. Liu, 5 nm-gate nanowire FinFET, in VLSI Symp. Tech. Dig., 2004, pp [2] S. D. Suk, S. Y. Lee, S. M. Kim, E. J. Yoon, M. S. Kim, M. Li, C. W. Oh, K. H. Yeo, and S. H. Kim, High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability, in IEDM Tech. Dig., 2005, pp [3] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, and G. Q. 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